1 /* maxq.h -- Header file for MAXQ opcode table. 2 3 Copyright (C) 2004 Free Software Foundation, Inc. 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 Written by Vineet Sharma(vineets@noida.hcltech.com) 8 Inderpreet Singh (inderpreetb@noida.hcltech.com) 9 10 GDB, GAS, and the GNU binutils are free software; you can redistribute 11 them and/or modify them under the terms of the GNU General Public License 12 as published by the Free Software Foundation; either version 2, or (at 13 your option) any later version. 14 15 GDB, GAS, and the GNU binutils are distributed in the hope that they will 16 be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General 18 Public License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this file; see the file COPYING. If not, write to the Free Software 22 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 #ifndef _MAXQ20_H_ 25 #define _MAXQ20_H_ 26 27 /* This file contains the opcode table for the MAXQ10/20 processor. The table 28 has been designed on the lines of the SH processor with the following 29 fields: 30 (1) Instruction Name 31 (2) Instruction arguments description 32 (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4 33 |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8) 34 (4) Architecture supported 35 36 The Register table is also defined. It contains the following fields 37 (1) Register name 38 (2) Module Number 39 (3) Module Index 40 (4) Opcode 41 (5) Regtype 42 43 The Memory access table is defined containing the various opcodes for 44 memory access containing the following fields 45 (1) Memory access Operand Name 46 (2) Memory access Operand opcode. */ 47 48 # define MAXQ10 0x0001 49 # define MAXQ20 0x0002 50 # define MAX (MAXQ10 | MAXQ20) 51 52 /* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte: 53 NOP_DST 2nd byte: NOP_SRC. */ 54 # define NOP_FMT 1 55 # define NOP_SRC 0x3A 56 # define NOP_DST 0x5A 57 58 typedef enum 59 { 60 ZEROBIT = 0x1, /* A zero followed by 3 bits. */ 61 ONEBIT = 0x2, /* A one followed by 3 bits. */ 62 REG = 0x4, /* Register. */ 63 MEM = 0x8, /* Memory access. */ 64 IMM = 0x10, /* Immediate value. */ 65 DISP = 0x20, /* Displacement value. */ 66 BIT = 0x40, /* Bit value. */ 67 FMT = 0x80, /* The format bit. */ 68 IMMBIT = 0x100, /* An immediate bit. */ 69 FLAG = 0x200, /* A Flag. */ 70 DATA = 0x400, /* Symbol in the data section. */ 71 BIT_BUCKET = 0x800, /* FOr BIT BUCKET. */ 72 } 73 UNKNOWN_OP; 74 75 typedef enum 76 { 77 NO_ARG = 0, 78 A_IMM = 0x01, /* An 8 bit immediate value. */ 79 A_REG = 0x2, /* An 8 bit source register. */ 80 A_MEM = 0x4, /* A 7 bit destination register. */ 81 FLAG_C = 0x8, /* Carry Flag. */ 82 FLAG_NC = 0x10, /* No Carry (~C) flag. */ 83 FLAG_Z = 0x20, /* Zero Flag. */ 84 FLAG_NZ = 0x40, /* Not Zero Flag. */ 85 FLAG_S = 0x80, /* Sign Flag. */ 86 FLAG_E = 0x100, /* Equals Flag. */ 87 FLAG_NE = 0x200, /* Not Equal Flag. */ 88 ACC_BIT = 0x400, /* One of the 16 accumulator bits of the form Acc.<b>. */ 89 DST_BIT = 0x800, /* One of the 8 bits of the specified SRC. */ 90 SRC_BIT = 0x1000, /* One of the 8 bits of the specified source register. */ 91 A_BIT_0 = 0x2000, /* #0. */ 92 A_BIT_1 = 0x4000, /* #1. */ 93 A_DISP = 0x8000, /* Displacement Operand. */ 94 A_DATA = 0x10000, /* Data in the data section. */ 95 A_BIT_BUCKET = 0x200000, 96 } 97 MAX_ARG_TYPE; 98 99 typedef struct 100 { 101 char * name; /* Name of the instruction. */ 102 unsigned int op_number; /* Operand Number or the number of operands. */ 103 MAX_ARG_TYPE arg[2]; /* Types of operands. */ 104 int format; /* Format bit. */ 105 int dst[2]; /* Destination in the move instruction. */ 106 int src[2]; /* Source in the move instruction. */ 107 int arch; /* The Machine architecture. */ 108 unsigned int instr_id; /* Added for decode and dissassembly. */ 109 } 110 MAXQ20_OPCODE_INFO; 111 112 /* Structure for holding opcodes of the same name. */ 113 typedef struct 114 { 115 const MAXQ20_OPCODE_INFO *start; /* The first opcode. */ 116 const MAXQ20_OPCODE_INFO *end; /* The last opcode. */ 117 } 118 MAXQ20_OPCODES; 119 120 /* The entry into the hash table will be of the type MAXX_OPCODES. */ 121 122 /* The definition of the table. */ 123 const MAXQ20_OPCODE_INFO op_table[] = 124 { 125 /* LOGICAL OPERATIONS */ 126 /* AND src : f001 1010 ssss ssss */ 127 {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0}, 128 {REG | MEM | IMM | DISP, 0}, MAX, 0x11}, 129 /* AND Acc.<b> : 1111 1010 bbbb 1010 */ 130 {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39}, 131 /* OR src : f010 1010 ssss ssss */ 132 {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0}, 133 {REG | MEM | IMM | DISP, 0}, MAX, 0x12}, 134 /* OR Acc.<b> : 1010 1010 bbbb 1010 */ 135 {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A}, 136 /* XOR src : f011 1010 ssss ssss */ 137 {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0}, 138 {REG | MEM | IMM | DISP, 0}, MAX, 0x13}, 139 /* XOR Acc.<b> : 1011 1010 bbbb 1010 */ 140 {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B}, 141 /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */ 142 /* CPL : 1000 1010 0001 1010 */ 143 {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21}, 144 /* CPL C : 1101 1010 0010 1010 */ 145 {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D}, 146 /* NEG : 1000 1010 1001 1010 */ 147 {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29}, 148 /* SLA : 1000 1010 0010 1010 */ 149 {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22}, 150 /* SLA2: 1000 1010 0011 1010 */ 151 {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23}, 152 /* SLA4: 1000 1010 0110 1010 */ 153 {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26}, 154 /* RL : 1000 1010 0100 1010 */ 155 {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24}, 156 /* RLC : 1000 1010 0101 1010 */ 157 {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25}, 158 /* SRA : 1000 1010 1111 1010 */ 159 {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F}, 160 /* SRA2: 1000 1010 1110 1010 */ 161 {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E}, 162 /* SRA4: 1000 1010 1011 1010 */ 163 {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B}, 164 /* SR : 1000 1010 1010 1010 */ 165 {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A}, 166 /* RR : 1000 1010 1100 1010 */ 167 {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C}, 168 /* RRC : 1000 1010 1101 1010 */ 169 {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D}, 170 /* MATH OPERATIONS */ 171 /* ADD src : f100 1010 ssss ssss */ 172 {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0}, 173 {IMM | REG | MEM | DISP, 0}, MAX, 0x14}, 174 /* ADDC src : f110 1010 ssss ssss */ 175 {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0}, 176 {IMM | REG | MEM | DISP, 0}, MAX, 0x16}, 177 /* SUB src : f101 1010 ssss ssss */ 178 {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0}, 179 {IMM | REG | MEM | DISP, 0}, MAX, 0x15}, 180 /* SUBB src : f111 1010 ssss ssss */ 181 {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0}, 182 {IMM | REG | MEM | DISP, 0}, MAX, 0x17}, 183 /* BRANCHING OPERATIONS */ 184 185 /* DJNZ LC[0] src: f100 1101 ssss ssss */ 186 {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0}, 187 {IMM | REG | MEM | DISP, 0}, MAX, 0xA4}, 188 /* DJNZ LC[1] src: f101 1101 ssss ssss */ 189 {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0}, 190 {IMM | REG | MEM | DISP, 0}, MAX, 0xA5}, 191 /* CALL src : f011 1101 ssss ssss */ 192 {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0}, 193 {IMM | REG | MEM | DISP, 0}, MAX, 0xA3}, 194 /* JUMP src : f000 1100 ssss ssss */ 195 {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0}, 196 {IMM | REG | MEM | DISP, 0}, MAX, 0x50}, 197 /* JUMP C,src : f010 1100 ssss ssss */ 198 {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0}, 199 {IMM | REG | MEM | DISP, 0}, MAX, 0x52}, 200 /* JUMP NC,src: f110 1100 ssss ssss */ 201 {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0}, 202 {IMM | REG | MEM | DISP, 0}, MAX, 0x56}, 203 /* JUMP Z,src : f001 1100 ssss ssss */ 204 {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0}, 205 {IMM | REG | MEM | DISP, 0}, MAX, 0x51}, 206 /* JUMP NZ,src: f101 1100 ssss ssss */ 207 {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0}, 208 {IMM | REG | MEM | DISP, 0}, MAX, 0x55}, 209 /* JUMP E,src : 0011 1100 ssss ssss */ 210 {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53}, 211 /* JUMP NE,src: 0111 1100 ssss ssss */ 212 {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57}, 213 /* JUMP S,src : f100 1100 ssss ssss */ 214 {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0}, 215 {IMM | REG | MEM | DISP, 0}, MAX, 0x54}, 216 /* RET : 1000 1100 0000 1101 */ 217 {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68}, 218 /* RET C : 1010 1100 0000 1101 */ 219 {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A}, 220 /* RET NC : 1110 1100 0000 1101 */ 221 {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E}, 222 /* RET Z : 1001 1100 0000 1101 */ 223 {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69}, 224 /* RET NZ : 1101 1100 0000 1101 */ 225 {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D}, 226 /* RET S : 1100 1100 0000 1101 */ 227 {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C}, 228 /* RETI : 1000 1100 1000 1101 */ 229 {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78}, 230 /* ADDED ACCORDING TO NEW SPECIFICATION */ 231 232 /* RETI C : 1010 1100 1000 1101 */ 233 {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A}, 234 /* RETI NC : 1110 1100 1000 1101 */ 235 {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E}, 236 /* RETI Z : 1001 1100 1000 1101 */ 237 {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79}, 238 /* RETI NZ : 1101 1100 1000 1101 */ 239 {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D}, 240 /* RETI S : 1100 1100 1000 1101 */ 241 {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C}, 242 /* MISCELLANEOUS INSTRUCTIONS */ 243 /* CMP src : f111 1000 ssss ssss */ 244 {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0}, 245 {REG | MEM | IMM | DISP, 0}, MAX, 0xD7}, 246 /* DATA TRANSFER OPERATIONS */ 247 /* XCH : 1000 1010 1000 1010 */ 248 {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28}, 249 /* XCHN : 1000 1010 0111 1010 */ 250 {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27}, 251 /* PUSH src : f000 1101 ssss ssss */ 252 {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0}, 253 {IMM | REG | MEM | DISP, 0}, MAX, 0xA0}, 254 /* POP dst : 1ddd dddd 0000 1101 */ 255 {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0}, 256 /* Added according to new spec */ 257 /* POPI dst : 1ddd dddd 1000 1101 */ 258 {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0}, 259 /* MOVE dst,src: fddd dddd ssss ssss */ 260 {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT, 261 {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80}, 262 /* BIT OPERATIONS */ 263 /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */ 264 {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E}, 265 /* MOVE C,#0 : 1101 1010 0000 1010 */ 266 {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D}, 267 /* MOVE C,#1 : 1101 1010 0001 1010 */ 268 {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D}, 269 /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */ 270 {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F}, 271 /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */ 272 {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40}, 273 /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */ 274 {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41}, 275 /* MOVE C,src.<b> : fbbb 0111 ssss ssss */ 276 {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97}, 277 /* NOP : 1101 1010 0011 1010 */ 278 {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D}, 279 {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00} 280 }; 281 282 /* All the modules. */ 283 284 #define MOD0 0x0 285 #define MOD1 0x1 286 #define MOD2 0x2 287 #define MOD3 0x3 288 #define MOD4 0x4 289 #define MOD5 0x5 290 #define MOD6 0x6 291 #define MOD7 0x7 292 #define MOD8 0x8 293 #define MOD9 0x9 294 #define MODA 0xa 295 #define MODB 0xb 296 #define MODC 0xc 297 #define MODD 0xd 298 #define MODE 0xe 299 #define MODF 0xf 300 301 /* Added according to new specification. */ 302 #define MOD10 0x10 303 #define MOD11 0x11 304 #define MOD12 0x12 305 #define MOD13 0x13 306 #define MOD14 0x14 307 #define MOD15 0x15 308 #define MOD16 0x16 309 #define MOD17 0x17 310 #define MOD18 0x18 311 #define MOD19 0x19 312 #define MOD1A 0x1a 313 #define MOD1B 0x1b 314 #define MOD1C 0x1c 315 #define MOD1D 0x1d 316 #define MOD1E 0x1e 317 #define MOD1F 0x1f 318 319 /* - Peripheral Register Modules - */ 320 /* Serial Register Modules. */ 321 #define CTRL MOD8 /* For the module containing the control registers. */ 322 #define ACC MOD9 /* For the module containing the 16 accumulators. */ 323 #define Act_ACC MODA /* For the module containing the active accumulator. */ 324 #define PFX MODB /* For the module containing the prefix registers. */ 325 #define IP MODC /* For the module containing the instruction pointer register. */ 326 #define SPIV MODD /* For the module containing the stack pointer and the interrupt vector. */ 327 #define LC MODD /* For the module containing the loop counters and HILO registers. */ 328 #define DP MODF /* For the module containig the data pointer registers. */ 329 330 /* Register Types. */ 331 typedef enum _Reg_type 332 { Reg_8R, /* 8 bit register. read only. */ 333 Reg_16R, /* 16 bit register, read only. */ 334 Reg_8W, /* 8 bit register, both read and write. */ 335 Reg_16W /* 16 bit register, both read and write. */ 336 } 337 Reg_type; 338 339 /* Register Structure. */ 340 typedef struct reg 341 { 342 char *reg_name; /* Register name. */ 343 short int Mod_name; /* The module name. */ 344 short int Mod_index; /* The module index. */ 345 int opcode; /* The opcode of the register. */ 346 Reg_type rtype; /* 8 bit/16 bit and read only/read write. */ 347 int arch; /* The Machine architecture. */ 348 } 349 reg_entry; 350 351 reg_entry *new_reg_table = NULL; 352 int num_of_reg = 0; 353 354 typedef struct 355 { 356 char *rname; 357 int rindex; 358 } 359 reg_index; 360 361 /* Register Table description. */ 362 reg_entry system_reg_table[] = 363 { 364 /* Serial Registers */ 365 /* MODULE 8 Registers : I call them the control registers. */ 366 /* Accumulator Pointer CTRL[0h] */ 367 { 368 "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX}, 369 /* Accumulator Pointer Control Register : CTRL[1h] */ 370 371 { 372 "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX}, 373 /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */ 374 { 375 "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX}, 376 /* Interrupt and Control Register : CTRL[5h] */ 377 { 378 "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX}, 379 /* Interrupt Mask Register : CTRL[6h] */ 380 { 381 "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX}, 382 /* Interrupt System Control : CTRL[8h] */ 383 { 384 "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX}, 385 /* Interrupt Identification Register : CTRL[Bh] */ 386 { 387 "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX}, 388 /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */ 389 { 390 "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX}, 391 /* Watchdog Control Register : CTRL[Fh] */ 392 { 393 "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX}, 394 /* The 16 accumulator registers : ACC[0h-Fh] */ 395 { 396 "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20}, 397 { 398 "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20}, 399 { 400 "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20}, 401 { 402 "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20}, 403 { 404 "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20}, 405 { 406 "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20}, 407 { 408 "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20}, 409 { 410 "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20}, 411 { 412 "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20}, 413 { 414 "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20}, 415 { 416 "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20}, 417 { 418 "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20}, 419 { 420 "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20}, 421 { 422 "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20}, 423 { 424 "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20}, 425 { 426 "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20}, 427 /* The Active Accumulators : Act_Acc[0h-1h] */ 428 { 429 "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20}, 430 { 431 "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20}, 432 /* The 16 accumulator registers : ACC[0h-Fh] */ 433 { 434 "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10}, 435 { 436 "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10}, 437 { 438 "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10}, 439 { 440 "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10}, 441 { 442 "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10}, 443 { 444 "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10}, 445 { 446 "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10}, 447 { 448 "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10}, 449 { 450 "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10}, 451 { 452 "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10}, 453 { 454 "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10}, 455 { 456 "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10}, 457 { 458 "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10}, 459 { 460 "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10}, 461 { 462 "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10}, 463 { 464 "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10}, 465 /* The Active Accumulators : Act_Acc[0h-1h] */ 466 { 467 "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10}, 468 /* The Active Accumulators : Act_Acc[0h-1h] */ 469 { 470 "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10}, 471 /* The Prefix Registers : PFX[0h,2h] */ 472 { 473 "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX}, 474 { 475 "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX}, 476 { 477 "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX}, 478 { 479 "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX}, 480 { 481 "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX}, 482 { 483 "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX}, 484 { 485 "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX}, 486 { 487 "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX}, 488 /* The Instruction Pointer Registers : IP[0h,8h] */ 489 { 490 "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX}, 491 /* The Stack Pointer Registers : SPIV[1h,9h] */ 492 { 493 "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX}, 494 /* The Interrupt Vector Registers : SPIV[2h,Ah] */ 495 { 496 "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX}, 497 /* ADDED for New Specification */ 498 499 /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */ 500 { 501 "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX}, 502 { 503 "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX}, 504 /* MODULE Eh Whole Column has changed */ 505 506 { 507 "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX}, 508 { 509 "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX}, 510 { 511 "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX}, 512 { 513 "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX}, 514 { 515 "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX}, 516 { 517 "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX}, 518 { 519 "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX}, 520 { 521 "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX}, 522 { 523 "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX}, 524 /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */ 525 { 526 "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX}, 527 { 528 "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX}, 529 }; 530 typedef struct 531 { 532 char *name; 533 int type; 534 } 535 match_table; 536 537 #define GPIO0 0x00 /* Gerneral Purpose I/O Module 0. */ 538 #define GPIO1 0x01 /* Gerneral Purpose I/O Module 1. */ 539 #define RTC 0x00 /* Real Time Clock Module. */ 540 #define MAC 0x02 /* Hardware Multiplier Module. */ 541 #define SER0 0x02 /* Contains the UART Registers. */ 542 #define SPI 0x03 /* Serial Pheripheral Interface Module. */ 543 #define OWBM 0x03 /* One Wire Bus Module. */ 544 #define SER1 0x03 /* Contains the UART Registers. */ 545 #define TIMER20 0x03 /* Timer Counter Module 2. */ 546 #define TIMER21 0x04 /* Timer Counter Module 2. */ 547 #define JTAGD 0x03 /* In-Circuit Debugging Support. */ 548 #define LCD 0x03 /* LCD register Modules. */ 549 550 /* Plugable modules register table f. */ 551 552 reg_entry peripheral_reg_table[] = 553 { 554 /* -------- The GPIO Module Registers -------- */ 555 /* Port n Output Registers : GPIO[0h-4h] */ 556 { 557 "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX}, 558 { 559 "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX}, 560 { 561 "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX}, 562 { 563 "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX}, 564 /* External Interrupt Flag Register : GPIO[6h] */ 565 { 566 "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX}, 567 /* External Interrupt Enable Register : GPIO[7h] */ 568 { 569 "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX}, 570 /* Port n Input Registers : GPIO[8h-Bh] */ 571 { 572 "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX}, 573 { 574 "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX}, 575 { 576 "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX}, 577 { 578 "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX}, 579 { 580 "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX}, 581 /* Port n Direction Registers : GPIO[Ch-Fh] */ 582 { 583 "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX}, 584 { 585 "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX}, 586 { 587 "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX}, 588 { 589 "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX}, 590 /* -------- Real Time Counter Module RTC -------- */ 591 /* RTC Control Register : [01h] */ 592 { 593 "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX}, 594 /* RTC Seconds High [02h] */ 595 { 596 "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX}, 597 /* RTC Seconds Low [03h] */ 598 { 599 "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX}, 600 /* RTC Subsecond Register [04h] */ 601 { 602 "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX}, 603 /* RTC Alarm seconds high [05h] */ 604 { 605 "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX}, 606 /* RTC Alarm seconds high [06h] */ 607 { 608 "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX}, 609 /* RTC Subsecond Alarm Register [07h] */ 610 { 611 "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX}, 612 /* -------- The GPIO Module Registers -------- */ 613 /* Port n Output Registers : GPIO[0h-4h] */ 614 { 615 "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX}, 616 { 617 "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX}, 618 { 619 "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX}, 620 { 621 "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX}, 622 /* External Interrupt Flag Register : GPIO[6h] */ 623 { 624 "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX}, 625 /* External Interrupt Enable Register : GPIO[7h] */ 626 { 627 "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX}, 628 /* Port n Input Registers : GPIO[8h-Bh] */ 629 { 630 "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX}, 631 { 632 "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX}, 633 { 634 "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX}, 635 { 636 "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX}, 637 { 638 "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX}, 639 /* Port n Direction Registers : GPIO[Ch-Fh] */ 640 { 641 "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX}, 642 { 643 "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX}, 644 { 645 "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX}, 646 { 647 "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX}, 648 #if 0 649 /* Supply Boltage Check Register */ 650 { 651 "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX}, 652 /* Wake up output register */ 653 { 654 "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX}, 655 #endif /* */ 656 657 /* -------- MAC Hardware multiplier module -------- */ 658 /* MAC Hardware Multiplier control register: [01h] */ 659 { 660 "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX}, 661 /* MAC Multiplier Operand A Register [02h] */ 662 { 663 "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX}, 664 /* MAC Multiplier Operand B Register [03h] */ 665 { 666 "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX}, 667 /* MAC Multiplier Accumulator 2 Register [04h] */ 668 { 669 "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX}, 670 /* MAC Multiplier Accumulator 1 Register [05h] */ 671 { 672 "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX}, 673 /* MAC Multiplier Accumulator 0 Register [06h] */ 674 { 675 "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX}, 676 /* -------- The Serial I/O module SER -------- */ 677 /* UART registers */ 678 /* Serial Port Control Register : SER[6h] */ 679 { 680 "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX}, 681 /* Serial Data Buffer Register : SER[7h] */ 682 { 683 "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX}, 684 /* Serial Port Mode Register : SER[4h] */ 685 { 686 "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX}, 687 /* Serial Port Phase Register : SER[4h] */ 688 { 689 "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX}, 690 /* ------ LCD Display Module ---------- */ 691 { 692 "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX}, 693 { 694 "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX}, 695 { 696 "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX}, 697 { 698 "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX}, 699 { 700 "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX}, 701 { 702 "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX}, 703 { 704 "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX}, 705 { 706 "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX}, 707 { 708 "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX}, 709 { 710 "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX}, 711 { 712 "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX}, 713 { 714 "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX}, 715 { 716 "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX}, 717 { 718 "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX}, 719 { 720 "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX}, 721 { 722 "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX}, 723 { 724 "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX}, 725 { 726 "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX}, 727 { 728 "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX}, 729 /* -------- SPI registers -------- */ 730 /* SPI data buffer Register : SER[7h] */ 731 { 732 "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX}, 733 /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */ 734 { 735 "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX}, 736 /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read 737 only. */ 738 { 739 "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX}, 740 /* SPI Clock Register : SER[Ah] */ 741 { 742 "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX}, 743 /* -------- One Wire Bus Master OWBM -------- */ 744 /* OWBM One Wire address Register register: [01h] */ 745 { 746 "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX}, 747 /* OWBM One Wire Data register: [02h] */ 748 { 749 "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX}, 750 /* -------- The Serial I/O module SER -------- */ 751 /* UART registers */ 752 /* Serial Port Control Register : SER[6h] */ 753 { 754 "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX}, 755 /* Serial Data Buffer Register : SER[7h] */ 756 { 757 "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX}, 758 /* Serial Port Mode Register : SER[4h] */ 759 { 760 "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX}, 761 /* Serial Port Phase Register : SER[4h] */ 762 { 763 "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX}, 764 /* -------- Timer/Counter 2 Module -------- */ 765 /* Timer 2 configuration Register : TC[3h] */ 766 { 767 "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX}, 768 { 769 "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX}, 770 { 771 "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX}, 772 { 773 "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX}, 774 { 775 "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX}, 776 { 777 "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX}, 778 { 779 "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX}, 780 { 781 "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX}, 782 { 783 "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX}, 784 /* Timer 2-1 configuration Register : TC[4h] */ 785 786 { 787 "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX}, 788 { 789 "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX}, 790 { 791 "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX}, 792 { 793 "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX}, 794 { 795 "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX}, 796 { 797 "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX}, 798 { 799 "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX}, 800 { 801 "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX}, 802 { 803 "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX}, 804 { 805 "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX}, 806 { 807 "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX}, 808 { 809 "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX}, 810 { 811 "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX}, 812 { 813 "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX}, 814 { 815 "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX}, 816 { 817 "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX}, 818 { 819 "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX}, 820 { 821 "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX}, 822 { 823 NULL, 0, 0, 0, 0, 0} 824 }; 825 826 /* Memory access argument. */ 827 struct mem_access 828 { 829 char *name; /* Name of the Memory access operand. */ 830 int opcode; /* Its corresponding opcode. */ 831 }; 832 typedef struct mem_access mem_access; 833 834 /* The Memory table for accessing the data memory through particular registers. */ 835 struct mem_access mem_table[] = 836 { 837 /* The Pop Operation on the stack. */ 838 {"@SP--", 0x0d}, 839 /* Data Pointer 0 */ 840 {"@DP[0]", 0x0f}, 841 /* Data Ponter 1 */ 842 {"@DP[1]", 0x4f}, 843 /* Data Pointer 0 post increment */ 844 {"@DP[0]++", 0x1f}, 845 /* Data Pointer 1 post increment */ 846 {"@DP[1]++", 0x5f}, 847 /* Data Pointer 0 post decrement */ 848 {"@DP[0]--", 0x2f}, 849 /* Data Pointer 1 post decrement */ 850 {"@DP[1]--", 0x6f}, 851 /* ADDED According to New Specification. */ 852 853 {"@BP[OFFS]", 0x0E}, 854 {"@BP[OFFS++]", 0x1E}, 855 {"@BP[OFFS--]", 0x2E}, 856 {"NUL", 0x76}, 857 {"@++SP", 0x0D}, 858 {"@BP[++OFFS]", 0x1E}, 859 {"@BP[--OFFS]", 0x2E}, 860 {"@++DP[0]", 0x1F}, 861 {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F} 862 }; 863 864 /* Register bit argument. */ 865 struct reg_bit 866 { 867 reg_entry *reg; 868 int bit; 869 }; 870 typedef struct reg_bit reg_bit; 871 872 /* There are certain names given to particular bits of some registers. 873 These will be taken care of here. */ 874 struct bit_name 875 { 876 char *name; 877 char *reg_bit; 878 }; 879 typedef struct bit_name bit_name; 880 881 bit_name bit_table[] = 882 { 883 { 884 "RI", "SCON.0"}, 885 /* FOr APC */ 886 { 887 "MOD0", "APC.0"}, 888 { 889 "MOD1", "APC.1"}, 890 { 891 "MOD2", "APC.2"}, 892 { 893 "IDS", "APC.6"}, 894 { 895 "CLR", "APC.6"}, 896 /* For PSF */ 897 { 898 "E", "PSF.0"}, 899 { 900 "C", "PSF.1"}, 901 { 902 "OV", "PSF.2"}, 903 { 904 "S", "PSF.6"}, 905 { 906 "Z", "PSF.7"}, 907 /* For IC */ 908 909 { 910 "IGE", "IC.0"}, 911 { 912 "INS", "IC.1"}, 913 { 914 "CGDS", "IC.5"}, 915 /* For IMR */ 916 917 { 918 "IM0", "IMR.0"}, 919 { 920 "IM1", "IMR.1"}, 921 { 922 "IM2", "IMR.2"}, 923 { 924 "IM3", "IMR.3"}, 925 { 926 "IM4", "IMR.4"}, 927 { 928 "IM5", "IMR.5"}, 929 { 930 "IMS", "IMR.7"}, 931 /* For SC */ 932 { 933 "PWL", "SC.1"}, 934 { 935 "ROD", "SC.2"}, 936 { 937 "UPA", "SC.3"}, 938 { 939 "CDA0", "SC.4"}, 940 { 941 "CDA1", "SC.5"}, 942 /* For IIR */ 943 944 { 945 "II0", "IIR.0"}, 946 { 947 "II1", "IIR.1"}, 948 { 949 "II2", "IIR.2"}, 950 { 951 "II3", "IIR.3"}, 952 { 953 "II4", "IIR.4"}, 954 { 955 "II5", "IIR.5"}, 956 { 957 "IIS", "IIR.7"}, 958 /* For CKCN */ 959 960 { 961 "CD0", "CKCN.0"}, 962 { 963 "CD1", "CKCN.1"}, 964 { 965 "PMME", "CKCN.2"}, 966 { 967 "SWB", "CKCN.3"}, 968 { 969 "STOP", "CKCN.4"}, 970 { 971 "RGMD", "CKCN.5"}, 972 { 973 "RGSL", "CKCN.6"}, 974 /* For WDCN */ 975 976 { 977 "RWT", "WDCN.0"}, 978 { 979 "EWT", "WDCN.1"}, 980 { 981 "WTRF", "WDCN.2"}, 982 { 983 "WDIF", "WDCN.3"}, 984 { 985 "WD0", "WDCN.4"}, 986 { 987 "WD1", "WDCN.5"}, 988 { 989 "EWDI", "WDCN.6"}, 990 { 991 "POR", "WDCN.7"}, 992 /* For DPC */ 993 994 { 995 "DPS0", "DPC.0"}, 996 { 997 "DPS1", "DPC.1"}, 998 { 999 "WBS0", "DPC.2"}, 1000 { 1001 "WBS1", "DPC.3"}, 1002 { 1003 "WBS2", "DPC.4"}, 1004 1005 /* For SCON */ 1006 { 1007 "TI", "SCON.1"}, 1008 { 1009 "RB8", "SCON.2"}, 1010 { 1011 "TB8", "SCON.3"}, 1012 { 1013 "REN", "SCON.4"}, 1014 { 1015 "SM2", "SCON.5"}, 1016 { 1017 "SM1", "SCON.6"}, 1018 { 1019 "SM0", "SCON.7"}, 1020 { 1021 "FE", "SCON.7"} 1022 }; 1023 1024 const char *LSInstr[] = 1025 { 1026 "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP", 1027 "DJNZ", "CALL", NULL 1028 }; 1029 1030 typedef enum 1031 { 1032 DST, 1033 SRC, 1034 BOTH, 1035 } 1036 type1; 1037 1038 struct mem_access_syntax 1039 { 1040 char name[12]; /* Name of the Memory access operand. */ 1041 type1 type; 1042 char *invalid_op[5]; 1043 }; 1044 typedef struct mem_access_syntax mem_access_syntax; 1045 1046 /* The Memory Access table for accessing the data memory through particular 1047 registers. */ 1048 const mem_access_syntax mem_access_syntax_table[] = 1049 { 1050 { 1051 "@SP--", SRC, 1052 { 1053 NULL, NULL, NULL, NULL, NULL}}, 1054 /* Data Pointer 0 */ 1055 { 1056 "@DP[0]", BOTH, 1057 { 1058 "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}}, 1059 /* Data Ponter 1 */ 1060 { 1061 "@DP[1]", BOTH, 1062 { 1063 "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}}, 1064 /* Data Pointer 0 post increment */ 1065 { 1066 "@DP[0]++", SRC, 1067 { 1068 NULL, NULL, NULL, NULL, NULL}}, 1069 /* Data Pointer 1 post increment */ 1070 { 1071 "@DP[1]++", SRC, 1072 { 1073 NULL, NULL, NULL, NULL, NULL}}, 1074 /* Data Pointer 0 post decrement */ 1075 { 1076 "@DP[0]--", SRC, 1077 { 1078 NULL, NULL, NULL, NULL, NULL}}, 1079 /* Data Pointer 1 post decrement */ 1080 { 1081 "@DP[1]--", SRC, 1082 { 1083 NULL, NULL, NULL, NULL, NULL}}, 1084 /* ADDED According to New Specification */ 1085 1086 { 1087 "@BP[OFFS]", BOTH, 1088 { 1089 "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}}, 1090 { 1091 "@BP[OFFS++]", SRC, 1092 { 1093 NULL, NULL, NULL, NULL, NULL}}, 1094 { 1095 "@BP[OFFS--]", SRC, 1096 { 1097 NULL, NULL, NULL, NULL, NULL}}, 1098 { 1099 "NUL", DST, 1100 { 1101 NULL, NULL, NULL, NULL, NULL}}, 1102 { 1103 "@++SP", DST, 1104 { 1105 NULL, NULL, NULL, NULL, NULL}}, 1106 { 1107 "@BP[++OFFS]", DST, 1108 { 1109 "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}}, 1110 { 1111 "@BP[--OFFS]", DST, 1112 { 1113 "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}}, 1114 { 1115 "@++DP[0]", DST, 1116 { 1117 "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}}, 1118 { 1119 "@++DP[1]", DST, 1120 { 1121 "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}}, 1122 { 1123 "@--DP[0]", DST, 1124 { 1125 "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}}, 1126 { 1127 "@--DP[1]", DST, 1128 { 1129 "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}} 1130 }; 1131 1132 #endif 1133