1module test(
2	input clk, wen,
3	input [7:0] uns,
4	input signed [7:0] a, b,
5	input signed [23:0] c,
6	input signed [2:0] sel,
7	output [15:0] s, d, y, z, u, q, p, mul, div, mod, mux, And, Or, Xor, eq, neq, gt, lt, geq, leq, eqx, shr, sshr, shl, sshl, Land, Lor, Lnot, Not, Neg, pos, Andr, Orr, Xorr, Xnorr, Reduce_bool,
8        output [7:0] PMux
9);
10        //initial begin
11          //$display("shr = %b", shr);
12        //end
13	assign s = a+{b[6:2], 2'b1};
14	assign d = a-b;
15	assign y = x;
16	assign z[7:0] = s+d;
17	assign z[15:8] = s-d;
18        assign p = a & b | x;
19        assign mul = a * b;
20        assign div = a / b;
21        assign mod = a % b;
22        assign mux = x[0] ? a : b;
23        assign And = a & b;
24        assign Or = a | b;
25        assign Xor = a ^ b;
26        assign Not = ~a;
27        assign Neg = -a;
28        assign eq = a == b;
29        assign neq = a != b;
30        assign gt = a > b;
31        assign lt = a < b;
32        assign geq = a >= b;
33        assign leq = a <= b;
34        assign eqx = a === b;
35        assign shr = a >> b; //0111111111000000
36        assign sshr = a >>> b;
37        assign shl = a << b;
38        assign sshl = a <<< b;
39        assign Land = a && b;
40        assign Lor = a || b;
41        assign Lnot = !a;
42        assign pos = $signed(uns);
43        assign Andr = &a;
44        assign Orr = |a;
45        assign Xorr = ^a;
46        assign Xnorr = ~^a;
47        always @*
48          if(!a) begin
49             Reduce_bool = a;
50          end else begin
51             Reduce_bool = b;
52          end
53        //always @(sel or c or a)
54        //  begin
55        //    case (sel)
56        //      3'b000: PMux = a;
57        //      3'b001: PMux = c[7:0];
58        //      3'b010: PMux = c[15:8];
59        //      3'b100: PMux = c[23:16];
60        //    endcase
61        //  end
62
63endmodule
64