1 /* $OpenBSD: bereg.h,v 1.5 2022/01/09 05:42:58 jsg Exp $ */ 2 /* $NetBSD: bereg.h,v 1.4 2000/07/24 04:28:51 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 /* 59 * BE Global registers 60 */ 61 #if 0 62 struct be_bregs { 63 u_int32_t xif_cfg; /* XIF config */ 64 u_int32_t _unused[63]; /* reserved */ 65 u_int32_t stat; /* status, clear on read */ 66 u_int32_t imask; /* interrupt mask */ 67 u_int32_t _unused2[64]; /* reserved */ 68 u_int32_t tx_swreset; /* tx software reset */ 69 u_int32_t tx_cfg; /* tx config */ 70 u_int32_t ipkt_gap1; /* inter-packet gap 1 */ 71 u_int32_t ipkt_gap2; /* inter-packet gap 2 */ 72 u_int32_t attempt_limit; /* tx attempt limit */ 73 u_int32_t stime; /* tx slot time */ 74 u_int32_t preamble_len; /* size of tx preamble */ 75 u_int32_t preamble_pattern; /* pattern for tx preamble */ 76 u_int32_t tx_sframe_delim; /* tx delimiter */ 77 u_int32_t jsize; /* jam length */ 78 u_int32_t tx_pkt_max; /* tx max pkt size */ 79 u_int32_t tx_pkt_min; /* tx min pkt size */ 80 u_int32_t peak_attempt; /* count of tx peak attempts */ 81 u_int32_t dt_ctr; /* tx defer timer */ 82 u_int32_t nc_ctr; /* tx normal collision cntr */ 83 u_int32_t fc_ctr; /* tx first-collision cntr */ 84 u_int32_t ex_ctr; /* tx excess-collision cntr */ 85 u_int32_t lt_ctr; /* tx late-collision cntr */ 86 u_int32_t rand_seed; /* tx random number seed */ 87 u_int32_t tx_smachine; /* tx state machine */ 88 u_int32_t _unused3[44]; /* reserved */ 89 u_int32_t rx_swreset; /* rx software reset */ 90 u_int32_t rx_cfg; /* rx config register */ 91 u_int32_t rx_pkt_max; /* rx max pkt size */ 92 u_int32_t rx_pkt_min; /* rx min pkt size */ 93 u_int32_t mac_addr2; /* ethernet address 2 (MSB) */ 94 u_int32_t mac_addr1; /* ethernet address 1 */ 95 u_int32_t mac_addr0; /* ethernet address 0 (LSB) */ 96 u_int32_t fr_ctr; /* rx frame receive cntr */ 97 u_int32_t gle_ctr; /* rx giant-len error cntr */ 98 u_int32_t unale_ctr; /* rx unaligned error cntr */ 99 u_int32_t rcrce_ctr; /* rx CRC error cntr */ 100 u_int32_t rx_smachine; /* rx state machine */ 101 u_int32_t rx_cvalid; /* rx code violation */ 102 u_int32_t _unused4; /* reserved */ 103 u_int32_t htable3; /* hash table 3 */ 104 u_int32_t htable2; /* hash table 2 */ 105 u_int32_t htable1; /* hash table 1 */ 106 u_int32_t htable0; /* hash table 0 */ 107 u_int32_t afilter2; /* address filter 2 */ 108 u_int32_t afilter1; /* address filter 1 */ 109 u_int32_t afilter0; /* address filter 0 */ 110 u_int32_t afilter_mask; /* address filter mask */ 111 }; 112 #endif 113 /* register indices: */ 114 #define BE_BRI_XIFCFG (0*4) 115 #define BE_BRI_STAT (64*4) 116 #define BE_BRI_IMASK (65*4) 117 #define BE_BRI_TXCFG (131*4) 118 #define BE_BRI_JSIZE (139*4) 119 #define BE_BRI_NCCNT (144*4) 120 #define BE_BRI_FCCNT (145*4) 121 #define BE_BRI_EXCNT (146*4) 122 #define BE_BRI_LTCNT (147*4) 123 #define BE_BRI_RANDSEED (148*4) 124 #define BE_BRI_RXCFG (195*4) 125 #define BE_BRI_MACADDR2 (198*4) 126 #define BE_BRI_MACADDR1 (199*4) 127 #define BE_BRI_MACADDR0 (200*4) 128 #define BE_BRI_HASHTAB3 (208*4) 129 #define BE_BRI_HASHTAB2 (209*4) 130 #define BE_BRI_HASHTAB1 (210*4) 131 #define BE_BRI_HASHTAB0 (211*4) 132 133 /* be_bregs.xif_cfg: XIF config. */ 134 #define BE_BR_XCFG_ODENABLE 0x00000001 /* output driver enable */ 135 #define BE_BR_XCFG_RESV 0x00000002 /* reserved, write as 1 */ 136 #define BE_BR_XCFG_MLBACK 0x00000004 /* loopback-mode mii enable */ 137 #define BE_BR_XCFG_SMODE 0x00000008 /* enable serial mode */ 138 139 /* be_bregs.stat: status, clear on read. */ 140 #define BE_BR_STAT_GOTFRAME 0x00000001 /* received a frame */ 141 #define BE_BR_STAT_RCNTEXP 0x00000002 /* rx frame cntr expired */ 142 #define BE_BR_STAT_ACNTEXP 0x00000004 /* align-error cntr expired */ 143 #define BE_BR_STAT_CCNTEXP 0x00000008 /* crc-error cntr expired */ 144 #define BE_BR_STAT_LCNTEXP 0x00000010 /* length-error cntr expired */ 145 #define BE_BR_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ 146 #define BE_BR_STAT_CVCNTEXP 0x00000040 /* code-violation cntr exprd */ 147 #define BE_BR_STAT_SENTFRAME 0x00000100 /* transmitted a frame */ 148 #define BE_BR_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ 149 #define BE_BR_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ 150 #define BE_BR_STAT_NCNTEXP 0x00000800 /* normal-collision cntr exp */ 151 #define BE_BR_STAT_ECNTEXP 0x00001000 /* excess-collision cntr exp */ 152 #define BE_BR_STAT_LCCNTEXP 0x00002000 /* late-collision cntr exp */ 153 #define BE_BR_STAT_FCNTEXP 0x00004000 /* first-collision cntr exp */ 154 #define BE_BR_STAT_DTIMEXP 0x00008000 /* defer-timer expired */ 155 #define BE_BR_STAT_BITS "\020" \ 156 "\01GOTFRAME\02RCNTEXP\03ACNTEXP" \ 157 "\04CCNTEXP\05LCNTEXP\06RFIFOVF" \ 158 "\07CVCNTEXP\011SENTFRAME\012TFIFO_UND" \ 159 "\013MAXPKTERR\014NCNTEXP\015ECNTEXP" \ 160 "\016LCCNTEXP\017FCNTEXP\020DTIMEXP" 161 162 /* be_bregs.imask: interrupt mask. */ 163 #define BE_BR_IMASK_GOTFRAME 0x00000001 /* received a frame */ 164 #define BE_BR_IMASK_RCNTEXP 0x00000002 /* rx frame cntr expired */ 165 #define BE_BR_IMASK_ACNTEXP 0x00000004 /* align-error cntr expired */ 166 #define BE_BR_IMASK_CCNTEXP 0x00000008 /* crc-error cntr expired */ 167 #define BE_BR_IMASK_LCNTEXP 0x00000010 /* length-error cntr expired */ 168 #define BE_BR_IMASK_RFIFOVF 0x00000020 /* rx fifo overflow */ 169 #define BE_BR_IMASK_CVCNTEXP 0x00000040 /* code-violation cntr exprd */ 170 #define BE_BR_IMASK_SENTFRAME 0x00000100 /* transmitted a frame */ 171 #define BE_BR_IMASK_TFIFO_UND 0x00000200 /* tx fifo underrun */ 172 #define BE_BR_IMASK_MAXPKTERR 0x00000400 /* max-packet size error */ 173 #define BE_BR_IMASK_NCNTEXP 0x00000800 /* normal-collision cntr exp */ 174 #define BE_BR_IMASK_ECNTEXP 0x00001000 /* excess-collision cntr exp */ 175 #define BE_BR_IMASK_LCCNTEXP 0x00002000 /* late-collision cntr exp */ 176 #define BE_BR_IMASK_FCNTEXP 0x00004000 /* first-collision cntr exp */ 177 #define BE_BR_IMASK_DTIMEXP 0x00008000 /* defer-timer expired */ 178 179 /* be_bregs.tx_cfg: tx config. */ 180 #define BE_BR_TXCFG_ENABLE 0x00000001 /* enable the transmitter */ 181 #define BE_BR_TXCFG_FIFO 0x00000010 /* default tx fthresh */ 182 #define BE_BR_TXCFG_SMODE 0x00000020 /* enable slow transmit mode */ 183 #define BE_BR_TXCFG_CIGN 0x00000040 /* ignore tx collisions */ 184 #define BE_BR_TXCFG_FCSOFF 0x00000080 /* do not emit fcs */ 185 #define BE_BR_TXCFG_DBACKOFF 0x00000100 /* disable backoff */ 186 #define BE_BR_TXCFG_FULLDPLX 0x00000200 /* enable full-duplex */ 187 188 /* be_bregs.rx_cfg: rx config. */ 189 #define BE_BR_RXCFG_ENABLE 0x00000001 /* enable the receiver */ 190 #define BE_BR_RXCFG_FIFO 0x0000000e /* default rx fthresh */ 191 #define BE_BR_RXCFG_PSTRIP 0x00000020 /* pad byte strip enable */ 192 #define BE_BR_RXCFG_PMISC 0x00000040 /* enable promiscuous mode */ 193 #define BE_BR_RXCFG_DERR 0x00000080 /* disable error checking */ 194 #define BE_BR_RXCFG_DCRCS 0x00000100 /* disable crc stripping */ 195 #define BE_BR_RXCFG_ME 0x00000200 /* receive packets for me */ 196 #define BE_BR_RXCFG_PGRP 0x00000400 /* enable promisc group mode */ 197 #define BE_BR_RXCFG_HENABLE 0x00000800 /* enable hash filter */ 198 #define BE_BR_RXCFG_AENABLE 0x00001000 /* enable address filter */ 199 200 /* 201 * BE Channel registers 202 */ 203 #if 0 204 struct be_cregs { 205 u_int32_t ctrl; /* control */ 206 u_int32_t stat; /* status */ 207 u_int32_t rxds; /* rx descriptor ring ptr */ 208 u_int32_t txds; /* tx descriptor ring ptr */ 209 u_int32_t rimask; /* rx interrupt mask */ 210 u_int32_t timask; /* tx interrupt mask */ 211 u_int32_t qmask; /* qec error interrupt mask */ 212 u_int32_t bmask; /* be error interrupt mask */ 213 u_int32_t rxwbufptr; /* local memory rx write ptr */ 214 u_int32_t rxrbufptr; /* local memory rx read ptr */ 215 u_int32_t txwbufptr; /* local memory tx write ptr */ 216 u_int32_t txrbufptr; /* local memory tx read ptr */ 217 u_int32_t ccnt; /* collision counter */ 218 }; 219 #endif 220 /* register indices: */ 221 #define BE_CRI_CTRL (0*4) 222 #define BE_CRI_STAT (1*4) 223 #define BE_CRI_RXDS (2*4) 224 #define BE_CRI_TXDS (3*4) 225 #define BE_CRI_RIMASK (4*4) 226 #define BE_CRI_TIMASK (5*4) 227 #define BE_CRI_QMASK (6*4) 228 #define BE_CRI_BMASK (7*4) 229 #define BE_CRI_RXWBUF (8*4) 230 #define BE_CRI_RXRBUF (9*4) 231 #define BE_CRI_TXWBUF (10*4) 232 #define BE_CRI_TXRBUF (11*4) 233 #define BE_CRI_CCNT (12*4) 234 235 /* be_cregs.ctrl: control. */ 236 #define BE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */ 237 238 /* be_cregs.stat: status. */ 239 #define BE_CR_STAT_BERROR 0x80000000 /* be error */ 240 #define BE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */ 241 #define BE_CR_STAT_TXDERR 0x00080000 /* tx descriptor is bad */ 242 #define BE_CR_STAT_TXLERR 0x00040000 /* tx late error */ 243 #define BE_CR_STAT_TXPERR 0x00020000 /* tx parity error */ 244 #define BE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */ 245 #define BE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */ 246 #define BE_CR_STAT_RXDROP 0x00000010 /* rx packet dropped */ 247 #define BE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */ 248 #define BE_CR_STAT_RXLERR 0x00000004 /* rx late error */ 249 #define BE_CR_STAT_RXPERR 0x00000002 /* rx parity error */ 250 #define BE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */ 251 252 /* be_cregs.qmask: qec error interrupt mask. */ 253 #define BE_CR_QMASK_TXDERR 0x00080000 /* tx descriptor is bad */ 254 #define BE_CR_QMASK_TXLERR 0x00040000 /* tx late error */ 255 #define BE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */ 256 #define BE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */ 257 #define BE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */ 258 #define BE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */ 259 #define BE_CR_QMASK_RXLERR 0x00000004 /* rx late error */ 260 #define BE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */ 261 #define BE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */ 262 263 /* 264 * BE Transceiver registers 265 */ 266 #if 0 267 struct be_tregs { 268 u_int32_t tcvr_pal; /* transceiver pal */ 269 u_int32_t mgmt_pal; /* management pal */ 270 }; 271 #endif 272 /* register indices: */ 273 #define BE_TRI_TCVRPAL 0 274 #define BE_TRI_MGMTPAL 4 275 276 /* be_tregs.tcvr_pal: transceiver pal */ 277 #define TCVR_PAL_SERIAL 0x00000001 /* serial mode enable */ 278 #define TCVR_PAL_EXTLBACK 0x00000002 /* external loopback */ 279 #define TCVR_PAL_MSENSE 0x00000004 /* media sense */ 280 #define TCVR_PAL_LTENABLE 0x00000008 /* link test enable */ 281 #define TCVR_PAL_LTSTATUS 0x00000010 /* link test status: p1 only */ 282 #define TCVR_PAL_BITS "\020" \ 283 "\01SERIAL\02EXTLBACK\03MSENSE" \ 284 "\04LTENABLE\05LTSTATUS" 285 286 /* be_tregs.mgmt_pal: management pal */ 287 #define MGMT_PAL_DCLOCK 0x00000001 /* data clock strobe */ 288 #define MGMT_PAL_OENAB 0x00000002 /* output enable */ 289 #define MGMT_PAL_MDIO 0x00000004 /* MDIO data/attached */ 290 #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO /* external mdio */ 291 #define MGMT_PAL_EXT_MDIO_SHIFT 2 /* position of ext mdio bit */ 292 #define MGMT_PAL_TIMEO 0x00000008 /* tx enable timeout error */ 293 #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO /* internal mdio */ 294 #define MGMT_PAL_INT_MDIO_SHIFT 3 /* position of int mdio bit */ 295 #define MGMT_PAL_BITS "\020" \ 296 "\01DLCLOCK\02ENAB\03EXT_MDIO" \ 297 "\04INT_MDIO" 298 299 /* Packet buffer size */ 300 #define BE_PKT_BUF_SZ 2048 301 302 #define MC_POLY_BE 0x04c11db7UL /* mcast crc, big endian */ 303 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 304 305 /* PHY addresses */ 306 #define BE_PHY_EXTERNAL 0 307 #define BE_PHY_INTERNAL 1 308