1 ///////////////////////////////////////////////////////////////////////// 2 // $Id: rombios.h 14293 2021-06-27 14:50:26Z vruppert $ 3 ///////////////////////////////////////////////////////////////////////// 4 // 5 // Copyright (C) 2006-2020 The Bochs Project 6 // 7 // This library is free software; you can redistribute it and/or 8 // modify it under the terms of the GNU Lesser General Public 9 // License as published by the Free Software Foundation; either 10 // version 2 of the License, or (at your option) any later version. 11 // 12 // This library is distributed in the hope that it will be useful, 13 // but WITHOUT ANY WARRANTY; without even the implied warranty of 14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 // Lesser General Public License for more details. 16 // 17 // You should have received a copy of the GNU Lesser General Public 18 // License along with this library; if not, write to the Free Software 19 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 20 21 /* define it to include QEMU specific code */ 22 //#define BX_QEMU 23 24 #ifndef LEGACY 25 # define BX_ROMBIOS32 1 26 #else 27 # define BX_ROMBIOS32 0 28 #endif 29 30 #define DEBUG_ROMBIOS 0 31 #define DEBUG_ATA 0 32 #define DEBUG_INT13_HD 0 33 #define DEBUG_INT13_CD 0 34 #define DEBUG_INT13_ET 0 35 #define DEBUG_INT13_FL 0 36 #define DEBUG_INT15 0 37 #define DEBUG_INT16 0 38 #define DEBUG_INT1A 0 39 #define DEBUG_INT74 0 40 #define DEBUG_APM 0 41 42 #define PANIC_PORT 0x400 43 #define PANIC_PORT2 0x401 44 #define INFO_PORT 0x402 45 #define DEBUG_PORT 0x403 46 47 #define BIOS_PRINTF_HALT 1 48 #define BIOS_PRINTF_SCREEN 2 49 #define BIOS_PRINTF_INFO 4 50 #define BIOS_PRINTF_DEBUG 8 51 #define BIOS_PRINTF_ALL (BIOS_PRINTF_SCREEN | BIOS_PRINTF_INFO) 52 #define BIOS_PRINTF_DEBHALT (BIOS_PRINTF_SCREEN | BIOS_PRINTF_INFO | BIOS_PRINTF_HALT) 53 54 #define printf(format, p...) bios_printf(BIOS_PRINTF_SCREEN, format, ##p) 55 56 // Defines the output macros. 57 // BX_DEBUG goes to INFO port until we can easily choose debug info on a 58 // per-device basis. Debug info are sent only in debug mode 59 #if DEBUG_ROMBIOS 60 # define BX_DEBUG(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p) 61 #else 62 # define BX_DEBUG(format, p...) 63 #endif 64 #define BX_INFO(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p) 65 #define BX_PANIC(format, p...) bios_printf(BIOS_PRINTF_DEBHALT, format, ##p) 66 67 /* put the MP float table and ACPI RSDP in EBDA and the MP and ACPI tables in 68 high memory. Linux kernels < 2.6.30 might not work with this configuration */ 69 //#define BX_USE_EBDA_TABLES 70 71 #define ACPI_DATA_SIZE 0x00010000L 72 #define MPTABLE_MAX_SIZE 0x00002000 73 #define PM_IO_BASE 0xb000 74 #define SMB_IO_BASE 0xb100 75 #define SMP_MSR_ADDR 0x0510 76 77 // Define the application NAME 78 #if defined(BX_QEMU) 79 # define BX_APPNAME "QEMU" 80 # define BX_APPVENDOR "QEMU" 81 #else 82 # include "../bxversion.h" 83 # define BX_APPNAME "Bochs "VERSION 84 # define BX_APPVENDOR "The Bochs Project" 85 #endif 86 87 #define E820_RAM 1 88 #define E820_RESERVED 2 89 #define E820_ACPI 3 90 #define E820_NVS 4 91 #define E820_UNUSABLE 5 92 93 #define BX_CPU 3 94 #define BX_USE_PS2_MOUSE 1 95 #define BX_CALL_INT15_4F 1 96 #define BX_USE_EBDA 1 97 #define BX_SUPPORT_FLOPPY 1 98 #define BX_FLOPPY_ON_CNT 37 /* 2 seconds */ 99 #define BX_PCIBIOS 1 100 #define BX_APM 1 101 #define BX_PNPBIOS 1 102 /* define it if the (emulated) hardware supports SMM mode */ 103 #define BX_USE_SMM 104 105 #define BX_USE_ATADRV 1 106 #define BX_ELTORITO_BOOT 1 107 108 #define BX_MAX_ATA_INTERFACES 4 109 #define BX_MAX_ATA_DEVICES (BX_MAX_ATA_INTERFACES*2) 110 111 #define BX_VIRTUAL_PORTS 1 /* normal output to Bochs ports */ 112 #define BX_DEBUG_SERIAL 0 /* output to COM1 */ 113 114 /* model byte 0xFC = AT */ 115 #define SYS_MODEL_ID 0xFC 116 #define SYS_SUBMODEL_ID 0x00 117 #define BIOS_REVISION 1 118 #define BIOS_CONFIG_TABLE 0xe6f5 119 120 #ifndef BIOS_BUILD_DATE 121 # define BIOS_BUILD_DATE "06/23/99" 122 #endif 123 124 // 1K of base memory used for Extended Bios Data Area (EBDA) 125 // EBDA is used for PS/2 mouse support, and IDE BIOS, etc. 126 #define EBDA_SEG 0x9FC0 127 #define EBDA_SIZE 1 // In KiB 128 #define BASE_MEM_IN_K (640 - EBDA_SIZE) 129 130 /* IPL_SIZE bytes at 0x9ff00 are used for the IPL boot table. */ 131 #define IPL_SEG 0x9ff0 132 #define IPL_TABLE_OFFSET 0x0000 133 #define IPL_TABLE_ENTRIES 8 134 #define IPL_COUNT_OFFSET 0x0080 /* u16: number of valid table entries */ 135 #define IPL_SEQUENCE_OFFSET 0x0082 /* u16: next boot device */ 136 #define IPL_BOOTFIRST_OFFSET 0x0084 /* u16: user selected device */ 137 #define IPL_SIZE 0x86 138 #define IPL_TYPE_FLOPPY 0x01 139 #define IPL_TYPE_HARDDISK 0x02 140 #define IPL_TYPE_CDROM 0x03 141 #define IPL_TYPE_BEV 0x80 142 143 /* Ports */ 144 #define PORT_DMA_ADDR_2 0x0004 145 #define PORT_DMA_CNT_2 0x0005 146 #define PORT_DMA1_MASK_REG 0x000a 147 #define PORT_DMA1_MODE_REG 0x000b 148 #define PORT_DMA1_CLEAR_FF_REG 0x000c 149 #define PORT_DMA1_MASTER_CLEAR 0x000d 150 #define PORT_PIC1_CMD 0x0020 151 #define PORT_PIC1_DATA 0x0021 152 #define PORT_PIT_COUNTER0 0x0040 153 #define PORT_PIT_MODE 0x0043 154 #define PORT_PS2_DATA 0x0060 155 #define PORT_PS2_CTRLB 0x0061 156 #define PORT_PS2_STATUS 0x0064 157 #define PORT_CMOS_INDEX 0x0070 158 #define PORT_CMOS_DATA 0x0071 159 #define PORT_DIAG 0x0080 160 #define PORT_DMA_PAGE_2 0x0081 161 #define PORT_A20 0x0092 162 #define PORT_PIC2_CMD 0x00a0 163 #define PORT_PIC2_DATA 0x00a1 164 #define PORT_DMA2_MASK_REG 0x00d4 165 #define PORT_DMA2_MODE_REG 0x00d6 166 #define PORT_DMA2_MASTER_CLEAR 0x00da 167 #define PORT_ATA2_CMD_BASE 0x0170 168 #define PORT_ATA1_CMD_BASE 0x01f0 169 #define PORT_FD_DOR 0x03f2 170 #define PORT_FD_STATUS 0x03f4 171 #define PORT_FD_DATA 0x03f5 172 173 #define CPUID_MSR (1 << 5) 174 #define CPUID_APIC (1 << 9) 175 #define CPUID_MTRR (1 << 12) 176 177 #define CPUID_EXT_VMX (1 << 5) 178 #define MSR_FEATURE_CTRL 0x03a 179 #define FEATURE_CTRL_LOCK 0x1 180 #define FEATURE_CTRL_VMX 0x4 181 182 #define APIC_BASE ((uint8_t *)0xfee00000) 183 #define APIC_ICR_LOW 0x300 184 #define APIC_SVR 0x0F0 185 #define APIC_ID 0x020 186 #define APIC_LVT3 0x370 187 188 #define APIC_ENABLED 0x0100 189 190 #define AP_BOOT_ADDR 0x9f000 191 192 #define SMI_CMD_IO_ADDR 0xb2 193 194 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */ 195 196 #define MSR_MTRRcap 0x000000fe 197 #define MSR_MTRRfix64K_00000 0x00000250 198 #define MSR_MTRRfix16K_80000 0x00000258 199 #define MSR_MTRRfix16K_A0000 0x00000259 200 #define MSR_MTRRfix4K_C0000 0x00000268 201 #define MSR_MTRRfix4K_C8000 0x00000269 202 #define MSR_MTRRfix4K_D0000 0x0000026a 203 #define MSR_MTRRfix4K_D8000 0x0000026b 204 #define MSR_MTRRfix4K_E0000 0x0000026c 205 #define MSR_MTRRfix4K_E8000 0x0000026d 206 #define MSR_MTRRfix4K_F0000 0x0000026e 207 #define MSR_MTRRfix4K_F8000 0x0000026f 208 #define MSR_MTRRdefType 0x000002ff 209 210 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 211 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 212 213 #define MTRR_MEMTYPE_UC 0 214 #define MTRR_MEMTYPE_WC 1 215 #define MTRR_MEMTYPE_WT 4 216 #define MTRR_MEMTYPE_WP 5 217 #define MTRR_MEMTYPE_WB 6 218 219 #define QEMU_CFG_CTL_PORT 0x510 220 #define QEMU_CFG_DATA_PORT 0x511 221 #define QEMU_CFG_SIGNATURE 0x00 222 #define QEMU_CFG_ID 0x01 223 #define QEMU_CFG_UUID 0x02 224 225 #define PCI_ADDRESS_SPACE_MEM 0x00 226 #define PCI_ADDRESS_SPACE_IO 0x01 227 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 228 229 #define PCI_ROM_SLOT 6 230 #define PCI_NUM_REGIONS 7 231 232 #define PCI_DEVICES_MAX 64 233 234 #define PCI_CLASS_STORAGE_IDE 0x0101 235 #define PCI_CLASS_DISPLAY_VGA 0x0300 236 #define PCI_CLASS_SYSTEM_PIC 0x0800 237 238 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 239 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 240 #define PCI_COMMAND 0x04 /* 16 bits */ 241 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 242 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 243 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 244 #define PCI_HEADER_TYPE 0x0e /* Header type */ 245 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 246 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 247 #define PCI_MIN_GNT 0x3e /* 8 bits */ 248 #define PCI_MAX_LAT 0x3f /* 8 bits */ 249 250 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 251 252 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 253 #define PCI_ROM_ADDRESS_ENABLE 0x01 254 255 #define PCI_VENDOR_ID_INTEL 0x8086 256 #define PCI_DEVICE_ID_INTEL_82437 0x0122 257 #define PCI_DEVICE_ID_INTEL_82441 0x1237 258 #define PCI_DEVICE_ID_INTEL_82443 0x7190 259 #define PCI_DEVICE_ID_INTEL_82443_1 0x7191 260 #define PCI_DEVICE_ID_INTEL_82443_NOAGP 0x7192 261 #define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e 262 #define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 263 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 264 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 265 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 266 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111 267 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 268 269 #define PCI_VENDOR_ID_IBM 0x1014 270 #define PCI_VENDOR_ID_APPLE 0x106b 271