1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2019-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 #ifndef STRUCTURE_ALINGMENT_VERIFICATION 10 #pragma once 11 #endif 12 13 #include "usc_gen8.h" 14 15 namespace USC 16 { 17 18 19 /*****************************************************************************\ 20 ENUM: BLEND_OPTIMIZATION_MODE 21 \*****************************************************************************/ 22 enum BLEND_OPTIMIZATION_MODE 23 { 24 BLEND_OPTIMIZATION_NONE, // No optimizations 25 BLEND_OPTIMIZATION_SRC_ALPHA, // Discard: src.a == 0, Fill: src.a == 1 26 BLEND_OPTIMIZATION_INV_SRC_ALPHA, // Discard: src.a == 1, Fill: src.a == 0 27 BLEND_OPTIMIZATION_SRC_ALPHA_DISCARD_ONLY, // Discard: src.a == 0 28 BLEND_OPTIMIZATION_SRC_ALPHA_FILL_ONLY, // Fill: src.a == 1 29 BLEND_OPTIMIZATION_SRC_COLOR_ZERO, // Discard: src.rgb == 0 30 BLEND_OPTIMIZATION_SRC_COLOR_ONE, // Discard: src.rgb == 1 31 BLEND_OPTIMIZATION_SRC_BOTH_ZERO, // Discard: src.rgba == 0 32 BLEND_OPTIMIZATION_SRC_BOTH_ONE, // Discard: src.rgba == 1 33 BLEND_OPTIMIZATION_SRC_ALPHA_OR_COLOR_ZERO, // Discard: src.a == 0 || src.rgb == 0 34 BLEND_OPTIMIZATION_SRC_COLOR_ZERO_ALPHA_ONE, // Discard: src.rgb == 0 && src.a == 1 35 BLEND_OPTIMIZATION_SRC_COLOR_ZERO_ALPHA_IGNORE, // Discard: src.rgb == 0 and don't compute src.a 36 }; 37 38 /*****************************************************************************\ 39 \*****************************************************************************/ 40 struct SCompilerOutputVertexShader_Gen9 : public SCompilerOutputVertexShader_Gen8 41 { 42 bool m_EnableVertexReordering; 43 44 PADDING_1_BYTE 45 PADDING_2_BYTES 46 PADDING_4_BYTES 47 }; 48 49 50 51 /*****************************************************************************\ 52 STRUCT: SCompilerInputHullShader 53 \*****************************************************************************/ 54 struct SCompilerInputHullShader : public SCompilerInputCommon 55 { 56 float m_TessellationFactorScale; 57 }; 58 59 /* Structures for compile shader inputs*/ 60 61 struct SCompilerInputVertexShader : public SCompilerInputCommon 62 { 63 }; 64 struct SCompilerInputDomainShader : public SCompilerInputCommon 65 { 66 }; 67 struct SCompilerInputGeometryShader : public SCompilerInputCommon 68 { 69 }; 70 71 /*****************************************************************************\ 72 \*****************************************************************************/ 73 struct SCompilerOutputHullShader_Gen9 : public SCompilerOutputHullShader_Gen8 74 { 75 // ### DW7 3DSTATE_HS ### 76 unsigned int DispatchMode; // HS dispatch mode (DW7, BITFIELD_RANGE( 17,18 )) 77 unsigned int IncludePrimitiveID; // HS primitive ID (DW7, BITFIELD(0)) 78 }; 79 80 /*****************************************************************************\ 81 \*****************************************************************************/ 82 struct SCompilerOutputDomainShader_Gen9 : public SCompilerOutputDomainShader_Gen7 83 { 84 // ### DW7 3DSTATE_DS ### 85 unsigned int DispatchMode; //(DW7, bits 4...3) 86 87 // ### DW8 3DSTATE_DS ### 88 unsigned int m_VertexURBEntryOutputReadOffset; //(DW8, bits 26..21) 89 unsigned int m_VertexURBEntryOutputLength; //(DW8, bits 20..16) 90 91 // ### DW9 3DSTATE_DS ### 92 unsigned int m_DualPatchKernelProgramSize; 93 void* m_pDualPatchKernelProgram; //(DW9, bits 31...6) 94 95 bool m_HasPrimitiveIdInput; 96 97 PADDING_1_BYTE 98 PADDING_2_BYTES 99 PADDING_4_BYTES 100 PADDING_4_BYTES_x32_ONLY 101 }; 102 103 /*****************************************************************************\ 104 \*****************************************************************************/ 105 struct SCompilerOutputGeometryShader_Gen9 : public SCompilerOutputGeometryShader_Gen8 106 { 107 // identical to Gen8 108 }; 109 110 /*****************************************************************************\ 111 \*****************************************************************************/ 112 USC_PARAM() 113 struct SCompilerOutputPixelShader_Gen9 : public SCompilerOutputPixelShader_Gen8 114 { 115 GFX3DSTATE_SF_ATTRIBUTE_ACTIVE_COMPONENT attributeActiveComponent[ NUM_PSHADER_INPUT_REGISTERS ]; 116 117 unsigned int OutputUseMask[ NUM_PSHADER_OUTPUT_REGISTERS ]; 118 119 // ### DW1 3DSTATE_PS_EXTRA ### 120 GFX3DSTATE_PSEXTRA_INPUT_COVERAGE_MASK_MODE m_InputCoverageMaskMode; // (bit 1..0) 121 unsigned int m_BarycentricParamsArePulled; // (bit 3) 122 unsigned int m_PixelShaderComputesStencil; // (bit 5) 123 124 unsigned int m_FP16PayloadEnable; // (bit 17) 125 unsigned int m_CRastBinaryHeaderSize; 126 unsigned int m_SampleCmpToDiscardOptimizationSlot; 127 bool m_NeedsWAForSampleLInLoopPS; 128 bool m_SampleCmpToDiscardOptimizationPossible; 129 bool m_NeedPSSync; 130 PADDING_1_BYTE 131 PADDING_4_BYTES 132 }; 133 134 /*****************************************************************************\ 135 STRUCT: SCompilerInputComputeShader_Gen9 136 \*****************************************************************************/ 137 struct SCompilerInputComputeShader_Gen9 : public SCompilerInputCommon_Gen7 138 { 139 // False - legacy 140 bool PooledEUMode; 141 142 // Maximum size of available pool in physical (EU) threads 143 unsigned int EUThreadsInPoolMax; 144 }; 145 146 /*****************************************************************************\ 147 \*****************************************************************************/ 148 struct SCompilerOutputComputeShader_Gen9 : public SCompilerOutputComputeShader_Gen8 149 { 150 // identical to Gen8 151 }; 152 153 } // namespace USC 154