1 /* 2 * Copyright 2015 Ettus Research LLC 3 * 4 * This program is free software: you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation, either version 3 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef _NET_ENC28J60_H_ 19 #define _NET_ENC28J60_H_ 20 21 #include <avr/io.h> 22 23 #define SPI_DDR DDRB 24 #define SPI_PORT PORTB 25 #define SPI_CS 0 26 #define SPI_MOSI 2 27 #define SPI_MISO 3 28 #define SPI_SCK 1 29 30 // Register Masks 31 #define ADDR_MASK 0x1F 32 #define BANK_MASK 0x60 33 #define SPRD_MASK 0x80 34 35 // All Banks Registers 36 #define EIE 0x1B 37 #define EIR 0x1C 38 #define ESTAT 0x1D 39 #define ECON2 0x1E 40 #define ECON1 0x1F 41 42 // Bank 0 Registers 43 #define ERDPTL 0x00 44 #define ERDPTH 0x01 45 #define EWRPTL 0x02 46 #define EWRPTH 0x03 47 #define ETXSTL 0x04 48 #define ETXSTH 0x05 49 #define ETXNDL 0x06 50 #define ETXNDH 0x07 51 #define ERXSTL 0x08 52 #define ERXSTH 0x09 53 #define ERXNDL 0x0A 54 #define ERXNDH 0x0B 55 #define ERXRDPTL 0x0C 56 #define ERXRDPTH 0x0D 57 #define ERXWRPTL 0x0E 58 #define ERXWRPTH 0x0F 59 #define EDMASTL 0x10 60 #define EDMASTH 0x11 61 #define EDMANDL 0x12 62 #define EDMANDH 0x13 63 #define EDMADSTL 0x14 64 #define EDMADSTH 0x15 65 #define EDMACSL 0x16 66 #define EDMACSH 0x17 67 68 // Bank 1 Registers 69 #define EHT0 0x20 70 #define EHT1 0x21 71 #define EHT2 0x22 72 #define EHT3 0x23 73 #define EHT4 0x24 74 #define EHT5 0x25 75 #define EHT6 0x26 76 #define EHT7 0x27 77 #define EPMM0 0x28 78 #define EPMM1 0x29 79 #define EPMM2 0x2A 80 #define EPMM3 0x2B 81 #define EPMM4 0x2C 82 #define EPMM5 0x2D 83 #define EPMM6 0x2E 84 #define EPMM7 0x2F 85 #define EPMCSL 0x30 86 #define EPMCSH 0x31 87 #define EPMOL 0x34 88 #define EPMOH 0x35 89 #define EWOLIE 0x36 90 #define EWOLIR 0x37 91 #define ERXFCON 0x38 92 #define EPKTCNT 0x39 93 94 // Bank 2 Register 95 #define MACON1 0xC0 96 #define MACON2 0xC1 97 #define MACON3 0xC2 98 #define MACON4 0xC3 99 #define MABBIPG 0xC4 100 #define MAIPGL 0xC6 101 #define MAIPGH 0xC7 102 #define MACLCON1 0xC8 103 #define MACLCON2 0xC9 104 #define MAMXFLL 0xCA 105 #define MAMXFLH 0xCB 106 #define MAPHSUP 0xCD 107 #define MICON 0xD1 108 #define MICMD 0xD2 109 #define MIREGADR 0xD4 110 #define MIWRL 0xD6 111 #define MIWRH 0xD7 112 #define MIRDL 0xD8 113 #define MIRDH 0xD9 114 115 // Bank 3 Registers 116 #define MAADR1 0xE0 117 #define MAADR0 0xE1 118 #define MAADR3 0xE2 119 #define MAADR2 0xE3 120 #define MAADR5 0xE4 121 #define MAADR4 0xE5 122 #define EBSTSD 0x66 123 #define EBSTCON 0x67 124 #define EBSTCSL 0x68 125 #define EBSTCSH 0x69 126 #define MISTAT 0xEA 127 #define EREVID 0x72 128 #define ECOCON 0x75 129 #define EFLOCON 0x77 130 #define EPAUSL 0x78 131 #define EPAUSH 0x79 132 133 // PHY Registers 134 #define PHCON1 0x00 135 #define PHSTAT1 0x01 136 #define PHHID1 0x02 137 #define PHHID2 0x03 138 #define PHCON2 0x10 139 #define PHSTAT2 0x11 140 #define PHIE 0x12 141 #define PHIR 0x13 142 #define PHLCON 0x14 143 144 // ERXFCON bit definitions 145 #define UCEN 0x80 146 #define ANDOR 0x40 147 #define CRCEN 0x20 148 #define PMEN 0x10 149 #define MPEN 0x08 150 #define HTEN 0x04 151 #define MCEN 0x02 152 #define BCEN 0x01 153 154 // EIE bit definitions 155 #define INTIE 0x80 156 #define PKTIE 0x40 157 #define DMAIE 0x20 158 #define LINKIE 0x10 159 #define TXIE 0x08 160 #define WOLIE 0x04 161 #define TXERIE 0x02 162 #define RXERIE 0x01 163 164 // EIR bit definitions 165 #define PKTIF 0x40 166 #define DMAIF 0x20 167 #define LINKIF 0x10 168 #define TXIF 0x08 169 #define WOLIF 0x04 170 #define TXERIF 0x02 171 #define RXERIF 0x01 172 173 // ESTAT bit definitions 174 #define INT 0x80 175 #define LATECOL 0x10 176 #define RXBUSY 0x04 177 #define TXABRT 0x02 178 #define CLKRDY 0x01 179 180 // ECON2 bit definitions 181 #define AUTOINC 0x80 182 #define PKTDEC 0x40 183 #define PWRSV 0x20 184 #define VRPS 0x08 185 186 // ECON1 bit definitions 187 #define TXRST 0x80 188 #define RXRST 0x40 189 #define DMAST 0x20 190 #define CSUMEN 0x10 191 #define TXRTS 0x08 192 #define ENCRXEN 0x04 193 #define BSEL1 0x02 194 #define BSEL0 0x01 195 196 // MACON1 bit definitions 197 #define LOOPBK 0x10 198 #define TXPAUS 0x08 199 #define RXPAUS 0x04 200 #define PASSALL 0x02 201 #define MARXEN 0x01 202 203 // MACON2 bit definitions 204 #define MARST 0x80 205 #define RNDRST 0x40 206 #define MARXRST 0x08 207 #define RFUNRST 0x04 208 #define MATXRST 0x02 209 #define TFUNRST 0x01 210 211 // MACON3 bit definitions 212 #define PADCFG2 0x80 213 #define PADCFG1 0x40 214 #define PADCFG0 0x20 215 #define TXCRCEN 0x10 216 #define PHDRLEN 0x08 217 #define HFRMLEN 0x04 218 #define FRMLNEN 0x02 219 #define FULDPX 0x01 220 221 // MICMD bit definitions 222 #define MIISCAN 0x02 223 #define MIIRD 0x01 224 225 // MISTAT bit definitions 226 #define NVALID 0x04 227 #define SCAN 0x02 228 #define BUSY 0x01 229 230 // PHCON1 bit definitions 231 #define PRST 0x8000 232 #define PLOOPBK 0x4000 233 #define PPWRSV 0x0800 234 #define PDPXMD 0x0100 235 236 // PHSTAT1 bit definitions 237 #define PFDPX 0x1000 238 #define PHDPX 0x0800 239 #define LLSTAT 0x0004 240 #define JBSTAT 0x0002 241 242 // PHCON2 bit definitions 243 #define FRCLINK 0x4000 244 #define TXDIS 0x2000 245 #define JABBER 0x0400 246 #define HDLDIS 0x0100 247 248 // Packet Control bit Definitions 249 #define PHUGEEN 0x08 250 #define PPADEN 0x04 251 #define PCRCEN 0x02 252 #define POVERRIDE 0x01 253 254 // SPI Instruction Set 255 #define RCR 0x00 // Read Control Register 256 #define RBM 0x3A // Read Buffer Memory 257 #define WCR 0x40 // Write Control Register 258 #define WBM 0x7A // Write Buffer Memory 259 #define BFS 0x80 // Bit Field Set 260 #define BFC 0xA0 // Bit Field Clear 261 #define SC 0xFF // Soft Reset 262 263 // Buffer 264 #define RXSTART_INIT 0x0000 265 #define RXSTOP_INIT (0x1FFF-0x0600-1) 266 #define TXSTART_INIT (0x1FFF-0x0600) 267 #define TXSTOP_INIT 0x1FFF 268 #define MAX_FRAMELEN 1500 269 270 void enc28j60_init(uint8_t* mac_addr); 271 272 uint16_t enc28j60_recv(uint8_t* buffer, uint16_t max_len); 273 274 void enc28j60_send(uint8_t* buffer, uint16_t len); 275 276 #endif /* _NET_ENC28J60_H_ */ 277