1 /* $NetBSD: if_nireg.h,v 1.6 2005/12/11 12:21:15 christos Exp $ */ 2 /* 3 * Copyright (c) 1988 Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Chris Torek. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * @(#)nireg.h 7.3 (Berkeley) 6/28/90 34 */ 35 36 /* 37 * Registers for the DEBNA and DEBNK Ethernet interfaces 38 * (DEC calls these Network Interfaces, hence nireg.h) 39 */ 40 41 /* 42 * this seems to be intended to be more general, but I have no details, 43 * so it goes here for now 44 * 45 * BI Vax Port (BVP) stuff first: 46 */ 47 #ifdef notdef 48 struct bvpregs { 49 u_long p_pcr; /* port control register */ 50 u_long p_psr; /* port status register */ 51 u_long p_per; /* port error register */ 52 u_long p_pdr; /* port data register */ 53 }; 54 55 /* 56 * BI node space registers 57 */ 58 struct ni_regs { 59 struct biiregs ni_bi; /* BIIC registers, except GPRs */ 60 struct bvpregs ni_tkp; /* tk50 port control via BIIC GPRs */ 61 u_long ni_xxx[64]; /* unused */ 62 u_long ni_rxcd; /* receive console data */ 63 struct bvpregs ni_nip; /* NI port control via BCI3 GPRs */ 64 u_long ni_pudr; /* power-up diagnostic register */ 65 }; 66 #endif 67 68 #define NI_PCR 0x204 69 #define NI_PSR 0x208 70 #define NI_PER 0x20c 71 #define NI_PDR 0x210 72 #define NI_PUDR 0x204 73 74 /* bits in PCR */ 75 #define PCR_OWN 0x80 76 #define PCR_MFREEQ 0x000 77 #define PCR_DFREEQ 0x100 78 #define PCR_RFREEQ 0x200 79 #define PCR_IFREEQ 0x300 80 #define PCR_CMDQ0 PCR_MFREEQ 81 #define PCR_CMDQ1 PCR_DFREEQ 82 #define PCR_CMDQ2 PCR_RFREEQ 83 #define PCR_CMDQ3 PCR_IFREEQ 84 #define PCR_RESTART 11 85 #define PCR_FREEQNE 7 86 #define PCR_CMDQNE 6 87 #define PCR_SHUTDOWN 4 88 #define PCR_ENABLE 2 89 #define PCR_INIT 1 90 91 /* bits in PSR */ 92 #define PSR_OWN 0x80000000 93 #define PSR_STATE 0x00070000 94 #define PSR_STOPPED 0x00060000 95 #define PSR_ENABLED 0x00040000 96 #define PSR_INITED 0x00020000 97 #define PSR_UNDEF 0x00010000 98 #define PSR_RSQ 0x00000080 99 #define PSR_ERR 0x00000040 100 101 /* 102 * The DEBNx uses a very weird (set of) structure(s) to communicate 103 * with something as simple as an ethernet controller. This is not 104 * very different to the way communication is done over CI with disks. 105 */ 106 107 /* Message packet */ 108 struct ni_msg { 109 u_int32_t nm_forw; 110 u_int32_t nm_back; 111 u_int32_t nm_pad1; 112 u_int8_t nm_pad2; 113 u_int8_t nm_status; 114 u_int8_t nm_opcode; 115 u_int8_t nm_pad3; 116 u_int16_t nm_len; 117 u_int8_t nm_opcode2; 118 u_int8_t nm_status2; 119 u_int32_t nm_pad4; 120 u_int8_t nm_text[128]; 121 }; 122 123 /* Datagram packet */ 124 struct ni_dg { 125 u_int32_t nd_forw; 126 u_int32_t nd_back; 127 u_int32_t nd_pad1; 128 u_int8_t nd_pad2; 129 u_int8_t nd_status; 130 u_int8_t nd_opcode; 131 u_int8_t nd_pad3; 132 u_int16_t nd_len; 133 u_int16_t nd_status2; 134 u_int32_t nd_cmdref; 135 u_int32_t nd_ptdbidx; 136 struct { 137 u_int16_t _offset; 138 u_int16_t _len; 139 u_int16_t _index; 140 u_int16_t _key; 141 } bufs[NTXFRAGS]; 142 }; 143 144 #define NIDG_CHAIN 0x8000 145 146 /* NI parameter block */ 147 struct ni_param { 148 u_int8_t np_dpa[8]; 149 u_int8_t np_apa[8]; 150 u_int8_t np_lsa[8]; 151 u_int8_t np_bvc[8]; 152 u_int16_t np_curaddr; 153 u_int16_t np_maxaddr; 154 u_int16_t np_curptt; 155 u_int16_t np_maxptt; 156 u_int16_t np_curfq; 157 u_int16_t np_maxfq; 158 u_int32_t np_sid; 159 u_int32_t np_mop; 160 u_int32_t np_flags; 161 u_int32_t np_rcto; 162 u_int32_t np_xmto; 163 }; 164 165 #define NP_ECT 0x01 166 #define NP_PAD 0x02 167 #define NP_BOO 0x04 168 #define NP_CAR 0x08 169 #define NP_ILP 0x10 170 #define NP_ELP 0x20 171 #define NP_DCRC 0x40 172 #define NP_THRU 0x80 173 174 /* Protocol type definition block */ 175 struct ni_ptdb { 176 u_int16_t np_type; /* Protocol type */ 177 u_int8_t np_fque; /* Free queue */ 178 u_int8_t np_flags; /* See below */ 179 u_int32_t np_index; /* protocol type index */ 180 u_int16_t np_adrlen; /* # of multicast addresses */ 181 u_int16_t np_802; /* for IEEE 802 packets */ 182 u_int8_t np_mcast[16][8];/* Multicast (direct match) array */ 183 }; 184 185 #define PTDB_PROMISC 0x08 186 #define PTDB_802 0x10 187 #define PTDB_BDC 0x20 188 #define PTDB_UNKN 0x40 189 #define PTDB_AMC 0x80 190 191 /* Buffer descriptor */ 192 struct ni_bbd { 193 u_int16_t nb_status; /* Offset, valid etc */ 194 u_int16_t nb_key; 195 u_int32_t nb_len; /* Buffer length */ 196 u_int32_t nb_pte; /* start (vax) PTE for this buffer */ 197 u_int32_t nb_pad; 198 }; 199 #define NIBD_OFFSET 0x1ff 200 #define NIBD_VALID 0x8000 201 202 203 /* Free Queue Block */ 204 struct ni_fqb { 205 u_int32_t nf_mlen; 206 u_int32_t nf_mpad; 207 u_int32_t nf_mforw; 208 u_int32_t nf_mback; 209 u_int32_t nf_dlen; 210 u_int32_t nf_dpad; 211 u_int32_t nf_dforw; 212 u_int32_t nf_dback; 213 u_int32_t nf_rlen; 214 u_int32_t nf_rpad; 215 u_int32_t nf_rforw; 216 u_int32_t nf_rback; 217 u_int32_t nf_ilen; 218 u_int32_t nf_ipad; 219 u_int32_t nf_iforw; 220 u_int32_t nf_iback; 221 }; 222 223 /* DEBNx specific part of Generic VAX Port */ 224 struct ni_pqb { 225 u_int16_t np_veclvl; /* Interrupt vector + level */ 226 u_int16_t np_node; /* Where to interrupt */ 227 u_int32_t np_freeq; 228 u_int32_t np_vfqb; /* Free queue block pointer */ 229 u_int32_t np_pad1[39]; 230 u_int32_t np_bvplvl; 231 u_int32_t np_vpqb; /* Virtual address of Generic PQB */ 232 u_int32_t np_vbdt; /* Virtual address of descriptors */ 233 u_int32_t np_nbdr; /* Number of descriptors */ 234 u_int32_t np_spt; /* System Page Table */ 235 u_int32_t np_sptlen; /* System Page Table length */ 236 u_int32_t np_gpt; /* Global Page Table */ 237 u_int32_t np_gptlen; /* Global Page Table length */ 238 u_int32_t np_mask; 239 u_int32_t np_pad2[67]; 240 }; 241 242 /* "Generic VAX Port Control Block" whatever it means */ 243 struct ni_gvppqb { 244 u_int32_t nc_forw0; 245 u_int32_t nc_back0; 246 u_int32_t nc_forw1; 247 u_int32_t nc_back1; 248 u_int32_t nc_forw2; 249 u_int32_t nc_back2; 250 u_int32_t nc_forw3; 251 u_int32_t nc_back3; 252 u_int32_t nc_forwr; 253 u_int32_t nc_backr; 254 struct ni_pqb nc_pqb; /* DEBNx specific part of struct */ 255 }; 256 257 258 /* BVP opcodes, should be somewhere else */ 259 #define BVP_DGRAM 1 260 #define BVP_MSG 2 261 #define BVP_DGRAMI 3 262 #define BVP_DGRAMRX 33 263 #define BVP_MSGRX 34 264 #define BVP_DGRAMIRX 35 265 266 /* NI-specific sub-opcodes */ 267 #define NI_WSYSID 1 268 #define NI_RSYSID 2 269 #define NI_WPARAM 3 270 #define NI_RPARAM 4 271 #define NI_RCCNTR 5 272 #define NI_RDCNTR 6 273 #define NI_STPTDB 7 274 #define NI_CLPTDB 8 275 276 /* bits in ni_pudr */ 277 #define PUDR_TAPE 0x40000000 /* tk50 & assoc logic ok */ 278 #define PUDR_PATCH 0x20000000 /* patch logic ok */ 279 #define PUDR_VRAM 0x10000000 /* DEBNx onboard RAM ok */ 280 #define PUDR_VROM1 0x08000000 /* uVax ROM 1 ok */ /* ? */ 281 #define PUDR_VROM2 0x04000000 /* uVax ROM 2 ok */ 282 #define PUDR_VROM3 0x02000000 /* uVax ROM 3 ok */ 283 #define PUDR_VROM4 0x01000000 /* uVax ROM 4 ok */ 284 #define PUDR_UVAX 0x00800000 /* uVax passes self test */ 285 #define PUDR_BI 0x00400000 /* BIIC and BCI3 chips ok */ 286 #define PUDR_TMR 0x00200000 /* interval timer ok */ 287 #define PUDR_IRQ 0x00100000 /* no IRQ lines stuck */ 288 #define PUDR_NI 0x00080000 /* Ethernet ctlr ok */ 289 #define PUDR_TK50 0x00040000 /* tk50 present */ 290 #define PUDR_PRES 0x00001000 /* tk50 present (again?!) */ 291 #define PUDR_UVINT 0x00000800 /* uVax-to-80186 intr logic ok */ 292 #define PUDR_BUSHD 0x00000400 /* no bus hold errors */ 293 #define PUDR_II32 0x00000200 /* II32 transceivers ok */ 294 #define PUDR_MPSC 0x00000100 /* MPSC logic ok */ 295 #define PUDR_GAP 0x00000080 /* gap-detect logic ok */ 296 #define PUDR_MISC 0x00000040 /* misc. registers ok */ 297 #define PUDR_UNEXP 0x00000020 /* unexpected interrupt trapped */ 298 #define PUDR_80186 0x00000010 /* 80186 ok */ 299 #define PUDR_PATCH2 0x00000008 /* patch logic ok (again) */ 300 #define PUDR_8RAM 0x00000004 /* 80186 RAM ok */ 301 #define PUDR_8ROM2 0x00000002 /* 80186 ROM1 ok */ 302 #define PUDR_8ROM1 0x00000001 /* 80186 ROM2 ok */ 303