1 /* $NetBSD: cache_octeon.h,v 1.2 2016/07/11 16:15:35 matt Exp $ */ 2 3 #define CACHE_OCTEON_I 0 4 #define CACHE_OCTEON_D 1 5 6 #define CACHEOP_OCTEON_INV_ALL (0 << 2) /* I, D */ 7 #define CACHEOP_OCTEON_INDEX_LOAD_TAG (1 << 2) /* I, D */ 8 #define CACHEOP_OCTEON_BITMAP_STORE (3 << 2) /* I */ 9 #define CACHEOP_OCTEON_VIRTUAL_TAG_INV (4 << 2) /* D */ 10 11 #if !defined(_LOCORE) 12 13 /* 14 * cache_octeon_invalidate: 15 * 16 * Invalidate all cahce blocks. 17 * Argument "op" must be CACHE_OCTEON_I or CACHE_OCTEON_D. 18 * In Octeon specification, invalidate instruction works 19 * all cache blocks. 20 */ 21 #define cache_octeon_invalidate(op) \ 22 do { \ 23 __asm __volatile( \ 24 ".set noreorder \n\t" \ 25 "cache %0, 0($0) \n\t" \ 26 ".set reorder" \ 27 : \ 28 : "i" (op) \ 29 : "memory"); \ 30 } while (/*CONSTCOND*/0) 31 32 /* 33 * cache_octeon_op_line: 34 * 35 * Perform the specified cache operation on a single line. 36 */ 37 #define cache_op_octeon_line(va, op) \ 38 do { \ 39 __asm __volatile( \ 40 ".set noreorder \n\t" \ 41 "cache %1, 0(%0) \n\t" \ 42 ".set reorder" \ 43 : \ 44 : "r" (va), "i" (op) \ 45 : "memory"); \ 46 } while (/*CONSTCOND*/0) 47 48 void octeon_icache_sync_all(void); 49 void octeon_icache_sync_range(register_t va, vsize_t size); 50 void octeon_icache_sync_range_index(vaddr_t va, vsize_t size); 51 void octeon_pdcache_inv_all(void); 52 void octeon_pdcache_inv_range(register_t va, vsize_t size); 53 void octeon_pdcache_inv_range_index(vaddr_t va, vsize_t size); 54 void octeon_pdcache_wb_range(register_t va, vsize_t size); 55 56 #endif /* !_LOCORE */ 57