xref: /original-bsd/sys/hp300/hp300/clockreg.h (revision 4d96b6b1)
1 /*
2  * Copyright (c) 1988 University of Utah.
3  * Copyright (c) 1982, 1990, 1993
4  *	The Regents of the University of California.  All rights reserved.
5  *
6  * This code is derived from software contributed to Berkeley by
7  * the Systems Programming Group of the University of Utah Computer
8  * Science Department.
9  *
10  * %sccs.include.redist.c%
11  *
12  * from: Utah $Hdr: clockreg.h 1.14 91/01/18$
13  *
14  *	@(#)clockreg.h	8.2 (Berkeley) 01/12/94
15  */
16 
17 /*
18  * HP300 "real time clock" (MC6840) registers
19  */
20 
21 struct clkreg {
22 	u_char	clk_dummy1;
23 	u_char	clk_cr3;
24 #define	clk_cr1	clk_cr3
25 	u_char	clk_dummy2;
26 	u_char	clk_cr2;
27 #define	clk_sr	clk_cr2
28 	u_char	clk_dummy3;
29 	u_char	clk_msb1;
30 	u_char	clk_dummy4;
31 	u_char	clk_lsb1;
32 	u_char	clk_dummy5;
33 	u_char	clk_msb2;
34 	u_char	clk_dummy6;
35 	u_char	clk_lsb2;
36 	u_char	clk_dummy7;
37 	u_char	clk_msb3;
38 	u_char	clk_dummy8;
39 	u_char	clk_lsb3;
40 };
41 
42 /* base/offsets for register access (for locore.s) */
43 #define	CLKBASE		IIOPOFF(0x5F8000)
44 #define	CLKCR1		0x1
45 #define	CLKCR2		0x3
46 #define	CLKCR3		CLKCR1
47 #define	CLKSR		CLKCR2
48 #define	CLKMSB1		0x5
49 #define	CLKMSB2		0x9
50 #define	CLKMSB3		0xD
51 
52 /* output of counter 3 clocks counter 2 */
53 
54 #define	CLK_OENAB	0x80	/* output enable */
55 #define	CLK_IENAB	0x40	/* interrupt enable */
56 #define	CLK_8BIT	0x04	/* 8 bit mode */
57 #define	CLK_RESET	0x01	/* chip reset (CR1 only) */
58 #define	CLK_CR1		0x01	/* select CR1 (CR2 only) */
59 #define	CLK_CR3		0x00	/* select CR3 (CR2 only) */
60 #define CLK_INT1	0x01	/* interrupt flag for timer 1 (SR only) */
61 #define CLK_INT2	0x02	/* interrupt flag for timer 2 (SR only) */
62 #define CLK_INT3	0x04	/* interrupt flag for timer 3 (SR only) */
63 #define	CLK_INTR	0x80	/* composite interrupt flag (SR only) */
64 
65 #define CLK_RESOLUTION	4	/* 4 usec resolution (250Khz) */
66 #define	CLK_INTERVAL	2500	/* 10msec interval at 250KHz */
67 #ifdef NOTDEF
68 #define CLK_INTERVAL	5000	/* 20msec interval at 250Khz */
69 #endif
70 
71 /*
72  * HP300 battery-backed clock
73  */
74 
75 struct bbc_tm {
76 	int	tm_sec;
77 	int	tm_min;
78 	int	tm_hour;
79 	int	tm_mday;
80 	int	tm_mon;
81 	int	tm_year;
82 };
83 
84 #define FEBRUARY	2
85 #define	STARTOFTIME	1970
86 #define SECDAY		86400L
87 #define SECYR		(SECDAY * 365)
88 
89 #define BBC_SET_REG 	0xe0
90 #define BBC_WRITE_REG	0xc2
91 #define BBC_READ_REG	0xc3
92 #define NUM_BBC_REGS	12
93 
94 #define	leapyear(year)		((year) % 4 == 0)
95 #define	range_test(n, l, h)	if ((n) < (l) || (n) > (h)) return(0)
96 #define	days_in_year(a) 	(leapyear(a) ? 366 : 365)
97 #define	days_in_month(a) 	(month_days[(a) - 1])
98 #define	bbc_to_decimal(a,b) 	(bbc_registers[a] * 10 + bbc_registers[b])
99 #define	decimal_to_bbc(a,b,n) 	{ \
100 	bbc_registers[a] = (n) % 10; \
101 	bbc_registers[b] = (n) / 10; \
102 }
103