1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * ni_labpc register definitions.
4  */
5 
6 #ifndef _NI_LABPC_REGS_H
7 #define _NI_LABPC_REGS_H
8 
9 /*
10  * Register map (all registers are 8-bit)
11  */
12 #define STAT1_REG		0x00	/* R: Status 1 reg */
13 #define STAT1_DAVAIL		BIT(0)
14 #define STAT1_OVERRUN		BIT(1)
15 #define STAT1_OVERFLOW		BIT(2)
16 #define STAT1_CNTINT		BIT(3)
17 #define STAT1_GATA0		BIT(5)
18 #define STAT1_EXTGATA0		BIT(6)
19 #define CMD1_REG		0x00	/* W: Command 1 reg */
20 #define CMD1_MA(x)		(((x) & 0x7) << 0)
21 #define CMD1_TWOSCMP		BIT(3)
22 #define CMD1_GAIN(x)		(((x) & 0x7) << 4)
23 #define CMD1_SCANEN		BIT(7)
24 #define CMD2_REG		0x01	/* W: Command 2 reg */
25 #define CMD2_PRETRIG		BIT(0)
26 #define CMD2_HWTRIG		BIT(1)
27 #define CMD2_SWTRIG		BIT(2)
28 #define CMD2_TBSEL		BIT(3)
29 #define CMD2_2SDAC0		BIT(4)
30 #define CMD2_2SDAC1		BIT(5)
31 #define CMD2_LDAC(x)		BIT(6 + ((x) & 0x1))
32 #define CMD3_REG		0x02	/* W: Command 3 reg */
33 #define CMD3_DMAEN		BIT(0)
34 #define CMD3_DIOINTEN		BIT(1)
35 #define CMD3_DMATCINTEN		BIT(2)
36 #define CMD3_CNTINTEN		BIT(3)
37 #define CMD3_ERRINTEN		BIT(4)
38 #define CMD3_FIFOINTEN		BIT(5)
39 #define ADC_START_CONVERT_REG	0x03	/* W: Start Convert reg */
40 #define DAC_LSB_REG(x)		(0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */
41 #define DAC_MSB_REG(x)		(0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */
42 #define ADC_FIFO_CLEAR_REG	0x08	/* W: A/D FIFO Clear reg */
43 #define ADC_FIFO_REG		0x0a	/* R: A/D FIFO reg */
44 #define DMATC_CLEAR_REG		0x0a	/* W: DMA Interrupt Clear reg */
45 #define TIMER_CLEAR_REG		0x0c	/* W: Timer Interrupt Clear reg */
46 #define CMD6_REG		0x0e	/* W: Command 6 reg */
47 #define CMD6_NRSE		BIT(0)
48 #define CMD6_ADCUNI		BIT(1)
49 #define CMD6_DACUNI(x)		BIT(2 + ((x) & 0x1))
50 #define CMD6_HFINTEN		BIT(5)
51 #define CMD6_DQINTEN		BIT(6)
52 #define CMD6_SCANUP		BIT(7)
53 #define CMD4_REG		0x0f	/* W: Command 3 reg */
54 #define CMD4_INTSCAN		BIT(0)
55 #define CMD4_EOIRCV		BIT(1)
56 #define CMD4_ECLKDRV		BIT(2)
57 #define CMD4_SEDIFF		BIT(3)
58 #define CMD4_ECLKRCV		BIT(4)
59 #define DIO_BASE_REG		0x10	/* R/W: 8255 DIO base reg */
60 #define COUNTER_A_BASE_REG	0x14	/* R/W: 8253 Counter A base reg */
61 #define COUNTER_B_BASE_REG	0x18	/* R/W: 8253 Counter B base reg */
62 #define CMD5_REG		0x1c	/* W: Command 5 reg */
63 #define CMD5_WRTPRT		BIT(2)
64 #define CMD5_DITHEREN		BIT(3)
65 #define CMD5_CALDACLD		BIT(4)
66 #define CMD5_SCLK		BIT(5)
67 #define CMD5_SDATA		BIT(6)
68 #define CMD5_EEPROMCS		BIT(7)
69 #define STAT2_REG		0x1d	/* R: Status 2 reg */
70 #define STAT2_PROMOUT		BIT(0)
71 #define STAT2_OUTA1		BIT(1)
72 #define STAT2_FIFONHF		BIT(2)
73 #define INTERVAL_COUNT_REG	0x1e	/* W: Interval Counter Data reg */
74 #define INTERVAL_STROBE_REG	0x1f	/* W: Interval Counter Strobe reg */
75 
76 #endif /* _NI_LABPC_REGS_H */
77