1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Midhunchandra Kodiyath <midhunchandra.kodiyath@intel.com> 26 * 27 */ 28 #ifndef _MEDIA__DRIVER_HWCMDS_H 29 #define _MEDIA__DRIVER_HWCMDS_H 30 #include "media_drv_hw.h" 31 #include "media_drv_init.h" 32 #define CMD(pipeline,op,sub_op) ((3 << 29) | \ 33 ((pipeline) << 27) | \ 34 ((op) << 24) | \ 35 ((sub_op) << 16)) 36 #define CMD_MI (0x0 << 29) 37 #define CMD_2D (0x2 << 29) 38 #define CMD_3D (0x3 << 29) 39 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23)) 40 #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23)) 41 #define BATCH_SIZE 0x80000 42 #define BATCH_RESERVED 0x10 43 #define MAX_BATCH_SIZE 0x400000 44 //PIPELINE CONTROL 45 #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16)) 46 #define CMD_PIPE_CONTROL_DEST_ADDR_TYPE (1 << 24) 47 #define CMD_PIPE_CONTROL_CS_STALL (1 << 20) 48 #define CMD_PIPE_CONTROL_NOWRITE (0 << 14) 49 #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14) 50 #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14) 51 #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14) 52 #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13) 53 #define CMD_PIPE_CONTROL_RT_FLUSH_ENABLE (1 << 12) 54 #define CMD_PIPE_CONTROL_INSTR_CI_ENABLE (1 << 11) 55 #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10) 56 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) 57 #define CMD_PIPE_CONTROL_FLUSH_ENABLE (1 << 7) 58 #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5) 59 #define CMD_PIPE_CONTROL_VF_CI_ENABLE (1 << 4) 60 #define CMD_PIPE_CONTROL_CONSTANT_CI_ENABLE (1 << 3) 61 #define CMD_PIPE_CONTROL_STATE_CI_ENABLE (1 << 2) 62 #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2) 63 #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2) 64 #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) 65 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) 66 #define CMD_PIPE_CONTROL_DWORD_LEN 3 67 //STATE_BASE_ADDRESS 68 #define BASE_ADDRESS_MODIFY (1 << 0) 69 #define CMD_STATE_BASE_ADDRESS_LEN 12//10 70 #define CMD_STATE_BASE_ADDRESS CMD(0,1,1) 71 //PIPELINE SELECT 72 #define CMD_PIPELINE_SELECT CMD(1, 1, 4) 73 #define PIPELINE_SELECT_3D 0 74 #define PIPELINE_SELECT_MEDIA 1 75 76 77 //MEDIA VFE STATE 78 #define CMD_MEDIA_VFE_STATE_LEN 8 79 #define CMD_MEDIA_VFE_STATE CMD(2, 0, 0) 80 81 //MEDIA CURBE LOAD 82 #define CMD_MEDIA_CURBE_LOAD CMD(2, 0, 1) 83 84 //ID LOAD 85 #define CMD_MEDIA_INTERFACE_LOAD CMD(2, 0, 2) 86 87 //MI PREDICATE 88 #define CMD_MI_SET_PREDICATE (CMD_MI | (1<<23)) 89 90 //MEDIA_OBJECT_WALKER 91 #define CMD_MEDIA_OBJECT_WALKER_LEN 17 92 #define CMD_MEDIA_OBJECT_WALKER CMD(2, 1, 3) 93 94 //MEDIA_OBJECT 95 #define CMD_MEDIA_OBJECT_LEN 6 96 #define CMD_MEDIA_OBJECT CMD(2, 1, 0) 97 98 //MI STORE DATA IMM 99 #define CMD_MI_STORE_DATA_IMM (CMD_MI | (1<<28)) 100 101 #define FLUSH_NONE 0x00 102 #define FLUSH_WRITE_CACHE 0x01 103 #define FLUSH_READ_CACHE 0x02 104 105 #define I_FRM 1 106 #define P_FRM 2 107 #define B_FRM 3 108 #define SINGLE_MODE 1 109 #define DUAL_MODE 2 110 #define TRI_MODE 3 111 #define QUAD_MODE 4 112 113 #define SCALE_SRC_Y 0 114 #define SCALE_DST_Y 1 115 116 //#define DEGREE_46 3 117 typedef struct media_curbe_scaling_data 118 { 119 UINT input_pic_width:16; 120 UINT input_pic_height:16; 121 UINT src_planar_y:32; 122 UINT dest_planar_y:32; 123 } CURBE_SCALING_DATA; 124 125 STATUS mediadrv_set_curbe_scaling (MEDIA_GPE_CTX * gpe_context, 126 SCALING_CURBE_PARAMS * params); 127 STATUS mediadrv_mi_store_data_imm_cmd (MEDIA_BATCH_BUFFER * batch, 128 MI_STORE_DATA_IMM_PARAMS * params); 129 STATUS media_object_walker_cmd (MEDIA_BATCH_BUFFER * batch, 130 MEDIA_OBJ_WALKER_PARAMS * params); 131 STATUS mediadrv_media_mi_set_predicate_cmd (MEDIA_BATCH_BUFFER * batch, 132 MI_SET_PREDICATE_PARAMS * params); 133 STATUS mediadrv_gen_media_curbe_load_cmd (MEDIA_BATCH_BUFFER * batch, 134 CURBE_LOAD_PARAMS * params); 135 STATUS mediadrv_gen_media_id_load_cmd (MEDIA_BATCH_BUFFER * batch, 136 ID_LOAD_PARAMS * params); 137 STATUS mediadrv_gen_media_vfe_state_cmd (MEDIA_BATCH_BUFFER * batch, 138 VFE_STATE_PARAMS * params); 139 STATUS mediadrv_gen_state_base_address_cmd (MEDIA_BATCH_BUFFER * batch, 140 STATE_BASE_ADDR_PARAMS * params); 141 STATUS mediadrv_gen_pipeline_select_cmd (MEDIA_BATCH_BUFFER * batch); 142 STATUS mediadrv_gen_pipe_ctrl_cmd (MEDIA_BATCH_BUFFER * batch, 143 PIPE_CONTROL_PARAMS * params); 144 145 STATUS 146 media_object_cmd (MEDIA_BATCH_BUFFER *batch, 147 MEDIA_OBJECT_PARAMS *params); 148 149 150 #define MI_FLUSH (CMD_MI | (0x4 << 23)) 151 #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0) 152 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2) 153 #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7) 154 155 #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12) 156 157 #endif 158