1 /* 2 * (C) Copyright 2011 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * based on kilauea.h 6 * by Stefan Roese, DENX Software Engineering, sr@denx.de. 7 * and Grant Erickson <gerickson@nuovations.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 /************************************************************************ 13 * io64.h - configuration for Guntermann & Drunck Io64 (405EX) 14 ***********************************************************************/ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /*----------------------------------------------------------------------- 20 * High Level Configuration Options 21 *----------------------------------------------------------------------*/ 22 #define CONFIG_IO64 1 /* Board is Io64 */ 23 #define CONFIG_405EX 1 /* Specifc 405EX support*/ 24 #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ 25 26 #ifndef CONFIG_SYS_TEXT_BASE 27 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 28 #endif 29 30 /* 31 * CHIP_21 errata 32 */ 33 #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY 34 35 /* 36 * Include common defines/options for all AMCC eval boards 37 */ 38 #define CONFIG_HOSTNAME io64 39 #define CONFIG_IDENT_STRING " io64 0.02" 40 #include "amcc-common.h" 41 42 #define CONFIG_BOARD_EARLY_INIT_F 43 #define CONFIG_BOARD_EARLY_INIT_R 44 #define CONFIG_MISC_INIT_R 45 #define CONFIG_LAST_STAGE_INIT 46 #define CONFIG_SYS_GENERIC_BOARD 47 48 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 49 50 /* new uImage format support */ 51 #define CONFIG_FIT 52 #define CONFIG_FIT_VERBOSE 53 54 /*----------------------------------------------------------------------- 55 * Base addresses -- Note these are effective addresses where the 56 * actual resources get mapped (not physical addresses) 57 *----------------------------------------------------------------------*/ 58 #define CONFIG_SYS_FLASH_BASE 0xFC000000 59 #define CONFIG_SYS_NVRAM_BASE 0xF0000000 60 #define CONFIG_SYS_FPGA0_BASE 0xF0100000 61 #define CONFIG_SYS_FPGA1_BASE 0xF0108000 62 #define CONFIG_SYS_LATCH_BASE 0xF0200000 63 64 /*----------------------------------------------------------------------- 65 * Initial RAM & Stack Pointer Configuration Options 66 * 67 * There are traditionally three options for the primordial 68 * (i.e. initial) stack usage on the 405-series: 69 * 70 * 1) On-chip Memory (OCM) (i.e. SRAM) 71 * 2) Data cache 72 * 3) SDRAM 73 * 74 * For the 405EX(r), there is no OCM, so we are left with (2) or (3) 75 * the latter of which is less than desireable since it requires 76 * setting up the SDRAM and ECC in assembly code. 77 * 78 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip 79 * select on the External Bus Controller (EBC) and then select a 80 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, 81 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and 82 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, 83 * physical SDRAM to use (3). 84 *-----------------------------------------------------------------------*/ 85 86 #define CONFIG_SYS_INIT_DCACHE_CS 4 87 88 #if defined(CONFIG_SYS_INIT_DCACHE_CS) 89 #define CONFIG_SYS_INIT_RAM_ADDR \ 90 (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */ 91 #else 92 #define CONFIG_SYS_INIT_RAM_ADDR \ 93 (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ 94 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ 95 96 #define CONFIG_SYS_INIT_RAM_SIZE \ 97 (4 << 10) /* 4 KiB */ 98 #define CONFIG_SYS_GBL_DATA_OFFSET \ 99 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 100 101 /* 102 * If the data cache is being used for the primordial stack and global 103 * data area, the POST word must be placed somewhere else. The General 104 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves 105 * its compare and mask register contents across reset, so it is used 106 * for the POST word. 107 */ 108 109 #if defined(CONFIG_SYS_INIT_DCACHE_CS) 110 # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 # define CONFIG_SYS_POST_WORD_ADDR \ 112 (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) 113 #else 114 # define CONFIG_SYS_INIT_EXTRA_SIZE 16 115 # define CONFIG_SYS_INIT_SP_OFFSET \ 116 (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) 117 # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR 118 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ 119 120 /*----------------------------------------------------------------------- 121 * Serial Port 122 *----------------------------------------------------------------------*/ 123 #define CONFIG_CONS_INDEX 1 /* Use UART0 */ 124 #define CONFIG_SYS_BASE_BAUD 691200 125 126 /*----------------------------------------------------------------------- 127 * Environment 128 *----------------------------------------------------------------------*/ 129 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 130 131 /*----------------------------------------------------------------------- 132 * FLASH related 133 *----------------------------------------------------------------------*/ 134 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 135 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 136 137 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 138 #define CONFIG_SYS_MAX_FLASH_BANKS 1 139 #define CONFIG_SYS_MAX_FLASH_SECT 512 140 141 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 142 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 143 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 145 #define CONFIG_SYS_FLASH_EMPTY_INFO 146 147 #ifdef CONFIG_ENV_IS_IN_FLASH 148 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ 149 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 150 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 151 152 /* Address and size of Redundant Environment Sector */ 153 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 154 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 155 #endif /* CONFIG_ENV_IS_IN_FLASH */ 156 157 /* Gbit PHYs */ 158 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 159 #define CONFIG_BITBANGMII_MULTI 160 161 #define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */ 162 #define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */ 163 164 #define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0" 165 166 #define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */ 167 #define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */ 168 169 #define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1" 170 171 /*----------------------------------------------------------------------- 172 * DDR SDRAM 173 *----------------------------------------------------------------------*/ 174 #define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */ 175 176 /* 177 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION 178 * 179 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx 180 * SDRAM Controller DDR autocalibration values and takes a lot longer 181 * to run than Method_B. 182 * (See the Method_A and Method_B algorithm discription in the file: 183 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) 184 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A 185 * 186 * DDR Autocalibration Method_B is the default. 187 */ 188 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION 189 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION 190 #undef CONFIG_PPC4xx_DDR_METHOD_A 191 192 #define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE) 193 194 /* DDR1/2 SDRAM Device Control Register Data Values */ 195 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ 196 SDRAM_RXBAS_SDSZ_128MB | \ 197 SDRAM_RXBAS_SDAM_MODE2 | \ 198 SDRAM_RXBAS_SDBE_ENABLE) 199 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE 200 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE 201 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE 202 #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ 203 SDRAM_MCOPT1_4_BANKS | \ 204 SDRAM_MCOPT1_DDR2_TYPE | \ 205 SDRAM_MCOPT1_QDEP | \ 206 SDRAM_MCOPT1_DCOO_DISABLED) 207 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 208 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ 209 SDRAM_MODT_EB0R_ENABLE) 210 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 211 #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ 212 SDRAM_CODT_CKLZ_36OHM | \ 213 SDRAM_CODT_DQS_1_8_V_DDR2 | \ 214 SDRAM_CODT_IO_NMODE) 215 #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) 216 #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ 217 SDRAM_INITPLR_IMWT_ENCODE(80) | \ 218 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) 219 #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ 220 SDRAM_INITPLR_IMWT_ENCODE(3) | \ 221 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ 222 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ 223 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) 224 #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ 225 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 226 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 227 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ 228 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) 229 #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ 230 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 231 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 232 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ 233 SDRAM_INITPLR_IMA_ENCODE(0)) 234 #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ 235 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 236 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 237 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ 238 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ 239 JEDEC_MA_EMR_RTT_75OHM)) 240 #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ 241 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 242 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 243 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ 244 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ 245 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ 246 JEDEC_MA_MR_BLEN_4 | \ 247 JEDEC_MA_MR_DLL_RESET)) 248 #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ 249 SDRAM_INITPLR_IMWT_ENCODE(3) | \ 250 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ 251 SDRAM_INITPLR_IBA_ENCODE(0x0) | \ 252 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) 253 #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ 254 SDRAM_INITPLR_IMWT_ENCODE(26) | \ 255 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) 256 #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ 257 SDRAM_INITPLR_IMWT_ENCODE(26) | \ 258 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) 259 #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ 260 SDRAM_INITPLR_IMWT_ENCODE(26) | \ 261 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) 262 #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ 263 SDRAM_INITPLR_IMWT_ENCODE(26) | \ 264 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) 265 #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ 266 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 267 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 268 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ 269 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ 270 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ 271 JEDEC_MA_MR_BLEN_4)) 272 #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ 273 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 274 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 275 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ 276 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ 277 JEDEC_MA_EMR_RDQS_DISABLE | \ 278 JEDEC_MA_EMR_DQS_DISABLE | \ 279 JEDEC_MA_EMR_RTT_DISABLED | \ 280 JEDEC_MA_EMR_ODS_NORMAL)) 281 #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ 282 SDRAM_INITPLR_IMWT_ENCODE(2) | \ 283 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ 284 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ 285 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ 286 JEDEC_MA_EMR_RDQS_DISABLE | \ 287 JEDEC_MA_EMR_DQS_DISABLE | \ 288 JEDEC_MA_EMR_RTT_DISABLED | \ 289 JEDEC_MA_EMR_ODS_NORMAL)) 290 #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) 291 #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) 292 #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ 293 SDRAM_RQDC_RQFD_ENCODE(56)) 294 #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) 295 #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) 296 #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ 297 SDRAM_DLCR_DLCS_CONT_DONE | \ 298 SDRAM_DLCR_DLCV_ENCODE(165)) 299 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) 300 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 301 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ 302 SDRAM_SDTR1_RTW_2_CLK | \ 303 SDRAM_SDTR1_WTWO_1_CLK | \ 304 SDRAM_SDTR1_RTRO_1_CLK) 305 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ 306 SDRAM_SDTR2_WTR_2_CLK | \ 307 SDRAM_SDTR2_XSNR_32_CLK | \ 308 SDRAM_SDTR2_WPC_4_CLK | \ 309 SDRAM_SDTR2_RPC_2_CLK | \ 310 SDRAM_SDTR2_RP_3_CLK | \ 311 SDRAM_SDTR2_RRD_2_CLK) 312 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \ 313 SDRAM_SDTR3_RC_ENCODE(12) | \ 314 SDRAM_SDTR3_XCS | \ 315 SDRAM_SDTR3_RFC_ENCODE(21)) 316 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ 317 SDRAM_MMODE_DCL_DDR2_5_0_CLK | \ 318 SDRAM_MMODE_BLEN_4) 319 #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ 320 SDRAM_MEMODE_RTT_75OHM) 321 322 /*----------------------------------------------------------------------- 323 * I2C 324 *----------------------------------------------------------------------*/ 325 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 326 327 #define CONFIG_PCA9698 1 /* NXP PCA9698 */ 328 329 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ 330 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 331 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 332 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 333 334 /* I2C bootstrap EEPROM */ 335 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 336 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 337 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 338 339 /* Temp sensor/hwmon/dtt */ 340 #define CONFIG_DTT_LM63 1 /* National LM63 */ 341 #define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */ 342 #define CONFIG_DTT_PWM_LOOKUPTABLE \ 343 { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ 344 { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } 345 #define CONFIG_DTT_TACH_LIMIT 0xa10 346 347 /*----------------------------------------------------------------------- 348 * Ethernet 349 *----------------------------------------------------------------------*/ 350 #define CONFIG_M88E1111_PHY 1 351 #define CONFIG_IBM_EMAC4_V4 1 352 #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII 353 #define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */ 354 355 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ 356 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 357 358 #define CONFIG_HAS_ETH0 1 359 360 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ 361 #define CONFIG_PHY1_ADDR 0x13 362 363 /* Debug messages for the DDR autocalibration */ 364 #define CONFIG_AUTOCALIB "silent\0" 365 366 /* 367 * Default environment variables 368 */ 369 #define CONFIG_EXTRA_ENV_SETTINGS \ 370 CONFIG_AMCC_DEF_ENV \ 371 CONFIG_AMCC_DEF_ENV_POWERPC \ 372 CONFIG_AMCC_DEF_ENV_PPC_OLD \ 373 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 374 "logversion=2\0" \ 375 "kernel_addr=fc000000\0" \ 376 "fdt_addr=fc1e0000\0" \ 377 "ramdisk_addr=fc200000\0" \ 378 "pciconfighost=1\0" \ 379 "pcie_mode=RP:RP\0" \ 380 "" 381 382 /* 383 * Commands additional to the ones defined in amcc-common.h 384 */ 385 #define CONFIG_CMD_CHIP_CONFIG 386 #define CONFIG_CMD_DTT 387 388 #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY 389 390 /* POST support */ 391 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ 392 CONFIG_SYS_POST_CPU | \ 393 CONFIG_SYS_POST_ETHER | \ 394 CONFIG_SYS_POST_I2C | \ 395 CONFIG_SYS_POST_MEMORY_ON | \ 396 CONFIG_SYS_POST_UART) 397 398 /* Define here the base-addresses of the UARTs to test in POST */ 399 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ 400 CONFIG_SYS_NS16550_COM2 } 401 402 #define CONFIG_LOGBUFFER 403 #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ 404 405 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 406 407 /*----------------------------------------------------------------------- 408 * External Bus Controller (EBC) Setup 409 *----------------------------------------------------------------------*/ 410 411 /* Memory Bank 0 (NOR-flash) */ 412 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ 413 EBC_BXAP_TWT_ENCODE(11) | \ 414 EBC_BXAP_BCE_DISABLE | \ 415 EBC_BXAP_BCT_2TRANS | \ 416 EBC_BXAP_CSN_ENCODE(0) | \ 417 EBC_BXAP_OEN_ENCODE(0) | \ 418 EBC_BXAP_WBN_ENCODE(1) | \ 419 EBC_BXAP_WBF_ENCODE(2) | \ 420 EBC_BXAP_TH_ENCODE(2) | \ 421 EBC_BXAP_RE_DISABLED | \ 422 EBC_BXAP_SOR_NONDELAYED | \ 423 EBC_BXAP_BEM_WRITEONLY | \ 424 EBC_BXAP_PEN_DISABLED) 425 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ 426 EBC_BXCR_BS_64MB | \ 427 EBC_BXCR_BU_RW | \ 428 EBC_BXCR_BW_16BIT) 429 430 /* Memory Bank 1 (NVRAM/Uart) */ 431 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \ 432 EBC_BXAP_FWT_ENCODE(8) | \ 433 EBC_BXAP_BWT_ENCODE(4) | \ 434 EBC_BXAP_BCE_DISABLE | \ 435 EBC_BXAP_BCT_2TRANS | \ 436 EBC_BXAP_CSN_ENCODE(0) | \ 437 EBC_BXAP_OEN_ENCODE(1) | \ 438 EBC_BXAP_WBN_ENCODE(1) | \ 439 EBC_BXAP_WBF_ENCODE(1) | \ 440 EBC_BXAP_TH_ENCODE(2) | \ 441 EBC_BXAP_RE_DISABLED | \ 442 EBC_BXAP_SOR_NONDELAYED | \ 443 EBC_BXAP_BEM_WRITEONLY | \ 444 EBC_BXAP_PEN_DISABLED) 445 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \ 446 EBC_BXCR_BS_1MB | \ 447 EBC_BXCR_BU_RW | \ 448 EBC_BXCR_BW_8BIT) 449 450 /* Memory Bank 2 (FPGA) */ 451 #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ 452 EBC_BXAP_TWT_ENCODE(5) | \ 453 EBC_BXAP_BCE_DISABLE | \ 454 EBC_BXAP_BCT_2TRANS | \ 455 EBC_BXAP_CSN_ENCODE(0) | \ 456 EBC_BXAP_OEN_ENCODE(2) | \ 457 EBC_BXAP_WBN_ENCODE(1) | \ 458 EBC_BXAP_WBF_ENCODE(1) | \ 459 EBC_BXAP_TH_ENCODE(0) | \ 460 EBC_BXAP_RE_DISABLED | \ 461 EBC_BXAP_SOR_NONDELAYED | \ 462 EBC_BXAP_BEM_WRITEONLY | \ 463 EBC_BXAP_PEN_DISABLED) 464 #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ 465 EBC_BXCR_BS_1MB | \ 466 EBC_BXCR_BU_RW | \ 467 EBC_BXCR_BW_16BIT) 468 469 /* Memory Bank 3 (Latches) */ 470 #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ 471 EBC_BXAP_FWT_ENCODE(8) | \ 472 EBC_BXAP_BWT_ENCODE(4) | \ 473 EBC_BXAP_BCE_DISABLE | \ 474 EBC_BXAP_BCT_2TRANS | \ 475 EBC_BXAP_CSN_ENCODE(0) | \ 476 EBC_BXAP_OEN_ENCODE(1) | \ 477 EBC_BXAP_WBN_ENCODE(1) | \ 478 EBC_BXAP_WBF_ENCODE(1) | \ 479 EBC_BXAP_TH_ENCODE(2) | \ 480 EBC_BXAP_RE_DISABLED | \ 481 EBC_BXAP_SOR_NONDELAYED | \ 482 EBC_BXAP_BEM_WRITEONLY | \ 483 EBC_BXAP_PEN_DISABLED) 484 #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ 485 EBC_BXCR_BS_1MB | \ 486 EBC_BXCR_BU_RW | \ 487 EBC_BXCR_BW_16BIT) 488 489 /* EBC peripherals */ 490 491 #define CONFIG_SYS_FPGA_BASE(k) \ 492 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) 493 494 #define CONFIG_SYS_FPGA_DONE(k) \ 495 (k ? 0x0040 : 0x0080) 496 497 #define CONFIG_SYS_FPGA_COUNT 2 498 499 #define CONFIG_SYS_FPGA_PTR { \ 500 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \ 501 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE } 502 503 #define CONFIG_SYS_FPGA_COMMON 504 505 #define CONFIG_SYS_LATCH0_RESET 0xffff 506 #define CONFIG_SYS_LATCH0_BOOT 0xffff 507 #define CONFIG_SYS_LATCH1_RESET 0xffbf 508 #define CONFIG_SYS_LATCH1_BOOT 0xffff 509 510 /*----------------------------------------------------------------------- 511 * GPIO Setup 512 *----------------------------------------------------------------------*/ 513 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \ 514 { \ 515 /* GPIO Core 0 */ \ 516 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \ 517 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \ 518 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \ 519 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \ 520 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \ 521 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \ 522 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \ 523 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \ 524 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \ 525 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \ 526 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \ 527 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \ 528 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \ 529 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \ 530 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \ 531 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \ 532 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \ 533 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \ 534 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \ 535 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \ 536 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \ 537 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \ 538 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \ 539 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \ 540 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \ 541 {GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \ 542 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \ 543 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \ 544 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \ 545 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \ 546 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \ 547 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \ 548 } \ 549 } 550 551 #define CONFIG_SYS_GPIO_STARTUP_FINISHED 15 552 #define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14 553 554 #endif /* __CONFIG_H */ 555