1 /* $OpenBSD: azalia.h,v 1.69 2019/10/14 02:04:35 jcs Exp $ */ 2 /* $NetBSD: azalia.h,v 1.6 2006/01/16 14:15:26 kent Exp $ */ 3 4 /*- 5 * Copyright (c) 2005 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by TAMURA Kent 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/audioio.h> 35 36 /* ---------------------------------------------------------------- 37 * High Definition Audio constant values 38 * ---------------------------------------------------------------- */ 39 40 /* High Definition Audio registers */ 41 #define HDA_GCAP 0x000 /* 2 */ 42 #define HDA_GCAP_OSS(x) ((x & 0xf000) >> 12) 43 #define HDA_GCAP_ISS(x) ((x & 0x0f00) >> 8) 44 #define HDA_GCAP_BSS(x) ((x & 0x00f8) >> 3) 45 #define HDA_GCAP_NSDO_MASK 0x0006 46 #define HDA_GCAP_NSDO_1 0x0000 47 #define HDA_GCAP_NSDO_2 0x0002 48 #define HDA_GCAP_NSDO_4 0x0004 49 #define HDA_GCAP_NSDO_RESERVED 0x0006 50 #define HDA_GCAP_64OK 0x0001 51 #define HDA_VMIN 0x002 /* 1 */ 52 #define HDA_VMAJ 0x003 /* 1 */ 53 #define HDA_OUTPAY 0x004 /* 2 */ 54 #define HDA_INPAY 0x006 /* 2 */ 55 #define HDA_GCTL 0x008 /* 4 */ 56 #define HDA_GCTL_UNSOL 0x00000100 57 #define HDA_GCTL_FCNTRL 0x00000002 58 #define HDA_GCTL_CRST 0x00000001 59 #define HDA_WAKEEN 0x00c /* 2 */ 60 #define HDA_WAKEEN_SDIWEN 0x7fff 61 #define HDA_STATESTS 0x00e /* 2 */ 62 #define HDA_STATESTS_SDIWAKE 0x7fff 63 #define HDA_GSTS 0x010 /* 2 */ 64 #define HDA_GSTS_FSTS 0x0002 65 #define HDA_OUTSTRMPAY 0x018 /* 2 */ 66 #define HDA_INSTRMPAY 0x01a /* 2 */ 67 #define HDA_INTCTL 0x020 /* 4 */ 68 #define HDA_INTCTL_GIE 0x80000000 69 #define HDA_INTCTL_CIE 0x40000000 70 #define HDA_INTCTL_SIE 0x3fffffff 71 #define HDA_INTSTS 0x024 /* 4 */ 72 #define HDA_INTSTS_GIS 0x80000000 73 #define HDA_INTSTS_CIS 0x40000000 74 #define HDA_INTSTS_SIS 0x3fffffff 75 #define HDA_WALCLK 0x030 /* 4 */ 76 #define HDA_SSYNC 0x034 /* 4 */ 77 #define HDA_SSYNC_SSYNC 0x3fffffff 78 #define HDA_CORBLBASE 0x040 /* 4 */ 79 #define HDA_CORBUBASE 0x044 /* 4 */ 80 #define HDA_CORBWP 0x048 /* 2 */ 81 #define HDA_CORBWP_CORBWP 0x00ff 82 #define HDA_CORBRP 0x04a /* 2 */ 83 #define HDA_CORBRP_CORBRPRST 0x8000 84 #define HDA_CORBRP_CORBRP 0x00ff 85 #define HDA_CORBCTL 0x04c /* 1 */ 86 #define HDA_CORBCTL_CORBRUN 0x02 87 #define HDA_CORBCTL_CMEIE 0x01 88 #define HDA_CORBSTS 0x04d /* 1 */ 89 #define HDA_CORBSTS_CMEI 0x01 90 #define HDA_CORBSIZE 0x04e /* 1 */ 91 #define HDA_CORBSIZE_CORBSZCAP_MASK 0xf0 92 #define HDA_CORBSIZE_CORBSZCAP_2 0x10 93 #define HDA_CORBSIZE_CORBSZCAP_16 0x20 94 #define HDA_CORBSIZE_CORBSZCAP_256 0x40 95 #define HDA_CORBSIZE_CORBSIZE_MASK 0x03 96 #define HDA_CORBSIZE_CORBSIZE_2 0x00 97 #define HDA_CORBSIZE_CORBSIZE_16 0x01 98 #define HDA_CORBSIZE_CORBSIZE_256 0x02 99 #define HDA_RIRBLBASE 0x050 /* 4 */ 100 #define HDA_RIRBUBASE 0x054 /* 4 */ 101 #define HDA_RIRBWP 0x058 /* 2 */ 102 #define HDA_RIRBWP_RIRBWPRST 0x8000 103 #define HDA_RIRBWP_RIRBWP 0x00ff 104 #define HDA_RINTCNT 0x05a /* 2 */ 105 #define HDA_RINTCNT_RINTCNT 0x00ff 106 #define HDA_RIRBCTL 0x05c /* 1 */ 107 #define HDA_RIRBCTL_RIRBOIC 0x04 108 #define HDA_RIRBCTL_RIRBDMAEN 0x02 109 #define HDA_RIRBCTL_RINTCTL 0x01 110 #define HDA_RIRBSTS 0x05d /* 1 */ 111 #define HDA_RIRBSTS_RIRBOIS 0x04 112 #define HDA_RIRBSTS_RINTFL 0x01 113 #define HDA_RIRBSIZE 0x05e /* 1 */ 114 #define HDA_RIRBSIZE_RIRBSZCAP_MASK 0xf0 115 #define HDA_RIRBSIZE_RIRBSZCAP_2 0x10 116 #define HDA_RIRBSIZE_RIRBSZCAP_16 0x20 117 #define HDA_RIRBSIZE_RIRBSZCAP_256 0x40 118 #define HDA_RIRBSIZE_RIRBSIZE_MASK 0x03 119 #define HDA_RIRBSIZE_RIRBSIZE_2 0x00 120 #define HDA_RIRBSIZE_RIRBSIZE_16 0x01 121 #define HDA_RIRBSIZE_RIRBSIZE_256 0x02 122 #define HDA_IC 0x060 /* 4 */ 123 #define HDA_IR 0x064 /* 4 */ 124 #define HDA_IRS 0x068 /* 2 */ 125 #define HDA_IRS_IRRADD 0x00f0 126 #define HDA_IRS_IRRUNSOL 0x0008 127 #define HDA_IRS_IRV 0x0002 128 #define HDA_IRS_ICB 0x0001 129 #define HDA_DPLBASE 0x070 /* 4 */ 130 #define HDA_DPLBASE_DPLBASE 0xffffff80 131 #define HDA_DPLBASE_ENABLE 0x00000001 132 #define HDA_DPUBASE 0x074 133 134 #define HDA_SD_BASE 0x080 135 #define HDA_SD_CTL 0x00 /* 2 */ 136 #define HDA_SD_CTL_DEIE 0x0010 137 #define HDA_SD_CTL_FEIE 0x0008 138 #define HDA_SD_CTL_IOCE 0x0004 139 #define HDA_SD_CTL_RUN 0x0002 140 #define HDA_SD_CTL_SRST 0x0001 141 #define HDA_SD_CTL2 0x02 /* 1 */ 142 #define HDA_SD_CTL2_STRM 0xf0 143 #define HDA_SD_CTL2_STRM_SHIFT 4 144 #define HDA_SD_CTL2_DIR 0x08 145 #define HDA_SD_CTL2_TP 0x04 146 #define HDA_SD_CTL2_STRIPE 0x03 147 #define HDA_SD_STS 0x03 /* 1 */ 148 #define HDA_SD_STS_FIFORDY 0x20 149 #define HDA_SD_STS_DESE 0x10 150 #define HDA_SD_STS_FIFOE 0x08 151 #define HDA_SD_STS_BCIS 0x04 152 #define HDA_SD_LPIB 0x04 /* 4 */ 153 #define HDA_SD_CBL 0x08 /* 4 */ 154 #define HDA_SD_LVI 0x0c /* 2 */ 155 #define HDA_SD_LVI_LVI 0x00ff 156 #define HDA_SD_FIFOW 0x0e /* 2 */ 157 #define HDA_SD_FIFOS 0x10 /* 2 */ 158 #define HDA_SD_FMT 0x12 /* 2 */ 159 #define HDA_SD_FMT_BASE 0x4000 160 #define HDA_SD_FMT_BASE_48 0x0000 161 #define HDA_SD_FMT_BASE_44 0x4000 162 #define HDA_SD_FMT_MULT 0x3800 163 #define HDA_SD_FMT_MULT_X1 0x0000 164 #define HDA_SD_FMT_MULT_X2 0x0800 165 #define HDA_SD_FMT_MULT_X3 0x1000 166 #define HDA_SD_FMT_MULT_X4 0x1800 167 #define HDA_SD_FMT_DIV 0x0700 168 #define HDA_SD_FMT_DIV_BY1 0x0000 169 #define HDA_SD_FMT_DIV_BY2 0x0100 170 #define HDA_SD_FMT_DIV_BY3 0x0200 171 #define HDA_SD_FMT_DIV_BY4 0x0300 172 #define HDA_SD_FMT_DIV_BY5 0x0400 173 #define HDA_SD_FMT_DIV_BY6 0x0500 174 #define HDA_SD_FMT_DIV_BY7 0x0600 175 #define HDA_SD_FMT_DIV_BY8 0x0700 176 #define HDA_SD_FMT_BITS 0x0070 177 #define HDA_SD_FMT_BITS_8_16 0x0000 178 #define HDA_SD_FMT_BITS_16_16 0x0010 179 #define HDA_SD_FMT_BITS_20_32 0x0020 180 #define HDA_SD_FMT_BITS_24_32 0x0030 181 #define HDA_SD_FMT_BITS_32_32 0x0040 182 #define HDA_SD_FMT_CHAN 0x000f 183 #define HDA_SD_BDPL 0x18 /* 4 */ 184 #define HDA_SD_BDPU 0x1c /* 4 */ 185 #define HDA_SD_SIZE 0x20 186 187 /* CORB commands */ 188 #define CORB_GET_PARAMETER 0xf00 189 #define COP_VENDOR_ID 0x00 190 #define COP_VID_VENDOR(x) (x >> 16) 191 #define COP_VID_DEVICE(x) (x & 0xffff) 192 #define COP_REVISION_ID 0x02 193 #define COP_RID_MAJ(x) ((x >> 20) & 0x0f) 194 #define COP_RID_MIN(x) ((x >> 16) & 0x0f) 195 #define COP_RID_REVISION(x) ((x >> 8) & 0xff) 196 #define COP_RID_STEPPING(x) (x & 0xff) 197 #define COP_SUBORDINATE_NODE_COUNT 0x04 198 #define COP_START_NID(x) ((x & 0x00ff0000) >> 16) 199 #define COP_NSUBNODES(x) (x & 0x000000ff) 200 #define COP_FUNCTION_GROUP_TYPE 0x05 201 #define COP_FTYPE(x) (x & 0x000000ff) 202 #define COP_FTYPE_RESERVED 0x01 203 #define COP_FTYPE_AUDIO 0x01 204 #define COP_FTYPE_MODEM 0x02 205 #define COP_AUDIO_FUNCTION_GROUP_CAPABILITY 0x08 206 #define COP_AUDIO_WIDGET_CAP 0x09 207 #define COP_AWCAP_TYPE(x) ((x >> 20) & 0xf) 208 #define COP_AWTYPE_AUDIO_OUTPUT 0x0 209 #define COP_AWTYPE_AUDIO_INPUT 0x1 210 #define COP_AWTYPE_AUDIO_MIXER 0x2 211 #define COP_AWTYPE_AUDIO_SELECTOR 0x3 212 #define COP_AWTYPE_PIN_COMPLEX 0x4 213 #define COP_AWTYPE_POWER 0x5 214 #define COP_AWTYPE_VOLUME_KNOB 0x6 215 #define COP_AWTYPE_BEEP_GENERATOR 0x7 216 #define COP_AWTYPE_VENDOR_DEFINED 0xf 217 #define COP_AWCAP_STEREO 0x001 218 #define COP_AWCAP_INAMP 0x002 219 #define COP_AWCAP_OUTAMP 0x004 220 #define COP_AWCAP_AMPOV 0x008 221 #define COP_AWCAP_FORMATOV 0x010 222 #define COP_AWCAP_STRIPE 0x020 223 #define COP_AWCAP_PROC 0x040 224 #define COP_AWCAP_UNSOL 0x080 225 #define COP_AWCAP_CONNLIST 0x100 226 #define COP_AWCAP_DIGITAL 0x200 227 #define COP_AWCAP_POWER 0x400 228 #define COP_AWCAP_LRSWAP 0x800 229 #define COP_AWCAP_DELAY(x) ((x >> 16) & 0xf) 230 #define COP_PCM 0x0a 231 #define COP_PCM_B32 0x00100000 232 #define COP_PCM_B24 0x00080000 233 #define COP_PCM_B20 0x00040000 234 #define COP_PCM_B16 0x00020000 235 #define COP_PCM_B8 0x00010000 236 #define COP_PCM_R3840 0x00000800 237 #define COP_PCM_R1920 0x00000400 238 #define COP_PCM_R1764 0x00000200 239 #define COP_PCM_R960 0x00000100 240 #define COP_PCM_R882 0x00000080 241 #define COP_PCM_R480 0x00000040 242 #define COP_PCM_R441 0x00000020 243 #define COP_PCM_R320 0x00000010 244 #define COP_PCM_R220 0x00000008 245 #define COP_PCM_R160 0x00000004 246 #define COP_PCM_R110 0x00000002 247 #define COP_PCM_R80 0x00000001 248 #define COP_STREAM_FORMATS 0x0b 249 #define COP_STREAM_FORMAT_PCM 0x00000001 250 #define COP_STREAM_FORMAT_FLOAT32 0x00000002 251 #define COP_STREAM_FORMAT_AC3 0x00000003 252 #define COP_PINCAP 0x0c 253 #define COP_PINCAP_IMPEDANCE 0x00000001 254 #define COP_PINCAP_TRIGGER 0x00000002 255 #define COP_PINCAP_PRESENCE 0x00000004 256 #define COP_PINCAP_HEADPHONE 0x00000008 257 #define COP_PINCAP_OUTPUT 0x00000010 258 #define COP_PINCAP_INPUT 0x00000020 259 #define COP_PINCAP_BALANCE 0x00000040 260 #define COP_PINCAP_HDMI 0x00000080 261 #define COP_PINCAP_VREF(x) ((x >> 8) & 0xff) 262 #define COP_PINCAP_EAPD 0x00010000 263 #define COP_INPUT_AMPCAP 0x0d 264 #define COP_AMPCAP_OFFSET(x) (x & 0x0000007f) 265 #define COP_AMPCAP_NUMSTEPS(x) ((x >> 8) & 0x7f) 266 #define COP_AMPCAP_STEPSIZE(x) ((x >> 16) & 0x7f) 267 #define COP_AMPCAP_CTLOFF(x) ((x >> 24) & 0x7f) 268 #define COP_AMPCAP_MUTE 0x80000000 269 #define COP_CONNECTION_LIST_LENGTH 0x0e 270 #define COP_CLL_LONG 0x00000080 271 #define COP_CLL_LENGTH(x) (x & 0x0000007f) 272 #define COP_SUPPORTED_POWER_STATES 0x0f 273 #define COP_PROCESSING_CAPABILITIES 0x10 274 #define COP_GPIO_COUNT 0x11 275 #define COP_GPIO_GPIOS(x) (x & 0xff) 276 #define COP_GPIO_GPOS(x) ((x >> 8) & 0xff) 277 #define COP_GPIO_GPIS(x) ((x >> 16) & 0xff) 278 #define COP_GPIO_UNSOL 0x40000000 279 #define COP_GPIO_WAKE 0x80000000 280 #define COP_OUTPUT_AMPCAP 0x12 281 #define COP_VOLUME_KNOB_CAPABILITIES 0x13 282 #define COP_VKCAP_DELTA 0x00000080 283 #define COP_VKCAP_NUMSTEPS(x) (x & 0x7f) 284 #define CORB_GET_CONNECTION_SELECT_CONTROL 0xf01 285 #define CORB_CSC_INDEX(x) (x & 0xff) 286 #define CORB_SET_CONNECTION_SELECT_CONTROL 0x701 287 #define CORB_GET_CONNECTION_LIST_ENTRY 0xf02 288 #define CORB_GET_PROCESSING_STATE 0xf03 289 #define CORB_SET_PROCESSING_STATE 0x703 290 #define CORB_GET_COEFFICIENT_INDEX 0xd00 291 #define CORB_SET_COEFFICIENT_INDEX 0x500 292 #define CORB_GET_PROCESSING_COEFFICIENT 0xc00 293 #define CORB_SET_PROCESSING_COEFFICIENT 0x400 294 #define CORB_GET_AMPLIFIER_GAIN_MUTE 0xb00 295 #define CORB_GAGM_INPUT 0x0000 296 #define CORB_GAGM_OUTPUT 0x8000 297 #define CORB_GAGM_RIGHT 0x0000 298 #define CORB_GAGM_LEFT 0x2000 299 #define CORB_GAGM_MUTE 0x00000080 300 #define CORB_GAGM_GAIN(x) (x & 0x0000007f) 301 #define CORB_SET_AMPLIFIER_GAIN_MUTE 0x300 302 #define CORB_AGM_GAIN_MASK 0x007f 303 #define CORB_AGM_MUTE 0x0080 304 #define CORB_AGM_INDEX_SHIFT 8 305 #define CORB_AGM_RIGHT 0x1000 306 #define CORB_AGM_LEFT 0x2000 307 #define CORB_AGM_INPUT 0x4000 308 #define CORB_AGM_OUTPUT 0x8000 309 #define CORB_GET_CONVERTER_FORMAT 0xa00 310 #define CORB_SET_CONVERTER_FORMAT 0x200 311 #define CORB_GET_DIGITAL_CONTROL 0xf0d 312 #define CORB_SET_DIGITAL_CONTROL_L 0x70d 313 #define CORB_SET_DIGITAL_CONTROL_H 0x70e 314 #define CORB_DCC_DIGEN 0x01 315 #define CORB_DCC_V 0x02 316 #define CORB_DCC_VCFG 0x04 317 #define CORB_DCC_PRE 0x08 318 #define CORB_DCC_COPY 0x10 319 #define CORB_DCC_NAUDIO 0x20 320 #define CORB_DCC_PRO 0x40 321 #define CORB_DCC_L 0x80 322 #define CORB_DCC_CC(x) ((x >> 8) & 0x7f) 323 #define CORB_GET_POWER_STATE 0xf05 324 #define CORB_SET_POWER_STATE 0x705 325 #define CORB_PS_D0 0x0 326 #define CORB_PS_D1 0x1 327 #define CORB_PS_D2 0x2 328 #define CORB_PS_D3 0x3 329 #define CORB_GET_CONVERTER_STREAM_CHANNEL 0xf06 330 #define CORB_SET_CONVERTER_STREAM_CHANNEL 0x706 331 #define CORB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04 332 #define CORB_SET_INPUT_CONVERTER_SDI_SELECT 0x704 333 #define CORB_GET_PIN_WIDGET_CONTROL 0xf07 334 #define CORB_SET_PIN_WIDGET_CONTROL 0x707 335 #define CORB_PWC_HEADPHONE 0x80 336 #define CORB_PWC_OUTPUT 0x40 337 #define CORB_PWC_INPUT 0x20 338 #define CORB_PWC_VREF_MASK 0x07 339 #define CORB_PWC_VREF_HIZ 0x00 340 #define CORB_PWC_VREF_50 0x01 341 #define CORB_PWC_VREF_GND 0x02 342 #define CORB_PWC_VREF_80 0x04 343 #define CORB_PWC_VREF_100 0x05 344 #define CORB_GET_UNSOLICITED_RESPONSE 0xf08 345 #define CORB_SET_UNSOLICITED_RESPONSE 0x708 346 #define CORB_UNSOL_ENABLE 0x80 347 #define CORB_UNSOL_TAG(x) (x & 0x3f) 348 #define CORB_GET_PIN_SENSE 0xf09 349 #define CORB_PS_PRESENCE 0x80000000 350 #define CORB_PS_IMPEDANCE(x) (x & 0x7fffffff) 351 #define CORB_EXECUTE_PIN_SENSE 0x709 352 #define CORB_PS_RIGHT 0x1 353 #define CORB_GET_EAPD_BTL_ENABLE 0xf0c 354 #define CORB_SET_EAPD_BTL_ENABLE 0x70c 355 #define CORB_EAPD_BTL 0x01 356 #define CORB_EAPD_EAPD 0x02 357 #define CORB_EAPD_LRSWAP 0x04 358 #define CORB_GET_GPI_DATA 0xf10 359 #define CORB_SET_GPI_DATA 0x710 360 #define CORB_GET_GPI_WAKE_ENABLE_MASK 0xf11 361 #define CORB_SET_GPI_WAKE_ENABLE_MASK 0x711 362 #define CORB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12 363 #define CORB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712 364 #define CORB_GET_GPI_STICKY_MASK 0xf13 365 #define CORB_SET_GPI_STICKY_MASK 0x713 366 #define CORB_GET_GPO_DATA 0xf14 367 #define CORB_SET_GPO_DATA 0x714 368 #define CORB_GET_GPIO_DATA 0xf15 369 #define CORB_SET_GPIO_DATA 0x715 370 #define CORB_GET_GPIO_ENABLE_MASK 0xf16 371 #define CORB_SET_GPIO_ENABLE_MASK 0x716 372 #define CORB_GET_GPIO_DIRECTION 0xf17 373 #define CORB_SET_GPIO_DIRECTION 0x717 374 #define CORB_GET_GPIO_WAKE_ENABLE_MASK 0xf18 375 #define CORB_SET_GPIO_WAKE_ENABLE_MASK 0x718 376 #define CORB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19 377 #define CORB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719 378 #define CORB_GET_GPIO_STICKY_MASK 0xf1a 379 #define CORB_SET_GPIO_STICKY_MASK 0x71a 380 #define CORB_GET_GPIO_POLARITY 0xfe7 381 #define CORB_SET_GPIO_POLARITY 0x7e7 382 #define CORB_GET_BEEP_GENERATION 0xf0a 383 #define CORB_SET_BEEP_GENERATION 0x70a 384 #define CORB_GET_VOLUME_KNOB 0xf0f 385 #define CORB_SET_VOLUME_KNOB 0x70f 386 #define CORB_VKNOB_DIRECT 0x80 387 #define CORB_VKNOB_VOLUME(x) (x & 0x7f) 388 #define CORB_GET_SUBSYSTEM_ID 0xf20 389 #define CORB_SET_SUBSYSTEM_ID_1 0x720 390 #define CORB_SET_SUBSYSTEM_ID_2 0x721 391 #define CORB_SET_SUBSYSTEM_ID_3 0x722 392 #define CORB_SET_SUBSYSTEM_ID_4 0x723 393 #define CORB_GET_CONFIGURATION_DEFAULT 0xf1c 394 #define CORB_SET_CONFIGURATION_DEFAULT_1 0x71c 395 #define CORB_SET_CONFIGURATION_DEFAULT_2 0x71d 396 #define CORB_SET_CONFIGURATION_DEFAULT_3 0x71e 397 #define CORB_SET_CONFIGURATION_DEFAULT_4 0x71f 398 #define CORB_CD_SEQUENCE(x) (x & 0x0000000f) 399 #define CORB_CD_SEQUENCE_MAX 0x0f 400 #define CORB_CD_ASSOCIATION(x) ((x >> 4) & 0xf) 401 #define CORB_CD_ASSOCIATION_MAX 0x0f 402 #define CORB_CD_MISC_MASK 0x00000f00 403 #define CORB_CD_MISC(x) ((x >> 8) & 0xf) 404 #define CORB_CD_PRESENCEOV 0x1 405 #define CORB_CD_COLOR(x) ((x >> 12) & 0xf) 406 #define CORB_CD_COLOR_UNKNOWN 0x0 407 #define CORB_CD_BLACK 0x1 408 #define CORB_CD_GRAY 0x2 409 #define CORB_CD_BLUE 0x3 410 #define CORB_CD_GREEN 0x4 411 #define CORB_CD_RED 0x5 412 #define CORB_CD_ORANGE 0x6 413 #define CORB_CD_YELLOW 0x7 414 #define CORB_CD_PURPLE 0x8 415 #define CORB_CD_PINK 0x9 416 #define CORB_CD_WHITE 0xe 417 #define CORB_CD_COLOR_OTHER 0xf 418 #define CORB_CD_CONNECTION_OFFSET 16 419 #define CORB_CD_CONNECTION_BITS 0xf 420 #define CORB_CD_CONNECTION_MASK (CORB_CD_CONNECTION_BITS << CORB_CD_CONNECTION_OFFSET) 421 #define CORB_CD_CONNECTION(x) ((x >> CORB_CD_CONNECTION_OFFSET) & CORB_CD_CONNECTION_BITS) 422 #define CORB_CD_CONN_UNKNOWN 0x0 423 #define CORB_CD_18 0x1 424 #define CORB_CD_14 0x2 425 #define CORB_CD_ATAPI 0x3 426 #define CORB_CD_RCA 0x4 427 #define CORB_CD_OPTICAL 0x5 428 #define CORB_CD_OTHER_DIG 0x6 429 #define CORB_CD_OTHER_ANALOG 0x7 430 #define CORB_CD_DIN 0x8 431 #define CORB_CD_XLF 0x9 432 #define CORB_CD_RJ11 0xa 433 #define CORB_CD_CONN_COMB 0xb 434 #define CORB_CD_CONN_OTHER 0xf 435 #define CORB_CD_DEVICE_OFFSET 20 436 #define CORB_CD_DEVICE_BITS 0xf 437 #define CORB_CD_DEVICE_MASK (CORB_CD_DEVICE_BITS << CORB_CD_DEVICE_OFFSET) 438 #define CORB_CD_DEVICE(x) ((x >> CORB_CD_DEVICE_OFFSET) & CORB_CD_DEVICE_BITS) 439 #define CORB_CD_LINEOUT 0x0 440 #define CORB_CD_SPEAKER 0x1 441 #define CORB_CD_HEADPHONE 0x2 442 #define CORB_CD_CD 0x3 443 #define CORB_CD_SPDIFOUT 0x4 444 #define CORB_CD_DIGITALOUT 0x5 445 #define CORB_CD_MODEMLINE 0x6 446 #define CORB_CD_MODEMHANDSET 0x7 447 #define CORB_CD_LINEIN 0x8 448 #define CORB_CD_AUX 0x9 449 #define CORB_CD_MICIN 0xa 450 #define CORB_CD_TELEPHONY 0xb 451 #define CORB_CD_SPDIFIN 0xc 452 #define CORB_CD_DIGITALIN 0xd 453 #define CORB_CD_BEEP 0xe 454 #define CORB_CD_DEVICE_OTHER 0xf 455 #define CORB_CD_LOCATION_MASK 0x3f000000 456 #define CORB_CD_LOC_GEO(x) ((x >> 24) & 0xf) 457 #define CORB_CD_LOC_GEO_NA 0x0 458 #define CORB_CD_REAR 0x1 459 #define CORB_CD_FRONT 0x2 460 #define CORB_CD_LEFT 0x3 461 #define CORB_CD_RIGHT 0x4 462 #define CORB_CD_TOP 0x5 463 #define CORB_CD_BOTTOM 0x6 464 #define CORB_CD_LOC_SPEC0 0x7 465 #define CORB_CD_LOC_SPEC1 0x8 466 #define CORB_CD_LOC_SPEC2 0x9 467 #define CORB_CD_LOC_CHASS(x) ((x >> 28) & 0x3) 468 #define CORB_CD_EXTERNAL 0x0 469 #define CORB_CD_INTERNAL 0x1 470 #define CORB_CD_SEPARATE 0x2 471 #define CORB_CD_LOC_OTHER 0x3 472 #define CORB_CD_PORT_OFFSET 30 473 #define CORB_CD_PORT_BITS 0x3 474 #define CORB_CD_PORT_MASK (CORB_CD_PORT_BITS << CORB_CD_PORT_OFFSET) 475 #define CORB_CD_PORT(x) ((x >> CORB_CD_PORT_OFFSET) & CORB_CD_PORT_BITS) 476 #define CORB_CD_JACK 0x0 477 #define CORB_CD_NONE 0x1 478 #define CORB_CD_FIXED 0x2 479 #define CORB_CD_BOTH 0x3 480 #define CORB_GET_STRIPE_CONTROL 0xf24 481 #define CORB_SET_STRIPE_CONTROL 0x720 /* XXX typo in the spec? */ 482 #define CORB_EXECUTE_FUNCTION_RESET 0x7ff 483 484 #define CORB_NID_ROOT 0 485 #define HDA_MAX_CHANNELS 16 486 #define HDA_MAX_SENSE_PINS 16 487 #define HDA_MAX_CODECS 15 488 489 #define AZ_MAX_VOL_SLAVES 16 490 #define AZ_TAG_SPKR 0x01 491 #define AZ_TAG_PLAYVOL 0x02 492 493 #define AZ_CLASS_INPUT 0 494 #define AZ_CLASS_OUTPUT 1 495 #define AZ_CLASS_RECORD 2 496 497 #define AZ_QRK_NONE 0x00000000 498 #define AZ_QRK_GPIO_MASK 0x00000fff 499 #define AZ_QRK_GPIO_UNMUTE_0 0x00000001 500 #define AZ_QRK_GPIO_UNMUTE_1 0x00000002 501 #define AZ_QRK_GPIO_UNMUTE_2 0x00000004 502 #define AZ_QRK_GPIO_UNMUTE_3 0x00000008 503 #define AZ_QRK_GPIO_UNMUTE_4 0x00000010 504 #define AZ_QRK_GPIO_UNMUTE_5 0x00000020 505 #define AZ_QRK_GPIO_UNMUTE_6 0x00000040 506 #define AZ_QRK_GPIO_UNMUTE_7 0x00000080 507 #define AZ_QRK_GPIO_POL_0 0x00000100 508 #define AZ_QRK_WID_MASK 0x00fff000 509 #define AZ_QRK_WID_CDIN_1C 0x00001000 510 #define AZ_QRK_WID_BEEP_1D 0x00002000 511 #define AZ_QRK_WID_OVREF50 0x00004000 512 #define AZ_QRK_WID_AD1981_OAMP 0x00008000 513 #define AZ_QRK_WID_TPDOCK1 0x00010000 514 #define AZ_QRK_WID_TPDOCK2 0x00020000 515 #define AZ_QRK_WID_TPDOCK3 0x00040000 516 #define AZ_QRK_WID_CLOSE_PCBEEP 0x00080000 517 #define AZ_QRK_ROUTE_SPKR2_DAC 0x01000000 518 #define AZ_QRK_DOLBY_ATMOS 0x02000000 519 520 /* memory-mapped types */ 521 typedef struct { 522 uint32_t low; 523 uint32_t high; 524 uint32_t length; 525 uint32_t flags; 526 #define BDLIST_ENTRY_IOC 0x00000001 527 } __packed bdlist_entry_t; 528 #define HDA_BDL_MAX 256 529 530 typedef struct { 531 uint32_t position; 532 uint32_t reserved; 533 } __packed dmaposition_t; 534 535 typedef uint32_t corb_entry_t; 536 typedef struct { 537 uint32_t resp; 538 uint32_t resp_ex; 539 #define RIRB_UNSOL_TAG(resp) ((resp) >> 26) 540 #define RIRB_RESP_UNSOL (1 << 4) 541 #define RIRB_RESP_CODEC(ex) ((ex) & 0xf) 542 } __packed rirb_entry_t; 543 544 545 /* #define AZALIA_DEBUG */ 546 #ifdef AZALIA_DEBUG 547 # define DPRINTF(x) do { printf x; } while (0/*CONSTCOND*/) 548 #else 549 # define DPRINTF(x) do {} while (0/*CONSTCOND*/) 550 #endif 551 #define PTR_UPPER32(x) ((uint64_t)(x) >> 32) 552 553 typedef int nid_t; 554 555 typedef struct { 556 nid_t nid; 557 int enable; 558 uint32_t widgetcap; 559 int type; /* = bit20-24 of widgetcap */ 560 nid_t parent; 561 int mixer_class; 562 int nconnections; 563 nid_t *connections; 564 int selected; 565 uint32_t inamp_cap; 566 uint32_t outamp_cap; 567 char name[MAX_AUDIO_DEV_LEN]; 568 union { 569 struct { /* for AUDIO_INPUT/OUTPUT */ 570 uint32_t encodings; 571 uint32_t bits_rates; 572 } audio; 573 struct { /* for PIN */ 574 uint32_t cap; 575 uint32_t config; 576 int sequence; 577 int association; 578 int color; 579 int device; 580 } pin; 581 struct { /* for VOLUME_KNOB */ 582 uint32_t cap; 583 } volume; 584 } d; 585 } widget_t; 586 #define WIDGET_CHANNELS(w) ((w)->widgetcap & COP_AWCAP_STEREO ? 2 : 1) 587 588 typedef struct { 589 mixer_devinfo_t devinfo; 590 nid_t nid; /* target NID; 0 is invalid. */ 591 int target; /* 0-15: inamp index, 0x100: outamp, ... */ 592 #define IS_MI_TARGET_INAMP(x) ((x) <= 15) 593 #define MI_TARGET_INAMP(x) (x) 594 #define MI_TARGET_OUTAMP 0x100 595 #define MI_TARGET_CONNLIST 0x101 596 #define MI_TARGET_PINDIR 0x102 /* for bidirectional pin */ 597 #define MI_TARGET_PINBOOST 0x103 /* for headphone pin */ 598 #define MI_TARGET_DAC 0x104 599 #define MI_TARGET_ADC 0x105 600 #define MI_TARGET_VOLUME 0x106 601 #define MI_TARGET_SPDIF 0x107 602 #define MI_TARGET_SPDIF_CC 0x108 603 #define MI_TARGET_EAPD 0x109 604 #define MI_TARGET_MUTESET 0x10a 605 #define MI_TARGET_PINSENSE 0x10b 606 #define MI_TARGET_SENSESET 0x10c 607 #define MI_TARGET_PLAYVOL 0x10d 608 #define MI_TARGET_RECVOL 0x10e 609 #define MI_TARGET_MIXERSET 0x10f 610 union { 611 int ord; 612 int mask; 613 mixer_level_t value; 614 } saved; 615 } mixer_item_t; 616 617 #define VALID_WIDGET_NID(nid, codec) (nid == (codec)->audiofunc || \ 618 (nid >= (codec)->wstart && \ 619 nid < (codec)->wend)) 620 621 typedef struct { 622 int nconv; 623 nid_t conv[HDA_MAX_CHANNELS]; 624 } convgroup_t; 625 typedef struct { 626 int cur; 627 int ngroups; 628 convgroup_t groups[2]; 629 } convgroupset_t; 630 631 typedef struct { 632 int master; 633 int vol_l; 634 int vol_r; 635 int mute; 636 int hw_step; 637 int hw_nsteps; 638 nid_t slaves[AZ_MAX_VOL_SLAVES]; 639 int nslaves; 640 int mask; 641 int cur; 642 } volgroup_t; 643 644 struct io_pin { 645 nid_t nid; /* NID of pin */ 646 nid_t conv; /* NID of default converter */ 647 int prio; /* assoc/seq/dir "priority" */ 648 }; 649 650 typedef struct codec_t { 651 struct azalia_t *az; 652 uint32_t vid; /* codec vendor/device ID */ 653 uint32_t subid; /* PCI subvendor/device ID */ 654 const char *name; 655 int address; 656 int nfunctions; 657 nid_t audiofunc; /* NID of an audio function node */ 658 nid_t wstart; /* start NID of audio widgets */ 659 nid_t wend; /* the last NID of audio widgets + 1 */ 660 widget_t *w; /* widgets in the audio function. 661 * w[0] to w[wstart-1] are unused. */ 662 #define FOR_EACH_WIDGET(this, i) for (i = (this)->wstart; i < (this)->wend; i++) 663 664 int codec_type; 665 #define AZ_CODEC_TYPE_ANALOG 0 666 #define AZ_CODEC_TYPE_DIGITAL 1 667 #define AZ_CODEC_TYPE_HDMI 2 668 669 int qrks; 670 671 convgroupset_t dacs; 672 convgroupset_t adcs; 673 int running; 674 675 int nmixers, maxmixers; 676 mixer_item_t *mixers; 677 678 struct audio_format *formats; 679 int nformats; 680 681 struct io_pin *ipins; 682 int nipins; 683 struct io_pin *ipins_d; 684 int nipins_d; 685 struct io_pin *opins; 686 int nopins; 687 struct io_pin *opins_d; 688 int nopins_d; 689 690 nid_t a_dacs[HDA_MAX_CHANNELS], a_dacs_d[HDA_MAX_CHANNELS]; 691 int na_dacs, na_dacs_d; 692 nid_t a_adcs[HDA_MAX_CHANNELS], a_adcs_d[HDA_MAX_CHANNELS]; 693 int na_adcs, na_adcs_d; 694 695 nid_t mic; /* fixed (internal) mic */ 696 nid_t mic_adc; 697 nid_t speaker; /* fixed (internal) speaker */ 698 nid_t speaker2; /* 2nd fixed (internal) speaker */ 699 nid_t spkr_dac; /* default DAC for speaker and speaker2 */ 700 nid_t input_mixer; 701 nid_t fhp; /* front headphone jack */ 702 nid_t fhp_dac; 703 int nout_jacks; /* number of default output jacks */ 704 705 int spkr_muted; 706 int spkr_muters; 707 int spkr_mute_method; 708 #define AZ_SPKR_MUTE_NONE 0 709 #define AZ_SPKR_MUTE_SPKR_MUTE 1 710 #define AZ_SPKR_MUTE_SPKR_DIR 2 711 #define AZ_SPKR_MUTE_DAC_MUTE 3 712 713 volgroup_t playvols; 714 volgroup_t recvols; 715 716 nid_t sense_pins[HDA_MAX_SENSE_PINS]; 717 int nsense_pins; 718 } codec_t; 719 720 int azalia_codec_init_vtbl(codec_t *); 721 int azalia_codec_construct_format(codec_t *, int, int); 722 int azalia_widget_enabled(const codec_t *, nid_t); 723 int azalia_codec_gpio_quirks(codec_t *); 724 int azalia_codec_widget_quirks(codec_t *, nid_t); 725 int azalia_codec_fnode(codec_t *, nid_t, int, int); 726 727 int azalia_init_dacgroup(codec_t *); 728 int azalia_mixer_init(codec_t *); 729 int azalia_mixer_delete(codec_t *); 730 int azalia_unsol_event(codec_t *, int); 731 int azalia_comresp(const codec_t *, nid_t, uint32_t, uint32_t, uint32_t *); 732 int azalia_mixer_get(const codec_t *, nid_t, int, mixer_ctrl_t *); 733 int azalia_mixer_set(codec_t *, nid_t, int, const mixer_ctrl_t *); 734 735 int azalia_codec_enable_unsol(codec_t *); 736 737 void azalia_codec_init_dolby_atmos(codec_t *); 738