1 /* $NetBSD: cpu.h,v 1.101 2015/01/23 07:27:05 nonaka Exp $ */
2
3 /*
4 * Copyright (C) 1999 Wolfgang Solfrank.
5 * Copyright (C) 1999 TooLs GmbH.
6 * Copyright (C) 1995-1997 Wolfgang Solfrank.
7 * Copyright (C) 1995-1997 TooLs GmbH.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by TooLs GmbH.
21 * 4. The name of TooLs GmbH may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35 #ifndef _POWERPC_CPU_H_
36 #define _POWERPC_CPU_H_
37
38 struct cache_info {
39 int dcache_size;
40 int dcache_line_size;
41 int icache_size;
42 int icache_line_size;
43 };
44
45 #if defined(_KERNEL) || defined(_KMEMUSER)
46 #if defined(_KERNEL_OPT)
47 #include "opt_lockdebug.h"
48 #include "opt_modular.h"
49 #include "opt_multiprocessor.h"
50 #include "opt_ppcarch.h"
51 #endif
52
53 #ifdef _KERNEL
54 #include <machine/intr.h>
55 #include <sys/device_if.h>
56 #include <sys/evcnt.h>
57 #endif
58
59 #include <sys/cpu_data.h>
60
61 struct cpu_info {
62 struct cpu_data ci_data; /* MI per-cpu data */
63 #ifdef _KERNEL
64 device_t ci_dev; /* device of corresponding cpu */
65 struct cpu_softc *ci_softc; /* private cpu info */
66 struct lwp *ci_curlwp; /* current owner of the processor */
67
68 struct pcb *ci_curpcb;
69 struct pmap *ci_curpm;
70 struct lwp *ci_softlwps[SOFTINT_COUNT];
71 int ci_cpuid; /* from SPR_PIR */
72
73 int ci_want_resched;
74 volatile uint64_t ci_lastintr;
75 volatile u_long ci_lasttb;
76 volatile int ci_tickspending;
77 volatile int ci_cpl;
78 volatile int ci_iactive;
79 volatile int ci_idepth;
80 union {
81 #if !defined(PPC_BOOKE) && !defined(_MODULE)
82 volatile imask_t un1_ipending;
83 #define ci_ipending ci_un1.un1_ipending
84 #endif
85 uint64_t un1_pad64;
86 } ci_un1;
87 volatile uint32_t ci_pending_ipis;
88 int ci_mtx_oldspl;
89 int ci_mtx_count;
90 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE)
91 char *ci_intstk;
92 #endif
93 #define CI_SAVETEMP (0*CPUSAVE_LEN)
94 #define CI_SAVEDDB (1*CPUSAVE_LEN)
95 #define CI_SAVEIPKDB (2*CPUSAVE_LEN)
96 #define CI_SAVEMMU (3*CPUSAVE_LEN)
97 #define CI_SAVEMAX (4*CPUSAVE_LEN)
98 #define CPUSAVE_LEN 8
99 #if !defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE)
100 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN)
101 #else
102 #define CPUSAVE_SIZE 128
103 #endif
104 #define CPUSAVE_R28 0 /* where r28 gets saved */
105 #define CPUSAVE_R29 1 /* where r29 gets saved */
106 #define CPUSAVE_R30 2 /* where r30 gets saved */
107 #define CPUSAVE_R31 3 /* where r31 gets saved */
108 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */
109 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */
110 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */
111 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */
112 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
113 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
114 register_t ci_savearea[CPUSAVE_SIZE];
115 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE)
116 uint32_t ci_pmap_asid_cur;
117 union pmap_segtab *ci_pmap_segtabs[2];
118 #define ci_pmap_kern_segtab ci_pmap_segtabs[0]
119 #define ci_pmap_user_segtab ci_pmap_segtabs[1]
120 struct pmap_tlb_info *ci_tlb_info;
121 #endif /* PPC_BOOKE || MODULAR || _MODULE */
122 struct cache_info ci_ci;
123 void *ci_sysmon_cookie;
124 void (*ci_idlespin)(void);
125 uint32_t ci_khz;
126 struct evcnt ci_ev_clock; /* clock intrs */
127 struct evcnt ci_ev_statclock; /* stat clock */
128 struct evcnt ci_ev_traps; /* calls to trap() */
129 struct evcnt ci_ev_kdsi; /* kernel DSI traps */
130 struct evcnt ci_ev_udsi; /* user DSI traps */
131 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
132 struct evcnt ci_ev_kisi; /* kernel ISI traps */
133 struct evcnt ci_ev_isi; /* user ISI traps */
134 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
135 struct evcnt ci_ev_pgm; /* user PGM traps */
136 struct evcnt ci_ev_debug; /* user debug traps */
137 struct evcnt ci_ev_fpu; /* FPU traps */
138 struct evcnt ci_ev_fpusw; /* FPU context switch */
139 struct evcnt ci_ev_ali; /* Alignment traps */
140 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
141 struct evcnt ci_ev_scalls; /* system call traps */
142 struct evcnt ci_ev_vec; /* Altivec traps */
143 struct evcnt ci_ev_vecsw; /* Altivec context switches */
144 struct evcnt ci_ev_umchk; /* user MCHK events */
145 struct evcnt ci_ev_ipi; /* IPIs received */
146 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */
147 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */
148 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */
149 #endif /* _KERNEL */
150 };
151 #endif /* _KERNEL || _KMEMUSER */
152
153 #ifdef _KERNEL
154
155 #if defined(MULTIPROCESSOR) && !defined(_MODULE)
156 struct cpu_hatch_data {
157 int hatch_running;
158 device_t hatch_self;
159 struct cpu_info *hatch_ci;
160 uint32_t hatch_tbu;
161 uint32_t hatch_tbl;
162 uint32_t hatch_hid0;
163 uint32_t hatch_pir;
164 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE)
165 uintptr_t hatch_asr;
166 uintptr_t hatch_sdr1;
167 uint32_t hatch_sr[16];
168 uintptr_t hatch_ibatu[8], hatch_ibatl[8];
169 uintptr_t hatch_dbatu[8], hatch_dbatl[8];
170 #endif
171 #if defined(PPC_BOOKE)
172 vaddr_t hatch_sp;
173 u_int hatch_tlbidx;
174 #endif
175 };
176
177 struct cpuset_info {
178 kcpuset_t *cpus_running;
179 kcpuset_t *cpus_hatched;
180 kcpuset_t *cpus_paused;
181 kcpuset_t *cpus_resumed;
182 kcpuset_t *cpus_halted;
183 };
184
185 extern struct cpuset_info cpuset_info;
186 #endif /* MULTIPROCESSOR && !_MODULE */
187
188 #if defined(MULTIPROCESSOR) || defined(_MODULE)
189 #define cpu_number() (curcpu()->ci_index + 0)
190
191 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
192 #define CPU_INFO_ITERATOR int
193 #define CPU_INFO_FOREACH(cii, ci) \
194 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++
195
196 #else
197 #define cpu_number() 0
198
199 #define CPU_IS_PRIMARY(ci) true
200 #define CPU_INFO_ITERATOR int
201 #define CPU_INFO_FOREACH(cii, ci) \
202 (void)cii, ci = curcpu(); ci != NULL; ci = NULL
203
204 #endif /* MULTIPROCESSOR || _MODULE */
205
206 extern struct cpu_info cpu_info[];
207
208 static __inline struct cpu_info * curcpu(void) __pure;
209 static __inline struct cpu_info *
curcpu(void)210 curcpu(void)
211 {
212 struct cpu_info *ci;
213
214 __asm volatile ("mfsprg0 %0" : "=r"(ci));
215 return ci;
216 }
217
218 #ifdef __clang__
219 #define curlwp (curcpu()->ci_curlwp)
220 #else
221 register struct lwp *powerpc_curlwp __asm("r13");
222 #define curlwp powerpc_curlwp
223 #endif
224 #define curpcb (curcpu()->ci_curpcb)
225 #define curpm (curcpu()->ci_curpm)
226
227 static __inline register_t
mfmsr(void)228 mfmsr(void)
229 {
230 register_t msr;
231
232 __asm volatile ("mfmsr %0" : "=r"(msr));
233 return msr;
234 }
235
236 static __inline void
mtmsr(register_t msr)237 mtmsr(register_t msr)
238 {
239 //KASSERT(msr & PSL_CE);
240 //KASSERT(msr & PSL_DE);
241 __asm volatile ("mtmsr %0" : : "r"(msr));
242 }
243
244 #if !defined(_MODULE)
245 static __inline uint32_t
mftbl(void)246 mftbl(void)
247 {
248 uint32_t tbl;
249
250 __asm volatile (
251 #ifdef PPC_IBM403
252 " mftblo %[tbl]" "\n"
253 #elif defined(PPC_BOOKE)
254 " mfspr %[tbl],268" "\n"
255 #else
256 " mftbl %[tbl]" "\n"
257 #endif
258 : [tbl] "=r" (tbl));
259
260 return tbl;
261 }
262
263 static __inline uint64_t
mftb(void)264 mftb(void)
265 {
266 uint64_t tb;
267
268 #ifdef _ARCH_PPC64
269 __asm volatile ("mftb %0" : "=r"(tb));
270 #else
271 int tmp;
272
273 __asm volatile (
274 #ifdef PPC_IBM403
275 "1: mftbhi %[tb]" "\n"
276 " mftblo %L[tb]" "\n"
277 " mftbhi %[tmp]" "\n"
278 #elif defined(PPC_BOOKE)
279 "1: mfspr %[tb],269" "\n"
280 " mfspr %L[tb],268" "\n"
281 " mfspr %[tmp],269" "\n"
282 #else
283 "1: mftbu %[tb]" "\n"
284 " mftb %L[tb]" "\n"
285 " mftbu %[tmp]" "\n"
286 #endif
287 " cmplw %[tb],%[tmp]" "\n"
288 " bne- 1b" "\n"
289 : [tb] "=r" (tb), [tmp] "=r"(tmp)
290 :: "cr0");
291 #endif
292
293 return tb;
294 }
295
296 static __inline uint32_t
mfrtcl(void)297 mfrtcl(void)
298 {
299 uint32_t rtcl;
300
301 __asm volatile ("mfrtcl %0" : "=r"(rtcl));
302 return rtcl;
303 }
304
305 static __inline void
mfrtc(uint32_t * rtcp)306 mfrtc(uint32_t *rtcp)
307 {
308 uint32_t tmp;
309
310 __asm volatile (
311 "1: mfrtcu %[rtcu]" "\n"
312 " mfrtcl %[rtcl]" "\n"
313 " mfrtcu %[tmp]" "\n"
314 " cmplw %[rtcu],%[tmp]" "\n"
315 " bne- 1b"
316 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp)
317 :: "cr0");
318 }
319
320 static __inline uint64_t
rtc_nanosecs(void)321 rtc_nanosecs(void)
322 {
323 /*
324 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick.
325 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds.
326 * RTCU is seconds, 32 bits.
327 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns)
328 */
329 uint64_t cycles;
330 uint32_t tmp[2];
331
332 mfrtc(tmp);
333
334 cycles = tmp[0] * 1000000000;
335 cycles += (tmp[1] >> 7);
336
337 return cycles;
338 }
339 #endif /* !_MODULE */
340
341 static __inline uint32_t
mfpvr(void)342 mfpvr(void)
343 {
344 uint32_t pvr;
345
346 __asm volatile ("mfpvr %0" : "=r"(pvr));
347 return (pvr);
348 }
349
350 #ifdef _MODULE
351 extern const char __CPU_MAXNUM;
352 /*
353 * Make with 0xffff to force a R_PPC_ADDR16_LO without the
354 * corresponding R_PPC_ADDR16_HI relocation.
355 */
356 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff)
357 #endif /* _MODULE */
358
359 #if !defined(_MODULE)
360 extern char *booted_kernel;
361 extern int powersave;
362 extern int cpu_timebase;
363 extern int cpu_printfataltraps;
364
365 struct cpu_info *
366 cpu_attach_common(device_t, int);
367 void cpu_setup(device_t, struct cpu_info *);
368 void cpu_identify(char *, size_t);
369 void cpu_probe_cache(void);
370
371 void dcache_wb_page(vaddr_t);
372 void dcache_wbinv_page(vaddr_t);
373 void dcache_inv_page(vaddr_t);
374 void dcache_zero_page(vaddr_t);
375 void icache_inv_page(vaddr_t);
376 void dcache_wb(vaddr_t, vsize_t);
377 void dcache_wbinv(vaddr_t, vsize_t);
378 void dcache_inv(vaddr_t, vsize_t);
379 void icache_inv(vaddr_t, vsize_t);
380
381 void * mapiodev(paddr_t, psize_t, bool);
382 void unmapiodev(vaddr_t, vsize_t);
383
384 #ifdef MULTIPROCESSOR
385 int md_setup_trampoline(volatile struct cpu_hatch_data *,
386 struct cpu_info *);
387 void md_presync_timebase(volatile struct cpu_hatch_data *);
388 void md_start_timebase(volatile struct cpu_hatch_data *);
389 void md_sync_timebase(volatile struct cpu_hatch_data *);
390 void md_setup_interrupts(void);
391 int cpu_spinup(device_t, struct cpu_info *);
392 register_t
393 cpu_hatch(void);
394 void cpu_spinup_trampoline(void);
395 void cpu_boot_secondary_processors(void);
396 void cpu_halt(void);
397 void cpu_halt_others(void);
398 void cpu_pause(struct trapframe *);
399 void cpu_pause_others(void);
400 void cpu_resume(cpuid_t);
401 void cpu_resume_others(void);
402 int cpu_is_paused(int);
403 void cpu_debug_dump(void);
404 #endif /* MULTIPROCESSOR */
405 #endif /* !_MODULE */
406
407 #define cpu_proc_fork(p1, p2)
408
409 #define DELAY(n) delay(n)
410 void delay(unsigned int);
411
412 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf)
413 #define CLKF_PC(cf) cpu_clkf_pc(cf)
414 #define CLKF_INTR(cf) cpu_clkf_intr(cf)
415
416 bool cpu_clkf_usermode(const struct clockframe *);
417 vaddr_t cpu_clkf_pc(const struct clockframe *);
418 bool cpu_clkf_intr(const struct clockframe *);
419
420 #define LWP_PC(l) cpu_lwp_pc(l)
421
422 vaddr_t cpu_lwp_pc(struct lwp *);
423
424 void cpu_ast(struct lwp *, struct cpu_info *);
425 void * cpu_uarea_alloc(bool);
426 bool cpu_uarea_free(void *);
427 void cpu_need_resched(struct cpu_info *, int);
428 void cpu_signotify(struct lwp *);
429 void cpu_need_proftick(struct lwp *);
430 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0)
431
432 void cpu_fixup_stubs(void);
433
434 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE)
435 int cpu_get_dfs(void);
436 void cpu_set_dfs(int);
437
438 void oea_init(void (*)(void));
439 void oea_startup(const char *);
440 void oea_dumpsys(void);
441 void oea_install_extint(void (*)(void));
442 paddr_t kvtop(void *);
443
444 extern paddr_t msgbuf_paddr;
445 extern int cpu_altivec;
446 #endif
447
448 #endif /* _KERNEL */
449
450 /* XXX The below breaks unified pmap on ppc32 */
451
452 #if !defined(CACHELINESIZE) && !defined(_MODULE) \
453 && (defined(_KERNEL) || defined(_STANDALONE))
454 #if defined(PPC_IBM403)
455 #define CACHELINESIZE 16
456 #define MAXCACHELINESIZE 16
457 #elif defined (PPC_OEA64_BRIDGE)
458 #define CACHELINESIZE 128
459 #define MAXCACHELINESIZE 128
460 #else
461 #define CACHELINESIZE 32
462 #define MAXCACHELINESIZE 32
463 #endif /* PPC_OEA64_BRIDGE */
464 #endif
465
466 void __syncicache(void *, size_t);
467
468 /*
469 * CTL_MACHDEP definitions.
470 */
471 #define CPU_CACHELINE 1
472 #define CPU_TIMEBASE 2
473 #define CPU_CPUTEMP 3
474 #define CPU_PRINTFATALTRAPS 4
475 #define CPU_CACHEINFO 5
476 #define CPU_ALTIVEC 6
477 #define CPU_MODEL 7
478 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */
479 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */
480 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */
481 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */
482 #define CPU_MAXID 12 /* number of valid machdep ids */
483
484 #endif /* _POWERPC_CPU_H_ */
485