1 /* $NetBSD: nid.h,v 1.4 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef NI_H 27 #define NI_H 28 29 #define CAYMAN_MAX_SH_GPRS 256 30 #define CAYMAN_MAX_TEMP_GPRS 16 31 #define CAYMAN_MAX_SH_THREADS 256 32 #define CAYMAN_MAX_SH_STACK_ENTRIES 4096 33 #define CAYMAN_MAX_FRC_EOV_CNT 16384 34 #define CAYMAN_MAX_BACKENDS 8 35 #define CAYMAN_MAX_BACKENDS_MASK 0xFF 36 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 37 #define CAYMAN_MAX_SIMDS 16 38 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF 39 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 40 #define CAYMAN_MAX_PIPES 8 41 #define CAYMAN_MAX_PIPES_MASK 0xFF 42 #define CAYMAN_MAX_LDS_NUM 0xFFFF 43 #define CAYMAN_MAX_TCC 16 44 #define CAYMAN_MAX_TCC_MASK 0xFF 45 46 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 47 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 48 49 #define DMIF_ADDR_CONFIG 0xBD4 50 51 /* fusion vce clocks */ 52 #define CG_ECLK_CNTL 0x620 53 # define ECLK_DIVIDER_MASK 0x7f 54 # define ECLK_DIR_CNTL_EN (1 << 8) 55 #define CG_ECLK_STATUS 0x624 56 # define ECLK_STATUS (1 << 0) 57 58 /* DCE6 only */ 59 #define DMIF_ADDR_CALC 0xC00 60 61 #define SRBM_GFX_CNTL 0x0E44 62 #define RINGID(x) (((x) & 0x3) << 0) 63 #define VMID(x) (((x) & 0x7) << 0) 64 #define SRBM_STATUS 0x0E50 65 #define RLC_RQ_PENDING (1 << 3) 66 #define GRBM_RQ_PENDING (1 << 5) 67 #define VMC_BUSY (1 << 8) 68 #define MCB_BUSY (1 << 9) 69 #define MCB_NON_DISPLAY_BUSY (1 << 10) 70 #define MCC_BUSY (1 << 11) 71 #define MCD_BUSY (1 << 12) 72 #define SEM_BUSY (1 << 14) 73 #define RLC_BUSY (1 << 15) 74 #define IH_BUSY (1 << 17) 75 76 #define SRBM_SOFT_RESET 0x0E60 77 #define SOFT_RESET_BIF (1 << 1) 78 #define SOFT_RESET_CG (1 << 2) 79 #define SOFT_RESET_DC (1 << 5) 80 #define SOFT_RESET_DMA1 (1 << 6) 81 #define SOFT_RESET_GRBM (1 << 8) 82 #define SOFT_RESET_HDP (1 << 9) 83 #define SOFT_RESET_IH (1 << 10) 84 #define SOFT_RESET_MC (1 << 11) 85 #define SOFT_RESET_RLC (1 << 13) 86 #define SOFT_RESET_ROM (1 << 14) 87 #define SOFT_RESET_SEM (1 << 15) 88 #define SOFT_RESET_VMC (1 << 17) 89 #define SOFT_RESET_DMA (1 << 20) 90 #define SOFT_RESET_TST (1 << 21) 91 #define SOFT_RESET_REGBB (1 << 22) 92 #define SOFT_RESET_ORB (1 << 23) 93 94 #define SRBM_READ_ERROR 0xE98 95 #define SRBM_INT_CNTL 0xEA0 96 #define SRBM_INT_ACK 0xEA8 97 98 #define SRBM_STATUS2 0x0EC4 99 #define DMA_BUSY (1 << 5) 100 #define DMA1_BUSY (1 << 6) 101 102 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 103 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 104 #define RESPONSE_TYPE_MASK 0x000000F0 105 #define RESPONSE_TYPE_SHIFT 4 106 #define VM_L2_CNTL 0x1400 107 #define ENABLE_L2_CACHE (1 << 0) 108 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 109 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 110 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 111 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 112 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 113 /* CONTEXT1_IDENTITY_ACCESS_MODE 114 * 0 physical = logical 115 * 1 logical via context1 page table 116 * 2 inside identity aperture use translation, outside physical = logical 117 * 3 inside identity aperture physical = logical, outside use translation 118 */ 119 #define VM_L2_CNTL2 0x1404 120 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 121 #define INVALIDATE_L2_CACHE (1 << 1) 122 #define VM_L2_CNTL3 0x1408 123 #define BANK_SELECT(x) ((x) << 0) 124 #define CACHE_UPDATE_MODE(x) ((x) << 6) 125 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 126 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 127 #define VM_L2_STATUS 0x140C 128 #define L2_BUSY (1 << 0) 129 #define VM_CONTEXT0_CNTL 0x1410 130 #define ENABLE_CONTEXT (1 << 0) 131 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 132 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 133 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 134 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 135 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 136 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 137 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 138 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 139 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 140 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 141 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 142 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 143 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 144 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 145 #define VM_CONTEXT1_CNTL 0x1414 146 #define VM_CONTEXT0_CNTL2 0x1430 147 #define VM_CONTEXT1_CNTL2 0x1434 148 #define VM_INVALIDATE_REQUEST 0x1478 149 #define VM_INVALIDATE_RESPONSE 0x147c 150 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 151 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 152 #define PROTECTIONS_MASK (0xf << 0) 153 #define PROTECTIONS_SHIFT 0 154 /* bit 0: range 155 * bit 2: pde0 156 * bit 3: valid 157 * bit 4: read 158 * bit 5: write 159 */ 160 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 161 #define MEMORY_CLIENT_ID_SHIFT 12 162 #define MEMORY_CLIENT_RW_MASK (1 << 24) 163 #define MEMORY_CLIENT_RW_SHIFT 24 164 #define FAULT_VMID_MASK (0x7 << 25) 165 #define FAULT_VMID_SHIFT 25 166 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 167 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 168 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 169 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 170 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 171 172 #define MC_SHARED_CHMAP 0x2004 173 #define NOOFCHAN_SHIFT 12 174 #define NOOFCHAN_MASK 0x00003000 175 #define MC_SHARED_CHREMAP 0x2008 176 177 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 178 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 179 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 180 #define MC_VM_MX_L1_TLB_CNTL 0x2064 181 #define ENABLE_L1_TLB (1 << 0) 182 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 183 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 184 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 185 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 186 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 187 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 188 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 189 #define FUS_MC_VM_FB_OFFSET 0x2068 190 191 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 192 #define MC_ARB_RAMCFG 0x2760 193 #define NOOFBANK_SHIFT 0 194 #define NOOFBANK_MASK 0x00000003 195 #define NOOFRANK_SHIFT 2 196 #define NOOFRANK_MASK 0x00000004 197 #define NOOFROWS_SHIFT 3 198 #define NOOFROWS_MASK 0x00000038 199 #define NOOFCOLS_SHIFT 6 200 #define NOOFCOLS_MASK 0x000000C0 201 #define CHANSIZE_SHIFT 8 202 #define CHANSIZE_MASK 0x00000100 203 #define BURSTLENGTH_SHIFT 9 204 #define BURSTLENGTH_MASK 0x00000200 205 #define CHANSIZE_OVERRIDE (1 << 11) 206 #define MC_SEQ_SUP_CNTL 0x28c8 207 #define RUN_MASK (1 << 0) 208 #define MC_SEQ_SUP_PGM 0x28cc 209 #define MC_IO_PAD_CNTL_D0 0x29d0 210 #define MEM_FALL_OUT_CMD (1 << 8) 211 #define MC_SEQ_MISC0 0x2a00 212 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 213 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 214 #define MC_SEQ_MISC0_GDDR5_VALUE 5 215 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 216 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 217 218 #define HDP_HOST_PATH_CNTL 0x2C00 219 #define HDP_NONSURFACE_BASE 0x2C04 220 #define HDP_NONSURFACE_INFO 0x2C08 221 #define HDP_NONSURFACE_SIZE 0x2C0C 222 #define HDP_ADDR_CONFIG 0x2F48 223 #define HDP_MISC_CNTL 0x2F4C 224 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 225 226 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 227 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 228 #define CGTS_SYS_TCC_DISABLE 0x3F90 229 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 230 231 #define RLC_GFX_INDEX 0x3FC4 232 233 #define CONFIG_MEMSIZE 0x5428 234 235 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 236 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 237 238 #define GRBM_CNTL 0x8000 239 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 240 #define GRBM_STATUS 0x8010 241 #define CMDFIFO_AVAIL_MASK 0x0000000F 242 #define RING2_RQ_PENDING (1 << 4) 243 #define SRBM_RQ_PENDING (1 << 5) 244 #define RING1_RQ_PENDING (1 << 6) 245 #define CF_RQ_PENDING (1 << 7) 246 #define PF_RQ_PENDING (1 << 8) 247 #define GDS_DMA_RQ_PENDING (1 << 9) 248 #define GRBM_EE_BUSY (1 << 10) 249 #define SX_CLEAN (1 << 11) 250 #define DB_CLEAN (1 << 12) 251 #define CB_CLEAN (1 << 13) 252 #define TA_BUSY (1 << 14) 253 #define GDS_BUSY (1 << 15) 254 #define VGT_BUSY_NO_DMA (1 << 16) 255 #define VGT_BUSY (1 << 17) 256 #define IA_BUSY_NO_DMA (1 << 18) 257 #define IA_BUSY (1 << 19) 258 #define SX_BUSY (1 << 20) 259 #define SH_BUSY (1 << 21) 260 #define SPI_BUSY (1 << 22) 261 #define SC_BUSY (1 << 24) 262 #define PA_BUSY (1 << 25) 263 #define DB_BUSY (1 << 26) 264 #define CP_COHERENCY_BUSY (1 << 28) 265 #define CP_BUSY (1 << 29) 266 #define CB_BUSY (1 << 30) 267 #define GUI_ACTIVE (1 << 31) 268 #define GRBM_STATUS_SE0 0x8014 269 #define GRBM_STATUS_SE1 0x8018 270 #define SE_SX_CLEAN (1 << 0) 271 #define SE_DB_CLEAN (1 << 1) 272 #define SE_CB_CLEAN (1 << 2) 273 #define SE_VGT_BUSY (1 << 23) 274 #define SE_PA_BUSY (1 << 24) 275 #define SE_TA_BUSY (1 << 25) 276 #define SE_SX_BUSY (1 << 26) 277 #define SE_SPI_BUSY (1 << 27) 278 #define SE_SH_BUSY (1 << 28) 279 #define SE_SC_BUSY (1 << 29) 280 #define SE_DB_BUSY (1 << 30) 281 #define SE_CB_BUSY (1 << 31) 282 #define GRBM_SOFT_RESET 0x8020 283 #define SOFT_RESET_CP (1 << 0) 284 #define SOFT_RESET_CB (1 << 1) 285 #define SOFT_RESET_DB (1 << 3) 286 #define SOFT_RESET_GDS (1 << 4) 287 #define SOFT_RESET_PA (1 << 5) 288 #define SOFT_RESET_SC (1 << 6) 289 #define SOFT_RESET_SPI (1 << 8) 290 #define SOFT_RESET_SH (1 << 9) 291 #define SOFT_RESET_SX (1 << 10) 292 #define SOFT_RESET_TC (1 << 11) 293 #define SOFT_RESET_TA (1 << 12) 294 #define SOFT_RESET_VGT (1 << 14) 295 #define SOFT_RESET_IA (1 << 15) 296 297 #define GRBM_GFX_INDEX 0x802C 298 #define INSTANCE_INDEX(x) ((x) << 0) 299 #define SE_INDEX(x) ((x) << 16) 300 #define INSTANCE_BROADCAST_WRITES (1 << 30) 301 #define SE_BROADCAST_WRITES (1 << 31) 302 303 #define SCRATCH_REG0 0x8500 304 #define SCRATCH_REG1 0x8504 305 #define SCRATCH_REG2 0x8508 306 #define SCRATCH_REG3 0x850C 307 #define SCRATCH_REG4 0x8510 308 #define SCRATCH_REG5 0x8514 309 #define SCRATCH_REG6 0x8518 310 #define SCRATCH_REG7 0x851C 311 #define SCRATCH_UMSK 0x8540 312 #define SCRATCH_ADDR 0x8544 313 #define CP_SEM_WAIT_TIMER 0x85BC 314 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 315 #define CP_COHER_CNTL2 0x85E8 316 #define CP_STALLED_STAT1 0x8674 317 #define CP_STALLED_STAT2 0x8678 318 #define CP_BUSY_STAT 0x867C 319 #define CP_STAT 0x8680 320 #define CP_ME_CNTL 0x86D8 321 #define CP_ME_HALT (1 << 28) 322 #define CP_PFP_HALT (1 << 26) 323 #define CP_RB2_RPTR 0x86f8 324 #define CP_RB1_RPTR 0x86fc 325 #define CP_RB0_RPTR 0x8700 326 #define CP_RB_WPTR_DELAY 0x8704 327 #define CP_MEQ_THRESHOLDS 0x8764 328 #define MEQ1_START(x) ((x) << 0) 329 #define MEQ2_START(x) ((x) << 8) 330 #define CP_PERFMON_CNTL 0x87FC 331 332 #define VGT_CACHE_INVALIDATION 0x88C4 333 #define CACHE_INVALIDATION(x) ((x) << 0) 334 #define VC_ONLY 0 335 #define TC_ONLY 1 336 #define VC_AND_TC 2 337 #define AUTO_INVLD_EN(x) ((x) << 6) 338 #define NO_AUTO 0 339 #define ES_AUTO 1 340 #define GS_AUTO 2 341 #define ES_AND_GS_AUTO 3 342 #define VGT_GS_VERTEX_REUSE 0x88D4 343 344 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 345 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 346 #define INACTIVE_QD_PIPES(x) ((x) << 8) 347 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 348 #define INACTIVE_QD_PIPES_SHIFT 8 349 #define INACTIVE_SIMDS(x) ((x) << 16) 350 #define INACTIVE_SIMDS_MASK 0xFFFF0000 351 #define INACTIVE_SIMDS_SHIFT 16 352 353 #define VGT_PRIMITIVE_TYPE 0x8958 354 #define VGT_NUM_INSTANCES 0x8974 355 #define VGT_TF_RING_SIZE 0x8988 356 #define VGT_OFFCHIP_LDS_BASE 0x89b4 357 358 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 359 #define PA_CL_ENHANCE 0x8A14 360 #define CLIP_VTX_REORDER_ENA (1 << 0) 361 #define NUM_CLIP_SEQ(x) ((x) << 1) 362 #define PA_SC_FIFO_SIZE 0x8BCC 363 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 364 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 365 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 366 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 367 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 368 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 369 370 #define SQ_CONFIG 0x8C00 371 #define VC_ENABLE (1 << 0) 372 #define EXPORT_SRC_C (1 << 1) 373 #define GFX_PRIO(x) ((x) << 2) 374 #define CS1_PRIO(x) ((x) << 4) 375 #define CS2_PRIO(x) ((x) << 6) 376 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 377 #define NUM_PS_GPRS(x) ((x) << 0) 378 #define NUM_VS_GPRS(x) ((x) << 16) 379 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 380 #define SQ_ESGS_RING_SIZE 0x8c44 381 #define SQ_GSVS_RING_SIZE 0x8c4c 382 #define SQ_ESTMP_RING_BASE 0x8c50 383 #define SQ_ESTMP_RING_SIZE 0x8c54 384 #define SQ_GSTMP_RING_BASE 0x8c58 385 #define SQ_GSTMP_RING_SIZE 0x8c5c 386 #define SQ_VSTMP_RING_BASE 0x8c60 387 #define SQ_VSTMP_RING_SIZE 0x8c64 388 #define SQ_PSTMP_RING_BASE 0x8c68 389 #define SQ_PSTMP_RING_SIZE 0x8c6c 390 #define SQ_MS_FIFO_SIZES 0x8CF0 391 #define CACHE_FIFO_SIZE(x) ((x) << 0) 392 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 393 #define DONE_FIFO_HIWATER(x) ((x) << 16) 394 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 395 #define SQ_LSTMP_RING_BASE 0x8e10 396 #define SQ_LSTMP_RING_SIZE 0x8e14 397 #define SQ_HSTMP_RING_BASE 0x8e18 398 #define SQ_HSTMP_RING_SIZE 0x8e1c 399 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 400 #define DYN_GPR_ENABLE (1 << 8) 401 #define SQ_CONST_MEM_BASE 0x8df8 402 403 #define SX_EXPORT_BUFFER_SIZES 0x900C 404 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 405 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 406 #define SMX_BUFFER_SIZE(x) ((x) << 16) 407 #define SX_DEBUG_1 0x9058 408 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 409 410 #define SPI_CONFIG_CNTL 0x9100 411 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 412 #define SPI_CONFIG_CNTL_1 0x913C 413 #define VTX_DONE_DELAY(x) ((x) << 0) 414 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 415 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 416 417 #define CGTS_TCC_DISABLE 0x9148 418 #define CGTS_USER_TCC_DISABLE 0x914C 419 #define TCC_DISABLE_MASK 0xFFFF0000 420 #define TCC_DISABLE_SHIFT 16 421 #define CGTS_SM_CTRL_REG 0x9150 422 #define OVERRIDE (1 << 21) 423 424 #define TA_CNTL_AUX 0x9508 425 #define DISABLE_CUBE_WRAP (1 << 0) 426 #define DISABLE_CUBE_ANISO (1 << 1) 427 428 #define TCP_CHAN_STEER_LO 0x960c 429 #define TCP_CHAN_STEER_HI 0x9610 430 431 #define CC_RB_BACKEND_DISABLE 0x98F4 432 #define BACKEND_DISABLE(x) ((x) << 16) 433 #define GB_ADDR_CONFIG 0x98F8 434 #define NUM_PIPES(x) ((x) << 0) 435 #define NUM_PIPES_MASK 0x00000007 436 #define NUM_PIPES_SHIFT 0 437 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 438 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 439 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 440 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 441 #define NUM_SHADER_ENGINES(x) ((x) << 12) 442 #define NUM_SHADER_ENGINES_MASK 0x00003000 443 #define NUM_SHADER_ENGINES_SHIFT 12 444 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 445 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 446 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 447 #define NUM_GPUS(x) ((x) << 20) 448 #define NUM_GPUS_MASK 0x00700000 449 #define NUM_GPUS_SHIFT 20 450 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 451 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 452 #define MULTI_GPU_TILE_SIZE_SHIFT 24 453 #define ROW_SIZE(x) ((x) << 28) 454 #define ROW_SIZE_MASK 0x30000000 455 #define ROW_SIZE_SHIFT 28 456 #define NUM_LOWER_PIPES(x) ((x) << 30) 457 #define NUM_LOWER_PIPES_MASK 0x40000000 458 #define NUM_LOWER_PIPES_SHIFT 30 459 #define GB_BACKEND_MAP 0x98FC 460 461 #define CB_PERF_CTR0_SEL_0 0x9A20 462 #define CB_PERF_CTR0_SEL_1 0x9A24 463 #define CB_PERF_CTR1_SEL_0 0x9A28 464 #define CB_PERF_CTR1_SEL_1 0x9A2C 465 #define CB_PERF_CTR2_SEL_0 0x9A30 466 #define CB_PERF_CTR2_SEL_1 0x9A34 467 #define CB_PERF_CTR3_SEL_0 0x9A38 468 #define CB_PERF_CTR3_SEL_1 0x9A3C 469 470 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 471 #define BACKEND_DISABLE_MASK 0x00FF0000 472 #define BACKEND_DISABLE_SHIFT 16 473 474 #define SMX_DC_CTL0 0xA020 475 #define USE_HASH_FUNCTION (1 << 0) 476 #define NUMBER_OF_SETS(x) ((x) << 1) 477 #define FLUSH_ALL_ON_EVENT (1 << 10) 478 #define STALL_ON_EVENT (1 << 11) 479 #define SMX_EVENT_CTL 0xA02C 480 #define ES_FLUSH_CTL(x) ((x) << 0) 481 #define GS_FLUSH_CTL(x) ((x) << 3) 482 #define ACK_FLUSH_CTL(x) ((x) << 6) 483 #define SYNC_FLUSH_CTL (1 << 8) 484 485 #define CP_RB0_BASE 0xC100 486 #define CP_RB0_CNTL 0xC104 487 #define RB_BUFSZ(x) ((x) << 0) 488 #define RB_BLKSZ(x) ((x) << 8) 489 #define RB_NO_UPDATE (1 << 27) 490 #define RB_RPTR_WR_ENA (1 << 31) 491 #define BUF_SWAP_32BIT (2 << 16) 492 #define CP_RB0_RPTR_ADDR 0xC10C 493 #define CP_RB0_RPTR_ADDR_HI 0xC110 494 #define CP_RB0_WPTR 0xC114 495 496 #define CP_INT_CNTL 0xC124 497 # define CNTX_BUSY_INT_ENABLE (1 << 19) 498 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 499 # define TIME_STAMP_INT_ENABLE (1 << 26) 500 501 #define CP_RB1_BASE 0xC180 502 #define CP_RB1_CNTL 0xC184 503 #define CP_RB1_RPTR_ADDR 0xC188 504 #define CP_RB1_RPTR_ADDR_HI 0xC18C 505 #define CP_RB1_WPTR 0xC190 506 #define CP_RB2_BASE 0xC194 507 #define CP_RB2_CNTL 0xC198 508 #define CP_RB2_RPTR_ADDR 0xC19C 509 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 510 #define CP_RB2_WPTR 0xC1A4 511 #define CP_PFP_UCODE_ADDR 0xC150 512 #define CP_PFP_UCODE_DATA 0xC154 513 #define CP_ME_RAM_RADDR 0xC158 514 #define CP_ME_RAM_WADDR 0xC15C 515 #define CP_ME_RAM_DATA 0xC160 516 #define CP_DEBUG 0xC1FC 517 518 #define VGT_EVENT_INITIATOR 0x28a90 519 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 520 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 521 522 /* TN SMU registers */ 523 #define TN_CURRENT_GNB_TEMP 0x1F390 524 525 /* pm registers */ 526 #define SMC_MSG 0x20c 527 #define HOST_SMC_MSG(x) ((x) << 0) 528 #define HOST_SMC_MSG_MASK (0xff << 0) 529 #define HOST_SMC_MSG_SHIFT 0 530 #define HOST_SMC_RESP(x) ((x) << 8) 531 #define HOST_SMC_RESP_MASK (0xff << 8) 532 #define HOST_SMC_RESP_SHIFT 8 533 #define SMC_HOST_MSG(x) ((x) << 16) 534 #define SMC_HOST_MSG_MASK (0xff << 16) 535 #define SMC_HOST_MSG_SHIFT 16 536 #define SMC_HOST_RESP(x) ((x) << 24) 537 #define SMC_HOST_RESP_MASK (0xff << 24) 538 #define SMC_HOST_RESP_SHIFT 24 539 540 #define CG_SPLL_FUNC_CNTL 0x600 541 #define SPLL_RESET (1 << 0) 542 #define SPLL_SLEEP (1 << 1) 543 #define SPLL_BYPASS_EN (1 << 3) 544 #define SPLL_REF_DIV(x) ((x) << 4) 545 #define SPLL_REF_DIV_MASK (0x3f << 4) 546 #define SPLL_PDIV_A(x) ((x) << 20) 547 #define SPLL_PDIV_A_MASK (0x7f << 20) 548 #define SPLL_PDIV_A_SHIFT 20 549 #define CG_SPLL_FUNC_CNTL_2 0x604 550 #define SCLK_MUX_SEL(x) ((x) << 0) 551 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 552 #define CG_SPLL_FUNC_CNTL_3 0x608 553 #define SPLL_FB_DIV(x) ((x) << 0) 554 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 555 #define SPLL_FB_DIV_SHIFT 0 556 #define SPLL_DITHEN (1 << 28) 557 558 #define MPLL_CNTL_MODE 0x61c 559 # define SS_SSEN (1 << 24) 560 # define SS_DSMODE_EN (1 << 25) 561 562 #define MPLL_AD_FUNC_CNTL 0x624 563 #define CLKF(x) ((x) << 0) 564 #define CLKF_MASK (0x7f << 0) 565 #define CLKR(x) ((x) << 7) 566 #define CLKR_MASK (0x1f << 7) 567 #define CLKFRAC(x) ((x) << 12) 568 #define CLKFRAC_MASK (0x1f << 12) 569 #define YCLK_POST_DIV(x) ((x) << 17) 570 #define YCLK_POST_DIV_MASK (3 << 17) 571 #define IBIAS(x) ((x) << 20) 572 #define IBIAS_MASK (0x3ff << 20) 573 #define RESET (1 << 30) 574 #define PDNB (1 << 31) 575 #define MPLL_AD_FUNC_CNTL_2 0x628 576 #define BYPASS (1 << 19) 577 #define BIAS_GEN_PDNB (1 << 24) 578 #define RESET_EN (1 << 25) 579 #define VCO_MODE (1 << 29) 580 #define MPLL_DQ_FUNC_CNTL 0x62c 581 #define MPLL_DQ_FUNC_CNTL_2 0x630 582 583 #define GENERAL_PWRMGT 0x63c 584 # define GLOBAL_PWRMGT_EN (1 << 0) 585 # define STATIC_PM_EN (1 << 1) 586 # define THERMAL_PROTECTION_DIS (1 << 2) 587 # define THERMAL_PROTECTION_TYPE (1 << 3) 588 # define ENABLE_GEN2PCIE (1 << 4) 589 # define ENABLE_GEN2XSP (1 << 5) 590 # define SW_SMIO_INDEX(x) ((x) << 6) 591 # define SW_SMIO_INDEX_MASK (3 << 6) 592 # define SW_SMIO_INDEX_SHIFT 6 593 # define LOW_VOLT_D2_ACPI (1 << 8) 594 # define LOW_VOLT_D3_ACPI (1 << 9) 595 # define VOLT_PWRMGT_EN (1 << 10) 596 # define BACKBIAS_PAD_EN (1 << 18) 597 # define BACKBIAS_VALUE (1 << 19) 598 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 599 # define AC_DC_SW (1 << 24) 600 601 #define SCLK_PWRMGT_CNTL 0x644 602 # define SCLK_PWRMGT_OFF (1 << 0) 603 # define SCLK_LOW_D1 (1 << 1) 604 # define FIR_RESET (1 << 4) 605 # define FIR_FORCE_TREND_SEL (1 << 5) 606 # define FIR_TREND_MODE (1 << 6) 607 # define DYN_GFX_CLK_OFF_EN (1 << 7) 608 # define GFX_CLK_FORCE_ON (1 << 8) 609 # define GFX_CLK_REQUEST_OFF (1 << 9) 610 # define GFX_CLK_FORCE_OFF (1 << 10) 611 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 612 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 613 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 614 # define DYN_LIGHT_SLEEP_EN (1 << 14) 615 #define MCLK_PWRMGT_CNTL 0x648 616 # define DLL_SPEED(x) ((x) << 0) 617 # define DLL_SPEED_MASK (0x1f << 0) 618 # define MPLL_PWRMGT_OFF (1 << 5) 619 # define DLL_READY (1 << 6) 620 # define MC_INT_CNTL (1 << 7) 621 # define MRDCKA0_PDNB (1 << 8) 622 # define MRDCKA1_PDNB (1 << 9) 623 # define MRDCKB0_PDNB (1 << 10) 624 # define MRDCKB1_PDNB (1 << 11) 625 # define MRDCKC0_PDNB (1 << 12) 626 # define MRDCKC1_PDNB (1 << 13) 627 # define MRDCKD0_PDNB (1 << 14) 628 # define MRDCKD1_PDNB (1 << 15) 629 # define MRDCKA0_RESET (1 << 16) 630 # define MRDCKA1_RESET (1 << 17) 631 # define MRDCKB0_RESET (1 << 18) 632 # define MRDCKB1_RESET (1 << 19) 633 # define MRDCKC0_RESET (1 << 20) 634 # define MRDCKC1_RESET (1 << 21) 635 # define MRDCKD0_RESET (1 << 22) 636 # define MRDCKD1_RESET (1 << 23) 637 # define DLL_READY_READ (1 << 24) 638 # define USE_DISPLAY_GAP (1 << 25) 639 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 640 # define MPLL_TURNOFF_D2 (1 << 28) 641 #define DLL_CNTL 0x64c 642 # define MRDCKA0_BYPASS (1 << 24) 643 # define MRDCKA1_BYPASS (1 << 25) 644 # define MRDCKB0_BYPASS (1 << 26) 645 # define MRDCKB1_BYPASS (1 << 27) 646 # define MRDCKC0_BYPASS (1 << 28) 647 # define MRDCKC1_BYPASS (1 << 29) 648 # define MRDCKD0_BYPASS (1 << 30) 649 # define MRDCKD1_BYPASS (1 << 31) 650 651 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 652 # define CURRENT_STATE_INDEX_MASK (0xf << 4) 653 # define CURRENT_STATE_INDEX_SHIFT 4 654 655 #define CG_AT 0x6d4 656 # define CG_R(x) ((x) << 0) 657 # define CG_R_MASK (0xffff << 0) 658 # define CG_L(x) ((x) << 16) 659 # define CG_L_MASK (0xffff << 16) 660 661 #define CG_BIF_REQ_AND_RSP 0x7f4 662 #define CG_CLIENT_REQ(x) ((x) << 0) 663 #define CG_CLIENT_REQ_MASK (0xff << 0) 664 #define CG_CLIENT_REQ_SHIFT 0 665 #define CG_CLIENT_RESP(x) ((x) << 8) 666 #define CG_CLIENT_RESP_MASK (0xff << 8) 667 #define CG_CLIENT_RESP_SHIFT 8 668 #define CLIENT_CG_REQ(x) ((x) << 16) 669 #define CLIENT_CG_REQ_MASK (0xff << 16) 670 #define CLIENT_CG_REQ_SHIFT 16 671 #define CLIENT_CG_RESP(x) ((x) << 24) 672 #define CLIENT_CG_RESP_MASK (0xff << 24) 673 #define CLIENT_CG_RESP_SHIFT 24 674 675 #define CG_SPLL_SPREAD_SPECTRUM 0x790 676 #define SSEN (1 << 0) 677 #define CLK_S(x) ((x) << 4) 678 #define CLK_S_MASK (0xfff << 4) 679 #define CLK_S_SHIFT 4 680 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 681 #define CLK_V(x) ((x) << 0) 682 #define CLK_V_MASK (0x3ffffff << 0) 683 #define CLK_V_SHIFT 0 684 685 #define SMC_SCRATCH0 0x81c 686 687 #define CG_SPLL_FUNC_CNTL_4 0x850 688 689 #define MPLL_SS1 0x85c 690 #define CLKV(x) ((x) << 0) 691 #define CLKV_MASK (0x3ffffff << 0) 692 #define MPLL_SS2 0x860 693 #define CLKS(x) ((x) << 0) 694 #define CLKS_MASK (0xfff << 0) 695 696 #define CG_CAC_CTRL 0x88c 697 #define TID_CNT(x) ((x) << 0) 698 #define TID_CNT_MASK (0x3fff << 0) 699 #define TID_UNIT(x) ((x) << 14) 700 #define TID_UNIT_MASK (0xf << 14) 701 702 #define CG_IND_ADDR 0x8f8 703 #define CG_IND_DATA 0x8fc 704 /* CGIND regs */ 705 #define CG_CGTT_LOCAL_0 0x00 706 #define CG_CGTT_LOCAL_1 0x01 707 708 #define MC_CG_CONFIG 0x25bc 709 #define MCDW_WR_ENABLE (1 << 0) 710 #define MCDX_WR_ENABLE (1 << 1) 711 #define MCDY_WR_ENABLE (1 << 2) 712 #define MCDZ_WR_ENABLE (1 << 3) 713 #define MC_RD_ENABLE(x) ((x) << 4) 714 #define MC_RD_ENABLE_MASK (3 << 4) 715 #define INDEX(x) ((x) << 6) 716 #define INDEX_MASK (0xfff << 6) 717 #define INDEX_SHIFT 6 718 719 #define MC_ARB_CAC_CNTL 0x2750 720 #define ENABLE (1 << 0) 721 #define READ_WEIGHT(x) ((x) << 1) 722 #define READ_WEIGHT_MASK (0x3f << 1) 723 #define READ_WEIGHT_SHIFT 1 724 #define WRITE_WEIGHT(x) ((x) << 7) 725 #define WRITE_WEIGHT_MASK (0x3f << 7) 726 #define WRITE_WEIGHT_SHIFT 7 727 #define ALLOW_OVERFLOW (1 << 13) 728 729 #define MC_ARB_DRAM_TIMING 0x2774 730 #define MC_ARB_DRAM_TIMING2 0x2778 731 732 #define MC_ARB_RFSH_RATE 0x27b0 733 #define POWERMODE0(x) ((x) << 0) 734 #define POWERMODE0_MASK (0xff << 0) 735 #define POWERMODE0_SHIFT 0 736 #define POWERMODE1(x) ((x) << 8) 737 #define POWERMODE1_MASK (0xff << 8) 738 #define POWERMODE1_SHIFT 8 739 #define POWERMODE2(x) ((x) << 16) 740 #define POWERMODE2_MASK (0xff << 16) 741 #define POWERMODE2_SHIFT 16 742 #define POWERMODE3(x) ((x) << 24) 743 #define POWERMODE3_MASK (0xff << 24) 744 #define POWERMODE3_SHIFT 24 745 746 #define MC_ARB_CG 0x27e8 747 #define CG_ARB_REQ(x) ((x) << 0) 748 #define CG_ARB_REQ_MASK (0xff << 0) 749 #define CG_ARB_REQ_SHIFT 0 750 #define CG_ARB_RESP(x) ((x) << 8) 751 #define CG_ARB_RESP_MASK (0xff << 8) 752 #define CG_ARB_RESP_SHIFT 8 753 #define ARB_CG_REQ(x) ((x) << 16) 754 #define ARB_CG_REQ_MASK (0xff << 16) 755 #define ARB_CG_REQ_SHIFT 16 756 #define ARB_CG_RESP(x) ((x) << 24) 757 #define ARB_CG_RESP_MASK (0xff << 24) 758 #define ARB_CG_RESP_SHIFT 24 759 760 #define MC_ARB_DRAM_TIMING_1 0x27f0 761 #define MC_ARB_DRAM_TIMING_2 0x27f4 762 #define MC_ARB_DRAM_TIMING_3 0x27f8 763 #define MC_ARB_DRAM_TIMING2_1 0x27fc 764 #define MC_ARB_DRAM_TIMING2_2 0x2800 765 #define MC_ARB_DRAM_TIMING2_3 0x2804 766 #define MC_ARB_BURST_TIME 0x2808 767 #define STATE0(x) ((x) << 0) 768 #define STATE0_MASK (0x1f << 0) 769 #define STATE0_SHIFT 0 770 #define STATE1(x) ((x) << 5) 771 #define STATE1_MASK (0x1f << 5) 772 #define STATE1_SHIFT 5 773 #define STATE2(x) ((x) << 10) 774 #define STATE2_MASK (0x1f << 10) 775 #define STATE2_SHIFT 10 776 #define STATE3(x) ((x) << 15) 777 #define STATE3_MASK (0x1f << 15) 778 #define STATE3_SHIFT 15 779 780 #define MC_CG_DATAPORT 0x2884 781 782 #define MC_SEQ_RAS_TIMING 0x28a0 783 #define MC_SEQ_CAS_TIMING 0x28a4 784 #define MC_SEQ_MISC_TIMING 0x28a8 785 #define MC_SEQ_MISC_TIMING2 0x28ac 786 #define MC_SEQ_PMG_TIMING 0x28b0 787 #define MC_SEQ_RD_CTL_D0 0x28b4 788 #define MC_SEQ_RD_CTL_D1 0x28b8 789 #define MC_SEQ_WR_CTL_D0 0x28bc 790 #define MC_SEQ_WR_CTL_D1 0x28c0 791 792 #define MC_SEQ_MISC0 0x2a00 793 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 794 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 795 #define MC_SEQ_MISC0_GDDR5_VALUE 5 796 #define MC_SEQ_MISC1 0x2a04 797 #define MC_SEQ_RESERVE_M 0x2a08 798 #define MC_PMG_CMD_EMRS 0x2a0c 799 800 #define MC_SEQ_MISC3 0x2a2c 801 802 #define MC_SEQ_MISC5 0x2a54 803 #define MC_SEQ_MISC6 0x2a58 804 805 #define MC_SEQ_MISC7 0x2a64 806 807 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 808 #define MC_SEQ_CAS_TIMING_LP 0x2a70 809 #define MC_SEQ_MISC_TIMING_LP 0x2a74 810 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 811 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 812 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 813 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 814 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 815 816 #define MC_PMG_CMD_MRS 0x2aac 817 818 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 819 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 820 821 #define MC_PMG_CMD_MRS1 0x2b44 822 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 823 #define MC_SEQ_PMG_TIMING_LP 0x2b4c 824 825 #define MC_PMG_CMD_MRS2 0x2b5c 826 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 827 828 #define AUX_CONTROL 0x6200 829 #define AUX_EN (1 << 0) 830 #define AUX_LS_READ_EN (1 << 8) 831 #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) 832 #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16) 833 #define AUX_DET_EN (1 << 18) 834 #define AUX_HPD_SEL(x) (((x) & 0x7) << 20) 835 #define AUX_IMPCAL_REQ_EN (1 << 24) 836 #define AUX_TEST_MODE (1 << 28) 837 #define AUX_DEGLITCH_EN (1 << 29) 838 #define AUX_SW_CONTROL 0x6204 839 #define AUX_SW_GO (1 << 0) 840 #define AUX_LS_READ_TRIG (1 << 2) 841 #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) 842 #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) 843 844 #define AUX_SW_INTERRUPT_CONTROL 0x620c 845 #define AUX_SW_DONE_INT (1 << 0) 846 #define AUX_SW_DONE_ACK (1 << 1) 847 #define AUX_SW_DONE_MASK (1 << 2) 848 #define AUX_SW_LS_DONE_INT (1 << 4) 849 #define AUX_SW_LS_DONE_MASK (1 << 6) 850 #define AUX_SW_STATUS 0x6210 851 #define AUX_SW_DONE (1 << 0) 852 #define AUX_SW_REQ (1 << 1) 853 #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) 854 #define AUX_SW_RX_TIMEOUT (1 << 7) 855 #define AUX_SW_RX_OVERFLOW (1 << 8) 856 #define AUX_SW_RX_HPD_DISCON (1 << 9) 857 #define AUX_SW_RX_PARTIAL_BYTE (1 << 10) 858 #define AUX_SW_NON_AUX_MODE (1 << 11) 859 #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12) 860 #define AUX_SW_RX_INVALID_STOP (1 << 14) 861 #define AUX_SW_RX_SYNC_INVALID_L (1 << 17) 862 #define AUX_SW_RX_SYNC_INVALID_H (1 << 18) 863 #define AUX_SW_RX_INVALID_START (1 << 19) 864 #define AUX_SW_RX_RECV_NO_DET (1 << 20) 865 #define AUX_SW_RX_RECV_INVALID_H (1 << 22) 866 #define AUX_SW_RX_RECV_INVALID_V (1 << 23) 867 868 #define AUX_SW_DATA 0x6218 869 #define AUX_SW_DATA_RW (1 << 0) 870 #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) 871 #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) 872 #define AUX_SW_AUTOINCREMENT_DISABLE (1U << 31) 873 874 #define LB_SYNC_RESET_SEL 0x6b28 875 #define LB_SYNC_RESET_SEL_MASK (3 << 0) 876 #define LB_SYNC_RESET_SEL_SHIFT 0 877 878 #define DC_STUTTER_CNTL 0x6b30 879 #define DC_STUTTER_ENABLE_A (1 << 0) 880 #define DC_STUTTER_ENABLE_B (1 << 1) 881 882 #define SQ_CAC_THRESHOLD 0x8e4c 883 #define VSP(x) ((x) << 0) 884 #define VSP_MASK (0xff << 0) 885 #define VSP_SHIFT 0 886 #define VSP0(x) ((x) << 8) 887 #define VSP0_MASK (0xff << 8) 888 #define VSP0_SHIFT 8 889 #define GPR(x) ((x) << 16) 890 #define GPR_MASK (0xff << 16) 891 #define GPR_SHIFT 16 892 893 #define SQ_POWER_THROTTLE 0x8e58 894 #define MIN_POWER(x) ((x) << 0) 895 #define MIN_POWER_MASK (0x3fff << 0) 896 #define MIN_POWER_SHIFT 0 897 #define MAX_POWER(x) ((x) << 16) 898 #define MAX_POWER_MASK (0x3fff << 16) 899 #define MAX_POWER_SHIFT 0 900 #define SQ_POWER_THROTTLE2 0x8e5c 901 #define MAX_POWER_DELTA(x) ((x) << 0) 902 #define MAX_POWER_DELTA_MASK (0x3fff << 0) 903 #define MAX_POWER_DELTA_SHIFT 0 904 #define STI_SIZE(x) ((x) << 16) 905 #define STI_SIZE_MASK (0x3ff << 16) 906 #define STI_SIZE_SHIFT 16 907 #define LTI_RATIO(x) ((x) << 27) 908 #define LTI_RATIO_MASK (0xf << 27) 909 #define LTI_RATIO_SHIFT 27 910 911 /* CG indirect registers */ 912 #define CG_CAC_REGION_1_WEIGHT_0 0x83 913 #define WEIGHT_TCP_SIG0(x) ((x) << 0) 914 #define WEIGHT_TCP_SIG0_MASK (0x3f << 0) 915 #define WEIGHT_TCP_SIG0_SHIFT 0 916 #define WEIGHT_TCP_SIG1(x) ((x) << 6) 917 #define WEIGHT_TCP_SIG1_MASK (0x3f << 6) 918 #define WEIGHT_TCP_SIG1_SHIFT 6 919 #define WEIGHT_TA_SIG(x) ((x) << 12) 920 #define WEIGHT_TA_SIG_MASK (0x3f << 12) 921 #define WEIGHT_TA_SIG_SHIFT 12 922 #define CG_CAC_REGION_1_WEIGHT_1 0x84 923 #define WEIGHT_TCC_EN0(x) ((x) << 0) 924 #define WEIGHT_TCC_EN0_MASK (0x3f << 0) 925 #define WEIGHT_TCC_EN0_SHIFT 0 926 #define WEIGHT_TCC_EN1(x) ((x) << 6) 927 #define WEIGHT_TCC_EN1_MASK (0x3f << 6) 928 #define WEIGHT_TCC_EN1_SHIFT 6 929 #define WEIGHT_TCC_EN2(x) ((x) << 12) 930 #define WEIGHT_TCC_EN2_MASK (0x3f << 12) 931 #define WEIGHT_TCC_EN2_SHIFT 12 932 #define WEIGHT_TCC_EN3(x) ((x) << 18) 933 #define WEIGHT_TCC_EN3_MASK (0x3f << 18) 934 #define WEIGHT_TCC_EN3_SHIFT 18 935 #define CG_CAC_REGION_2_WEIGHT_0 0x85 936 #define WEIGHT_CB_EN0(x) ((x) << 0) 937 #define WEIGHT_CB_EN0_MASK (0x3f << 0) 938 #define WEIGHT_CB_EN0_SHIFT 0 939 #define WEIGHT_CB_EN1(x) ((x) << 6) 940 #define WEIGHT_CB_EN1_MASK (0x3f << 6) 941 #define WEIGHT_CB_EN1_SHIFT 6 942 #define WEIGHT_CB_EN2(x) ((x) << 12) 943 #define WEIGHT_CB_EN2_MASK (0x3f << 12) 944 #define WEIGHT_CB_EN2_SHIFT 12 945 #define WEIGHT_CB_EN3(x) ((x) << 18) 946 #define WEIGHT_CB_EN3_MASK (0x3f << 18) 947 #define WEIGHT_CB_EN3_SHIFT 18 948 #define CG_CAC_REGION_2_WEIGHT_1 0x86 949 #define WEIGHT_DB_SIG0(x) ((x) << 0) 950 #define WEIGHT_DB_SIG0_MASK (0x3f << 0) 951 #define WEIGHT_DB_SIG0_SHIFT 0 952 #define WEIGHT_DB_SIG1(x) ((x) << 6) 953 #define WEIGHT_DB_SIG1_MASK (0x3f << 6) 954 #define WEIGHT_DB_SIG1_SHIFT 6 955 #define WEIGHT_DB_SIG2(x) ((x) << 12) 956 #define WEIGHT_DB_SIG2_MASK (0x3f << 12) 957 #define WEIGHT_DB_SIG2_SHIFT 12 958 #define WEIGHT_DB_SIG3(x) ((x) << 18) 959 #define WEIGHT_DB_SIG3_MASK (0x3f << 18) 960 #define WEIGHT_DB_SIG3_SHIFT 18 961 #define CG_CAC_REGION_2_WEIGHT_2 0x87 962 #define WEIGHT_SXM_SIG0(x) ((x) << 0) 963 #define WEIGHT_SXM_SIG0_MASK (0x3f << 0) 964 #define WEIGHT_SXM_SIG0_SHIFT 0 965 #define WEIGHT_SXM_SIG1(x) ((x) << 6) 966 #define WEIGHT_SXM_SIG1_MASK (0x3f << 6) 967 #define WEIGHT_SXM_SIG1_SHIFT 6 968 #define WEIGHT_SXM_SIG2(x) ((x) << 12) 969 #define WEIGHT_SXM_SIG2_MASK (0x3f << 12) 970 #define WEIGHT_SXM_SIG2_SHIFT 12 971 #define WEIGHT_SXS_SIG0(x) ((x) << 18) 972 #define WEIGHT_SXS_SIG0_MASK (0x3f << 18) 973 #define WEIGHT_SXS_SIG0_SHIFT 18 974 #define WEIGHT_SXS_SIG1(x) ((x) << 24) 975 #define WEIGHT_SXS_SIG1_MASK (0x3f << 24) 976 #define WEIGHT_SXS_SIG1_SHIFT 24 977 #define CG_CAC_REGION_3_WEIGHT_0 0x88 978 #define WEIGHT_XBR_0(x) ((x) << 0) 979 #define WEIGHT_XBR_0_MASK (0x3f << 0) 980 #define WEIGHT_XBR_0_SHIFT 0 981 #define WEIGHT_XBR_1(x) ((x) << 6) 982 #define WEIGHT_XBR_1_MASK (0x3f << 6) 983 #define WEIGHT_XBR_1_SHIFT 6 984 #define WEIGHT_XBR_2(x) ((x) << 12) 985 #define WEIGHT_XBR_2_MASK (0x3f << 12) 986 #define WEIGHT_XBR_2_SHIFT 12 987 #define WEIGHT_SPI_SIG0(x) ((x) << 18) 988 #define WEIGHT_SPI_SIG0_MASK (0x3f << 18) 989 #define WEIGHT_SPI_SIG0_SHIFT 18 990 #define CG_CAC_REGION_3_WEIGHT_1 0x89 991 #define WEIGHT_SPI_SIG1(x) ((x) << 0) 992 #define WEIGHT_SPI_SIG1_MASK (0x3f << 0) 993 #define WEIGHT_SPI_SIG1_SHIFT 0 994 #define WEIGHT_SPI_SIG2(x) ((x) << 6) 995 #define WEIGHT_SPI_SIG2_MASK (0x3f << 6) 996 #define WEIGHT_SPI_SIG2_SHIFT 6 997 #define WEIGHT_SPI_SIG3(x) ((x) << 12) 998 #define WEIGHT_SPI_SIG3_MASK (0x3f << 12) 999 #define WEIGHT_SPI_SIG3_SHIFT 12 1000 #define WEIGHT_SPI_SIG4(x) ((x) << 18) 1001 #define WEIGHT_SPI_SIG4_MASK (0x3f << 18) 1002 #define WEIGHT_SPI_SIG4_SHIFT 18 1003 #define WEIGHT_SPI_SIG5(x) ((x) << 24) 1004 #define WEIGHT_SPI_SIG5_MASK (0x3f << 24) 1005 #define WEIGHT_SPI_SIG5_SHIFT 24 1006 #define CG_CAC_REGION_4_WEIGHT_0 0x8a 1007 #define WEIGHT_LDS_SIG0(x) ((x) << 0) 1008 #define WEIGHT_LDS_SIG0_MASK (0x3f << 0) 1009 #define WEIGHT_LDS_SIG0_SHIFT 0 1010 #define WEIGHT_LDS_SIG1(x) ((x) << 6) 1011 #define WEIGHT_LDS_SIG1_MASK (0x3f << 6) 1012 #define WEIGHT_LDS_SIG1_SHIFT 6 1013 #define WEIGHT_SC(x) ((x) << 24) 1014 #define WEIGHT_SC_MASK (0x3f << 24) 1015 #define WEIGHT_SC_SHIFT 24 1016 #define CG_CAC_REGION_4_WEIGHT_1 0x8b 1017 #define WEIGHT_BIF(x) ((x) << 0) 1018 #define WEIGHT_BIF_MASK (0x3f << 0) 1019 #define WEIGHT_BIF_SHIFT 0 1020 #define WEIGHT_CP(x) ((x) << 6) 1021 #define WEIGHT_CP_MASK (0x3f << 6) 1022 #define WEIGHT_CP_SHIFT 6 1023 #define WEIGHT_PA_SIG0(x) ((x) << 12) 1024 #define WEIGHT_PA_SIG0_MASK (0x3f << 12) 1025 #define WEIGHT_PA_SIG0_SHIFT 12 1026 #define WEIGHT_PA_SIG1(x) ((x) << 18) 1027 #define WEIGHT_PA_SIG1_MASK (0x3f << 18) 1028 #define WEIGHT_PA_SIG1_SHIFT 18 1029 #define WEIGHT_VGT_SIG0(x) ((x) << 24) 1030 #define WEIGHT_VGT_SIG0_MASK (0x3f << 24) 1031 #define WEIGHT_VGT_SIG0_SHIFT 24 1032 #define CG_CAC_REGION_4_WEIGHT_2 0x8c 1033 #define WEIGHT_VGT_SIG1(x) ((x) << 0) 1034 #define WEIGHT_VGT_SIG1_MASK (0x3f << 0) 1035 #define WEIGHT_VGT_SIG1_SHIFT 0 1036 #define WEIGHT_VGT_SIG2(x) ((x) << 6) 1037 #define WEIGHT_VGT_SIG2_MASK (0x3f << 6) 1038 #define WEIGHT_VGT_SIG2_SHIFT 6 1039 #define WEIGHT_DC_SIG0(x) ((x) << 12) 1040 #define WEIGHT_DC_SIG0_MASK (0x3f << 12) 1041 #define WEIGHT_DC_SIG0_SHIFT 12 1042 #define WEIGHT_DC_SIG1(x) ((x) << 18) 1043 #define WEIGHT_DC_SIG1_MASK (0x3f << 18) 1044 #define WEIGHT_DC_SIG1_SHIFT 18 1045 #define WEIGHT_DC_SIG2(x) ((x) << 24) 1046 #define WEIGHT_DC_SIG2_MASK (0x3f << 24) 1047 #define WEIGHT_DC_SIG2_SHIFT 24 1048 #define CG_CAC_REGION_4_WEIGHT_3 0x8d 1049 #define WEIGHT_DC_SIG3(x) ((x) << 0) 1050 #define WEIGHT_DC_SIG3_MASK (0x3f << 0) 1051 #define WEIGHT_DC_SIG3_SHIFT 0 1052 #define WEIGHT_UVD_SIG0(x) ((x) << 6) 1053 #define WEIGHT_UVD_SIG0_MASK (0x3f << 6) 1054 #define WEIGHT_UVD_SIG0_SHIFT 6 1055 #define WEIGHT_UVD_SIG1(x) ((x) << 12) 1056 #define WEIGHT_UVD_SIG1_MASK (0x3f << 12) 1057 #define WEIGHT_UVD_SIG1_SHIFT 12 1058 #define WEIGHT_SPARE0(x) ((x) << 18) 1059 #define WEIGHT_SPARE0_MASK (0x3f << 18) 1060 #define WEIGHT_SPARE0_SHIFT 18 1061 #define WEIGHT_SPARE1(x) ((x) << 24) 1062 #define WEIGHT_SPARE1_MASK (0x3f << 24) 1063 #define WEIGHT_SPARE1_SHIFT 24 1064 #define CG_CAC_REGION_5_WEIGHT_0 0x8e 1065 #define WEIGHT_SQ_VSP(x) ((x) << 0) 1066 #define WEIGHT_SQ_VSP_MASK (0x3fff << 0) 1067 #define WEIGHT_SQ_VSP_SHIFT 0 1068 #define WEIGHT_SQ_VSP0(x) ((x) << 14) 1069 #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14) 1070 #define WEIGHT_SQ_VSP0_SHIFT 14 1071 #define CG_CAC_REGION_4_OVERRIDE_4 0xab 1072 #define OVR_MODE_SPARE_0(x) ((x) << 16) 1073 #define OVR_MODE_SPARE_0_MASK (0x1 << 16) 1074 #define OVR_MODE_SPARE_0_SHIFT 16 1075 #define OVR_VAL_SPARE_0(x) ((x) << 17) 1076 #define OVR_VAL_SPARE_0_MASK (0x1 << 17) 1077 #define OVR_VAL_SPARE_0_SHIFT 17 1078 #define OVR_MODE_SPARE_1(x) ((x) << 18) 1079 #define OVR_MODE_SPARE_1_MASK (0x3f << 18) 1080 #define OVR_MODE_SPARE_1_SHIFT 18 1081 #define OVR_VAL_SPARE_1(x) ((x) << 19) 1082 #define OVR_VAL_SPARE_1_MASK (0x3f << 19) 1083 #define OVR_VAL_SPARE_1_SHIFT 19 1084 #define CG_CAC_REGION_5_WEIGHT_1 0xb7 1085 #define WEIGHT_SQ_GPR(x) ((x) << 0) 1086 #define WEIGHT_SQ_GPR_MASK (0x3fff << 0) 1087 #define WEIGHT_SQ_GPR_SHIFT 0 1088 #define WEIGHT_SQ_LDS(x) ((x) << 14) 1089 #define WEIGHT_SQ_LDS_MASK (0x3fff << 14) 1090 #define WEIGHT_SQ_LDS_SHIFT 14 1091 1092 /* PCIE link stuff */ 1093 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 1094 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1095 # define LC_LINK_WIDTH_SHIFT 0 1096 # define LC_LINK_WIDTH_MASK 0x7 1097 # define LC_LINK_WIDTH_X0 0 1098 # define LC_LINK_WIDTH_X1 1 1099 # define LC_LINK_WIDTH_X2 2 1100 # define LC_LINK_WIDTH_X4 3 1101 # define LC_LINK_WIDTH_X8 4 1102 # define LC_LINK_WIDTH_X16 6 1103 # define LC_LINK_WIDTH_RD_SHIFT 4 1104 # define LC_LINK_WIDTH_RD_MASK 0x70 1105 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1106 # define LC_RECONFIG_NOW (1 << 8) 1107 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1108 # define LC_RENEGOTIATE_EN (1 << 10) 1109 # define LC_SHORT_RECONFIG_EN (1 << 11) 1110 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1111 # define LC_UPCONFIGURE_DIS (1 << 13) 1112 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1113 # define LC_GEN2_EN_STRAP (1 << 0) 1114 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 1115 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 1116 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 1117 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 1118 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 1119 # define LC_CURRENT_DATA_RATE (1 << 11) 1120 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 1121 # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 1122 # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 1123 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 1124 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 1125 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 1126 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 1127 #define MM_CFGREGS_CNTL 0x544c 1128 # define MM_WR_TO_CFG_EN (1 << 3) 1129 #define LINK_CNTL2 0x88 /* F0 */ 1130 # define TARGET_LINK_SPEED_MASK (0xf << 0) 1131 # define SELECTABLE_DEEMPHASIS (1 << 6) 1132 1133 /* 1134 * UVD 1135 */ 1136 #define UVD_SEMA_ADDR_LOW 0xEF00 1137 #define UVD_SEMA_ADDR_HIGH 0xEF04 1138 #define UVD_SEMA_CMD 0xEF08 1139 #define UVD_UDEC_ADDR_CONFIG 0xEF4C 1140 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 1141 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1142 #define UVD_NO_OP 0xEFFC 1143 #define UVD_RBC_RB_RPTR 0xF690 1144 #define UVD_RBC_RB_WPTR 0xF694 1145 #define UVD_STATUS 0xf6bc 1146 1147 /* 1148 * PM4 1149 */ 1150 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1151 (((reg) >> 2) & 0xFFFF) | \ 1152 ((n) & 0x3FFF) << 16) 1153 #define CP_PACKET2 0x80000000 1154 #define PACKET2_PAD_SHIFT 0 1155 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1156 1157 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1158 1159 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1160 (((op) & 0xFF) << 8) | \ 1161 ((n) & 0x3FFF) << 16) 1162 1163 /* Packet 3 types */ 1164 #define PACKET3_NOP 0x10 1165 #define PACKET3_SET_BASE 0x11 1166 #define PACKET3_CLEAR_STATE 0x12 1167 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1168 #define PACKET3_DEALLOC_STATE 0x14 1169 #define PACKET3_DISPATCH_DIRECT 0x15 1170 #define PACKET3_DISPATCH_INDIRECT 0x16 1171 #define PACKET3_INDIRECT_BUFFER_END 0x17 1172 #define PACKET3_MODE_CONTROL 0x18 1173 #define PACKET3_SET_PREDICATION 0x20 1174 #define PACKET3_REG_RMW 0x21 1175 #define PACKET3_COND_EXEC 0x22 1176 #define PACKET3_PRED_EXEC 0x23 1177 #define PACKET3_DRAW_INDIRECT 0x24 1178 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1179 #define PACKET3_INDEX_BASE 0x26 1180 #define PACKET3_DRAW_INDEX_2 0x27 1181 #define PACKET3_CONTEXT_CONTROL 0x28 1182 #define PACKET3_DRAW_INDEX_OFFSET 0x29 1183 #define PACKET3_INDEX_TYPE 0x2A 1184 #define PACKET3_DRAW_INDEX 0x2B 1185 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1186 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1187 #define PACKET3_NUM_INSTANCES 0x2F 1188 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1189 #define PACKET3_INDIRECT_BUFFER 0x32 1190 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1191 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1192 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1193 #define PACKET3_WRITE_DATA 0x37 1194 #define PACKET3_MEM_SEMAPHORE 0x39 1195 #define PACKET3_MPEG_INDEX 0x3A 1196 #define PACKET3_WAIT_REG_MEM 0x3C 1197 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1198 /* 0 - always 1199 * 1 - < 1200 * 2 - <= 1201 * 3 - == 1202 * 4 - != 1203 * 5 - >= 1204 * 6 - > 1205 */ 1206 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1207 /* 0 - reg 1208 * 1 - mem 1209 */ 1210 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1211 /* 0 - me 1212 * 1 - pfp 1213 */ 1214 #define PACKET3_MEM_WRITE 0x3D 1215 #define PACKET3_PFP_SYNC_ME 0x42 1216 #define PACKET3_SURFACE_SYNC 0x43 1217 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1218 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1219 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1220 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1221 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1222 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1223 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1224 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1225 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1226 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1227 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1228 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1229 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1230 # define PACKET3_FULL_CACHE_ENA (1 << 20) 1231 # define PACKET3_TC_ACTION_ENA (1 << 23) 1232 # define PACKET3_CB_ACTION_ENA (1 << 25) 1233 # define PACKET3_DB_ACTION_ENA (1 << 26) 1234 # define PACKET3_SH_ACTION_ENA (1 << 27) 1235 # define PACKET3_SX_ACTION_ENA (1 << 28) 1236 # define PACKET3_ENGINE_ME (1 << 31) 1237 #define PACKET3_ME_INITIALIZE 0x44 1238 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1239 #define PACKET3_COND_WRITE 0x45 1240 #define PACKET3_EVENT_WRITE 0x46 1241 #define EVENT_TYPE(x) ((x) << 0) 1242 #define EVENT_INDEX(x) ((x) << 8) 1243 /* 0 - any non-TS event 1244 * 1 - ZPASS_DONE 1245 * 2 - SAMPLE_PIPELINESTAT 1246 * 3 - SAMPLE_STREAMOUTSTAT* 1247 * 4 - *S_PARTIAL_FLUSH 1248 * 5 - TS events 1249 */ 1250 #define PACKET3_EVENT_WRITE_EOP 0x47 1251 #define DATA_SEL(x) ((x) << 29) 1252 /* 0 - discard 1253 * 1 - send low 32bit data 1254 * 2 - send 64bit data 1255 * 3 - send 64bit counter value 1256 */ 1257 #define INT_SEL(x) ((x) << 24) 1258 /* 0 - none 1259 * 1 - interrupt only (DATA_SEL = 0) 1260 * 2 - interrupt when data write is confirmed 1261 */ 1262 #define PACKET3_EVENT_WRITE_EOS 0x48 1263 #define PACKET3_PREAMBLE_CNTL 0x4A 1264 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1265 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1266 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1267 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1268 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1269 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1270 #define PACKET3_ONE_REG_WRITE 0x57 1271 #define PACKET3_SET_CONFIG_REG 0x68 1272 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1273 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1274 #define PACKET3_SET_CONTEXT_REG 0x69 1275 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1276 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1277 #define PACKET3_SET_ALU_CONST 0x6A 1278 /* alu const buffers only; no reg file */ 1279 #define PACKET3_SET_BOOL_CONST 0x6B 1280 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 1281 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 1282 #define PACKET3_SET_LOOP_CONST 0x6C 1283 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 1284 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1285 #define PACKET3_SET_RESOURCE 0x6D 1286 #define PACKET3_SET_RESOURCE_START 0x00030000 1287 #define PACKET3_SET_RESOURCE_END 0x00038000 1288 #define PACKET3_SET_SAMPLER 0x6E 1289 #define PACKET3_SET_SAMPLER_START 0x0003c000 1290 #define PACKET3_SET_SAMPLER_END 0x0003c600 1291 #define PACKET3_SET_CTL_CONST 0x6F 1292 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1293 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1294 #define PACKET3_SET_RESOURCE_OFFSET 0x70 1295 #define PACKET3_SET_ALU_CONST_VS 0x71 1296 #define PACKET3_SET_ALU_CONST_DI 0x72 1297 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1298 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1299 #define PACKET3_SET_APPEND_CNT 0x75 1300 #define PACKET3_ME_WRITE 0x7A 1301 1302 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1303 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1304 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1305 1306 #define DMA_RB_CNTL 0xd000 1307 # define DMA_RB_ENABLE (1 << 0) 1308 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1309 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1310 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1311 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1312 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1313 #define DMA_RB_BASE 0xd004 1314 #define DMA_RB_RPTR 0xd008 1315 #define DMA_RB_WPTR 0xd00c 1316 1317 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1318 #define DMA_RB_RPTR_ADDR_LO 0xd020 1319 1320 #define DMA_IB_CNTL 0xd024 1321 # define DMA_IB_ENABLE (1 << 0) 1322 # define DMA_IB_SWAP_ENABLE (1 << 4) 1323 # define CMD_VMID_FORCE (1U << 31) 1324 #define DMA_IB_RPTR 0xd028 1325 #define DMA_CNTL 0xd02c 1326 # define TRAP_ENABLE (1 << 0) 1327 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1328 # define SEM_WAIT_INT_ENABLE (1 << 2) 1329 # define DATA_SWAP_ENABLE (1 << 3) 1330 # define FENCE_SWAP_ENABLE (1 << 4) 1331 # define CTXEMPTY_INT_ENABLE (1 << 28) 1332 #define DMA_STATUS_REG 0xd034 1333 # define DMA_IDLE (1 << 0) 1334 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 1335 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 1336 #define DMA_TILING_CONFIG 0xd0b8 1337 #define DMA_MODE 0xd0bc 1338 1339 #define DMA_PACKET(cmd, t, s, n) ((((uint32_t)(cmd) & 0xF) << 28) | \ 1340 (((t) & 0x1) << 23) | \ 1341 (((s) & 0x1) << 22) | \ 1342 (((n) & 0xFFFFF) << 0)) 1343 1344 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1345 (((vmid) & 0xF) << 20) | \ 1346 (((n) & 0xFFFFF) << 0)) 1347 1348 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1349 (1 << 26) | \ 1350 (1 << 21) | \ 1351 (((n) & 0xFFFFF) << 0)) 1352 1353 #define DMA_SRBM_POLL_PACKET ((9 << 28) | \ 1354 (1 << 27) | \ 1355 (1 << 26)) 1356 1357 #define DMA_SRBM_READ_PACKET ((9 << 28) | \ 1358 (1 << 27)) 1359 1360 /* async DMA Packet types */ 1361 #define DMA_PACKET_WRITE 0x2 1362 #define DMA_PACKET_COPY 0x3 1363 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1364 #define DMA_PACKET_SEMAPHORE 0x5 1365 #define DMA_PACKET_FENCE 0x6 1366 #define DMA_PACKET_TRAP 0x7 1367 #define DMA_PACKET_SRBM_WRITE 0x9 1368 #define DMA_PACKET_CONSTANT_FILL 0xd 1369 #define DMA_PACKET_NOP 0xf 1370 1371 #endif 1372