1 /*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __CSIO_HW_H__
36 #define __CSIO_HW_H__
37
38 #include <linux/kernel.h>
39 #include <linux/pci.h>
40 #include <linux/device.h>
41 #include <linux/workqueue.h>
42 #include <linux/compiler.h>
43 #include <linux/cdev.h>
44 #include <linux/list.h>
45 #include <linux/mempool.h>
46 #include <linux/io.h>
47 #include <linux/spinlock_types.h>
48 #include <scsi/scsi_device.h>
49 #include <scsi/scsi_transport_fc.h>
50
51 #include "t4_hw.h"
52 #include "csio_hw_chip.h"
53 #include "csio_wr.h"
54 #include "csio_mb.h"
55 #include "csio_scsi.h"
56 #include "csio_defs.h"
57 #include "t4_regs.h"
58 #include "t4_msg.h"
59
60 /*
61 * An error value used by host. Should not clash with FW defined return values.
62 */
63 #define FW_HOSTERROR 255
64
65 #define CSIO_HW_NAME "Chelsio FCoE Adapter"
66 #define CSIO_MAX_PFN 8
67 #define CSIO_MAX_PPORTS 4
68
69 #define CSIO_MAX_LUN 0xFFFF
70 #define CSIO_MAX_QUEUE 2048
71 #define CSIO_MAX_CMD_PER_LUN 32
72 #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
73 #define CSIO_MAX_SECTOR_SIZE 128
74 #define CSIO_MIN_T6_FW 0x01102D00 /* FW 1.16.45.0 */
75
76 /* Interrupts */
77 #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
78 * (Forward intr iq + fw iq) */
79 #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
80 #define CSIO_MAX_SCSI_CPU 128
81 #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
82 #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
83
84 /* Queues */
85 enum {
86 CSIO_INTR_WRSIZE = 128,
87 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
88 CSIO_FWEVT_WRSIZE = 128,
89 CSIO_FWEVT_IQLEN = 128,
90 CSIO_FWEVT_FLBUFS = 64,
91 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
92 CSIO_HW_NIQ = 1,
93 CSIO_HW_NFLQ = 1,
94 CSIO_HW_NEQ = 1,
95 CSIO_HW_NINTXQ = 1,
96 };
97
98 struct csio_msix_entries {
99 void *dev_id; /* Priv object associated w/ this msix*/
100 char desc[24]; /* Description of this vector */
101 };
102
103 struct csio_scsi_qset {
104 int iq_idx; /* Ingress index */
105 int eq_idx; /* Egress index */
106 uint32_t intr_idx; /* MSIX Vector index */
107 };
108
109 struct csio_scsi_cpu_info {
110 int16_t max_cpus;
111 };
112
113 extern int csio_dbg_level;
114 extern unsigned int csio_port_mask;
115 extern int csio_msi;
116
117 #define CSIO_VENDOR_ID 0x1425
118 #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
119 #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
120
121 #define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
122 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
123 PM_TX_F | PM_RX_F | ULP_RX_F | \
124 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
125
126 /*
127 * Hard parameters used to initialize the card in the absence of a
128 * configuration file.
129 */
130 enum {
131 /* General */
132 CSIO_SGE_DBFIFO_INT_THRESH = 10,
133
134 CSIO_SGE_RX_DMA_OFFSET = 2,
135
136 CSIO_SGE_FLBUF_SIZE1 = 65536,
137 CSIO_SGE_FLBUF_SIZE2 = 1536,
138 CSIO_SGE_FLBUF_SIZE3 = 9024,
139 CSIO_SGE_FLBUF_SIZE4 = 9216,
140 CSIO_SGE_FLBUF_SIZE5 = 2048,
141 CSIO_SGE_FLBUF_SIZE6 = 128,
142 CSIO_SGE_FLBUF_SIZE7 = 8192,
143 CSIO_SGE_FLBUF_SIZE8 = 16384,
144
145 CSIO_SGE_TIMER_VAL_0 = 5,
146 CSIO_SGE_TIMER_VAL_1 = 10,
147 CSIO_SGE_TIMER_VAL_2 = 20,
148 CSIO_SGE_TIMER_VAL_3 = 50,
149 CSIO_SGE_TIMER_VAL_4 = 100,
150 CSIO_SGE_TIMER_VAL_5 = 200,
151
152 CSIO_SGE_INT_CNT_VAL_0 = 1,
153 CSIO_SGE_INT_CNT_VAL_1 = 4,
154 CSIO_SGE_INT_CNT_VAL_2 = 8,
155 CSIO_SGE_INT_CNT_VAL_3 = 16,
156 };
157
158 /* Slowpath events */
159 enum csio_evt {
160 CSIO_EVT_FW = 0, /* FW event */
161 CSIO_EVT_MBX, /* MBX event */
162 CSIO_EVT_SCN, /* State change notification */
163 CSIO_EVT_DEV_LOSS, /* Device loss event */
164 CSIO_EVT_MAX, /* Max supported event */
165 };
166
167 #define CSIO_EVT_MSG_SIZE 512
168 #define CSIO_EVTQ_SIZE 512
169
170 /* Event msg */
171 struct csio_evt_msg {
172 struct list_head list; /* evt queue*/
173 enum csio_evt type;
174 uint8_t data[CSIO_EVT_MSG_SIZE];
175 };
176
177 enum {
178 SERNUM_LEN = 16, /* Serial # length */
179 EC_LEN = 16, /* E/C length */
180 ID_LEN = 16, /* ID length */
181 };
182
183 enum {
184 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
185 };
186
187 /* serial flash and firmware constants */
188 enum {
189 SF_ATTEMPTS = 10, /* max retries for SF operations */
190
191 /* flash command opcodes */
192 SF_PROG_PAGE = 2, /* program page */
193 SF_WR_DISABLE = 4, /* disable writes */
194 SF_RD_STATUS = 5, /* read status register */
195 SF_WR_ENABLE = 6, /* enable writes */
196 SF_RD_DATA_FAST = 0xb, /* read flash */
197 SF_RD_ID = 0x9f, /* read ID */
198 SF_ERASE_SECTOR = 0xd8, /* erase sector */
199 };
200
201 /* Management module */
202 enum {
203 CSIO_MGMT_EQ_WRSIZE = 512,
204 CSIO_MGMT_IQ_WRSIZE = 128,
205 CSIO_MGMT_EQLEN = 64,
206 CSIO_MGMT_IQLEN = 64,
207 };
208
209 #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
210 #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
211
212 /* mgmt module stats */
213 struct csio_mgmtm_stats {
214 uint32_t n_abort_req; /* Total abort request */
215 uint32_t n_abort_rsp; /* Total abort response */
216 uint32_t n_close_req; /* Total close request */
217 uint32_t n_close_rsp; /* Total close response */
218 uint32_t n_err; /* Total Errors */
219 uint32_t n_drop; /* Total request dropped */
220 uint32_t n_active; /* Count of active_q */
221 uint32_t n_cbfn; /* Count of cbfn_q */
222 };
223
224 /* MGMT module */
225 struct csio_mgmtm {
226 struct csio_hw *hw; /* Pointer to HW moduel */
227 int eq_idx; /* Egress queue index */
228 int iq_idx; /* Ingress queue index */
229 int msi_vec; /* MSI vector */
230 struct list_head active_q; /* Outstanding ELS/CT */
231 struct list_head abort_q; /* Outstanding abort req */
232 struct list_head cbfn_q; /* Completion queue */
233 struct list_head mgmt_req_freelist; /* Free poll of reqs */
234 /* ELSCT request freelist*/
235 struct timer_list mgmt_timer; /* MGMT timer */
236 struct csio_mgmtm_stats stats; /* ELS/CT stats */
237 };
238
239 struct csio_adap_desc {
240 char model_no[16];
241 char description[32];
242 };
243
244 struct pci_params {
245 uint16_t vendor_id;
246 uint16_t device_id;
247 int vpd_cap_addr;
248 uint16_t speed;
249 uint8_t width;
250 };
251
252 /* User configurable hw parameters */
253 struct csio_hw_params {
254 uint32_t sf_size; /* serial flash
255 * size in bytes
256 */
257 uint32_t sf_nsec; /* # of flash sectors */
258 struct pci_params pci;
259 uint32_t log_level; /* Module-level for
260 * debug log.
261 */
262 };
263
264 struct csio_vpd {
265 uint32_t cclk;
266 uint8_t ec[EC_LEN + 1];
267 uint8_t sn[SERNUM_LEN + 1];
268 uint8_t id[ID_LEN + 1];
269 };
270
271 /* Firmware Port Capabilities types. */
272
273 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
274 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
275
276 enum fw_caps {
277 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
278 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
279 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
280 };
281
282 enum cc_pause {
283 PAUSE_RX = 1 << 0,
284 PAUSE_TX = 1 << 1,
285 PAUSE_AUTONEG = 1 << 2
286 };
287
288 enum cc_fec {
289 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
290 FEC_RS = 1 << 1, /* Reed-Solomon */
291 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
292 };
293
294 struct link_config {
295 fw_port_cap32_t pcaps; /* link capabilities */
296 fw_port_cap32_t def_acaps; /* default advertised capabilities */
297 fw_port_cap32_t acaps; /* advertised capabilities */
298 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
299
300 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
301 unsigned int speed; /* actual link speed (Mb/s) */
302
303 enum cc_pause requested_fc; /* flow control user has requested */
304 enum cc_pause fc; /* actual link flow control */
305
306 enum cc_fec requested_fec; /* Forward Error Correction: */
307 enum cc_fec fec; /* requested and actual in use */
308
309 unsigned char autoneg; /* autonegotiating? */
310
311 unsigned char link_ok; /* link up? */
312 unsigned char link_down_rc; /* link down reason */
313 };
314
315 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
316
317 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
318 FW_PORT_CAP32_ANEG)
319
320 /* Enable or disable autonegotiation. */
321 #define AUTONEG_DISABLE 0x00
322 #define AUTONEG_ENABLE 0x01
323
324 struct csio_pport {
325 uint16_t pcap;
326 uint16_t acap;
327 uint8_t portid;
328 uint8_t link_status;
329 uint16_t link_speed;
330 uint8_t mac[6];
331 uint8_t mod_type;
332 uint8_t rsvd1;
333 uint8_t rsvd2;
334 uint8_t rsvd3;
335 struct link_config link_cfg;
336 };
337
338 /* fcoe resource information */
339 struct csio_fcoe_res_info {
340 uint16_t e_d_tov;
341 uint16_t r_a_tov_seq;
342 uint16_t r_a_tov_els;
343 uint16_t r_r_tov;
344 uint32_t max_xchgs;
345 uint32_t max_ssns;
346 uint32_t used_xchgs;
347 uint32_t used_ssns;
348 uint32_t max_fcfs;
349 uint32_t max_vnps;
350 uint32_t used_fcfs;
351 uint32_t used_vnps;
352 };
353
354 /* HW State machine Events */
355 enum csio_hw_ev {
356 CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
357 CSIO_HWE_INIT, /* Config done, start Init */
358 CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
359 CSIO_HWE_FATAL, /* Fatal error during initialization */
360 CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
361 CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
362 CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
363 CSIO_HWE_QUIESCED, /* HBA quiesced */
364 CSIO_HWE_HBA_RESET, /* HBA reset requested */
365 CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
366 CSIO_HWE_FW_DLOAD, /* FW download requested */
367 CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
368 CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
369 CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
370 CSIO_HWE_MAX, /* Max HW event */
371 };
372
373 /* hw stats */
374 struct csio_hw_stats {
375 uint32_t n_evt_activeq; /* Number of event in active Q */
376 uint32_t n_evt_freeq; /* Number of event in free Q */
377 uint32_t n_evt_drop; /* Number of event droped */
378 uint32_t n_evt_unexp; /* Number of unexpected events */
379 uint32_t n_pcich_offline;/* Number of pci channel offline */
380 uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
381 uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
382 uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
383 uint32_t n_cpl_unexp; /* Number of unexpected cpl */
384 uint32_t n_mbint_unexp; /* Number of unexpected mbox */
385 /* interrupt */
386 uint32_t n_plint_unexp; /* Number of unexpected PL */
387 /* interrupt */
388 uint32_t n_plint_cnt; /* Number of PL interrupt */
389 uint32_t n_int_stray; /* Number of stray interrupt */
390 uint32_t n_err; /* Number of hw errors */
391 uint32_t n_err_fatal; /* Number of fatal errors */
392 uint32_t n_err_nomem; /* Number of memory alloc failure */
393 uint32_t n_err_io; /* Number of IO failure */
394 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
395 uint64_t n_reset_start; /* Start time after the reset */
396 uint32_t rsvd1;
397 };
398
399 /* Defines for hw->flags */
400 #define CSIO_HWF_MASTER 0x00000001 /* This is the Master
401 * function for the
402 * card.
403 */
404 #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
405 * enable bit set?
406 */
407 #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
408 #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
409 * allocated memory.
410 */
411 #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
412 * allocated in FW.
413 */
414 #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
415 #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
416 * id cached */
417 #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
418 * FW events
419 */
420 #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
421 * params
422 */
423 #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
424 * enabled?
425 */
426 #define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400 /* Is PCIe relaxed
427 * ordering enabled
428 */
429
430 #define csio_is_hw_intr_enabled(__hw) \
431 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
432 #define csio_is_host_intr_enabled(__hw) \
433 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
434 #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
435 #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
436 #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
437 #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
438 #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
439
440 /* Defines for intr_mode */
441 enum csio_intr_mode {
442 CSIO_IM_NONE = 0,
443 CSIO_IM_INTX = 1,
444 CSIO_IM_MSI = 2,
445 CSIO_IM_MSIX = 3,
446 };
447
448 /* Master HW structure: One per function */
449 struct csio_hw {
450 struct csio_sm sm; /* State machine: should
451 * be the 1st member.
452 */
453 spinlock_t lock; /* Lock for hw */
454
455 struct csio_scsim scsim; /* SCSI module*/
456 struct csio_wrm wrm; /* Work request module*/
457 struct pci_dev *pdev; /* PCI device */
458
459 void __iomem *regstart; /* Virtual address of
460 * register map
461 */
462 /* SCSI queue sets */
463 uint32_t num_sqsets; /* Number of SCSI
464 * queue sets */
465 uint32_t num_scsi_msix_cpus; /* Number of CPUs that
466 * will be used
467 * for ingress
468 * processing.
469 */
470
471 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
472 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
473
474 uint32_t evtflag; /* Event flag */
475 uint32_t flags; /* HW flags */
476
477 struct csio_mgmtm mgmtm; /* management module */
478 struct csio_mbm mbm; /* Mailbox module */
479
480 /* Lnodes */
481 uint32_t num_lns; /* Number of lnodes */
482 struct csio_lnode *rln; /* Root lnode */
483 struct list_head sln_head; /* Sibling node list
484 * list
485 */
486 int intr_iq_idx; /* Forward interrupt
487 * queue.
488 */
489 int fwevt_iq_idx; /* FW evt queue */
490 struct work_struct evtq_work; /* Worker thread for
491 * HW events.
492 */
493 struct list_head evt_free_q; /* freelist of evt
494 * elements
495 */
496 struct list_head evt_active_q; /* active evt queue*/
497
498 /* board related info */
499 char name[32];
500 char hw_ver[16];
501 char model_desc[32];
502 char drv_version[32];
503 char fwrev_str[32];
504 uint32_t optrom_ver;
505 uint32_t fwrev;
506 uint32_t tp_vers;
507 char chip_ver;
508 uint16_t chip_id; /* Tells T4/T5 chip */
509 enum csio_dev_state fw_state;
510 struct csio_vpd vpd;
511
512 uint8_t pfn; /* Physical Function
513 * number
514 */
515 uint32_t port_vec; /* Port vector */
516 uint8_t num_pports; /* Number of physical
517 * ports.
518 */
519 uint8_t rst_retries; /* Reset retries */
520 uint8_t cur_evt; /* current s/m evt */
521 uint8_t prev_evt; /* Previous s/m evt */
522 uint32_t dev_num; /* device number */
523 struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
524 struct csio_hw_params params; /* Hw parameters */
525
526 struct dma_pool *scsi_dma_pool; /* DMA pool for SCSI */
527 mempool_t *mb_mempool; /* Mailbox memory pool*/
528 mempool_t *rnode_mempool; /* rnode memory pool */
529
530 /* Interrupt */
531 enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
532 uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
533 * index
534 */
535 uint32_t nondata_intr_idx; /* nondata MSIX/intr
536 * idx
537 */
538
539 uint8_t cfg_neq; /* FW configured no of
540 * egress queues
541 */
542 uint8_t cfg_niq; /* FW configured no of
543 * iq queues.
544 */
545
546 struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
547 struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
548 * Operations
549 */
550
551 /* MSIX vectors */
552 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
553
554 struct dentry *debugfs_root; /* Debug FS */
555 struct csio_hw_stats stats; /* Hw statistics */
556 };
557
558 /* Register access macros */
559 #define csio_reg(_b, _r) ((_b) + (_r))
560
561 #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
562 #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
563 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
564 #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
565
566 #define csio_wr_reg8(_h, _v, _r) writeb((_v), \
567 csio_reg((_h)->regstart, (_r)))
568 #define csio_wr_reg16(_h, _v, _r) writew((_v), \
569 csio_reg((_h)->regstart, (_r)))
570 #define csio_wr_reg32(_h, _v, _r) writel((_v), \
571 csio_reg((_h)->regstart, (_r)))
572 #define csio_wr_reg64(_h, _v, _r) writeq((_v), \
573 csio_reg((_h)->regstart, (_r)))
574
575 void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
576
577 /* Core clocks <==> uSecs */
578 static inline uint32_t
csio_core_ticks_to_us(struct csio_hw * hw,uint32_t ticks)579 csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
580 {
581 /* add Core Clock / 2 to round ticks to nearest uS */
582 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
583 }
584
585 static inline uint32_t
csio_us_to_core_ticks(struct csio_hw * hw,uint32_t us)586 csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
587 {
588 return (us * hw->vpd.cclk) / 1000;
589 }
590
591 /* Easy access macros */
592 #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
593 #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
594 #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
595 #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
596
597 #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
598 #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
599 #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
600
601 #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
602 #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
603 #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
604 #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
605
606 /* Printing/logging */
607 #define CSIO_DEVID(__dev) ((__dev)->dev_num)
608 #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
609 #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
610
611 #define csio_info(__hw, __fmt, ...) \
612 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
613
614 #define csio_fatal(__hw, __fmt, ...) \
615 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
616
617 #define csio_err(__hw, __fmt, ...) \
618 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
619
620 #define csio_warn(__hw, __fmt, ...) \
621 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
622
623 #ifdef __CSIO_DEBUG__
624 #define csio_dbg(__hw, __fmt, ...) \
625 csio_info((__hw), __fmt, ##__VA_ARGS__);
626 #else
627 #define csio_dbg(__hw, __fmt, ...)
628 #endif
629
630 int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
631 int, int, uint32_t *);
632 void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
633 unsigned int, unsigned int);
634 int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
635 void csio_hw_intr_disable(struct csio_hw *);
636 int csio_hw_slow_intr_handler(struct csio_hw *);
637 int csio_handle_intr_status(struct csio_hw *, unsigned int,
638 const struct intr_info *);
639
640 fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps);
641 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
642 fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32);
643 fw_port_cap32_t lstatus_to_fwcap(u32 lstatus);
644
645 int csio_hw_start(struct csio_hw *);
646 int csio_hw_stop(struct csio_hw *);
647 int csio_hw_reset(struct csio_hw *);
648 int csio_is_hw_ready(struct csio_hw *);
649 int csio_is_hw_removing(struct csio_hw *);
650
651 int csio_fwevtq_handler(struct csio_hw *);
652 void csio_evtq_worker(struct work_struct *);
653 int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
654 void csio_evtq_flush(struct csio_hw *hw);
655
656 int csio_request_irqs(struct csio_hw *);
657 void csio_intr_enable(struct csio_hw *);
658 void csio_intr_disable(struct csio_hw *, bool);
659 void csio_hw_fatal_err(struct csio_hw *);
660
661 struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
662 int csio_config_queues(struct csio_hw *);
663
664 int csio_hw_init(struct csio_hw *);
665 void csio_hw_exit(struct csio_hw *);
666 #endif /* ifndef __CSIO_HW_H__ */
667