1 /* $OpenBSD: cz.c,v 1.30 2024/11/05 18:58:59 miod Exp $ */
2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 2000 Zembu Labs, Inc.
6 * All rights reserved.
7 *
8 * Authors: Jason R. Thorpe <thorpej@zembu.com>
9 * Bill Studenmund <wrstuden@zembu.com>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Zembu Labs, Inc.
22 * 4. Neither the name of Zembu Labs nor the names of its employees may
23 * be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS
27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS-
29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Cyclades-Z series multi-port serial adapter driver for NetBSD.
40 *
41 * Some notes:
42 *
43 * - The Cyclades-Z has fully automatic hardware (and software!)
44 * flow control. We only utilize RTS/CTS flow control here,
45 * and it is implemented in a very simplistic manner. This
46 * may be an area of future work.
47 *
48 * - The PLX can map the either the board's RAM or host RAM
49 * into the MIPS's memory window. This would enable us to
50 * use less expensive (for us) memory reads/writes to host
51 * RAM, rather than time-consuming reads/writes to PCI
52 * memory space. However, the PLX can only map a 0-128M
53 * window, so we would have to ensure that the DMA address
54 * of the host RAM fits there. This is kind of a pain,
55 * so we just don't bother right now.
56 *
57 * - In a perfect world, we would use the autoconfiguration
58 * mechanism to attach the TTYs that we find. However,
59 * that leads to somewhat icky looking autoconfiguration
60 * messages (one for every TTY, up to 64 per board!). So
61 * we don't do it that way, but assign minors as if there
62 * were the max of 64 ports per board.
63 *
64 * - We don't bother with PPS support here. There are so many
65 * ports, each with a large amount of buffer space, that the
66 * normal mode of operation is to poll the boards regularly
67 * (generally, every 20ms or so). This makes this driver
68 * unsuitable for PPS, as the latency will be generally too
69 * high.
70 */
71 /*
72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern
73 * for FreeBSD 3.2.
74 */
75
76 #include <sys/param.h>
77 #include <sys/systm.h>
78 #include <sys/proc.h>
79 #include <sys/device.h>
80 #include <sys/malloc.h>
81 #include <sys/tty.h>
82 #include <sys/conf.h>
83 #include <sys/time.h>
84 #include <sys/syslog.h>
85
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pcidevs.h>
89 #include <dev/pci/czreg.h>
90
91 #include <dev/pci/plx9060reg.h>
92 #include <dev/pci/plx9060var.h>
93
94 #include <dev/microcode/cyclades/cyzfirm.h>
95
96 #define CZ_DRIVER_VERSION 0x20000411
97
98 #define CZ_POLL_MS 20
99
100 /* These are the interrupts we always use. */
101 #define CZ_INTERRUPTS \
102 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \
103 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \
104 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \
105 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK)
106
107 /*
108 * cztty_softc:
109 *
110 * Per-channel (TTY) state.
111 */
112 struct cztty_softc {
113 struct cz_softc *sc_parent;
114 struct tty *sc_tty;
115
116 struct timeout sc_diag_to;
117
118 int sc_channel; /* Also used to flag unattached chan */
119 #define CZTTY_CHANNEL_DEAD -1
120
121 bus_space_tag_t sc_chan_st; /* channel space tag */
122 bus_space_handle_t sc_chan_sh; /* channel space handle */
123 bus_space_handle_t sc_buf_sh; /* buffer space handle */
124
125 u_int sc_overflows,
126 sc_parity_errors,
127 sc_framing_errors,
128 sc_errors;
129
130 int sc_swflags;
131
132 u_int32_t sc_rs_control_dtr,
133 sc_chanctl_hw_flow,
134 sc_chanctl_comm_baud,
135 sc_chanctl_rs_control,
136 sc_chanctl_comm_data_l,
137 sc_chanctl_comm_parity;
138 };
139
140 /*
141 * cz_softc:
142 *
143 * Per-board state.
144 */
145 struct cz_softc {
146 struct device cz_dev; /* generic device info */
147 struct plx9060_config cz_plx; /* PLX 9060 config info */
148 bus_space_tag_t cz_win_st; /* window space tag */
149 bus_space_handle_t cz_win_sh; /* window space handle */
150 struct timeout cz_timeout; /* timeout for polling-mode */
151
152 void *cz_ih; /* interrupt handle */
153
154 u_int32_t cz_mailbox0; /* our MAILBOX0 value */
155 int cz_nchannels; /* number of channels */
156 int cz_nopenchan; /* number of open channels */
157 struct cztty_softc *cz_ports; /* our array of ports */
158
159 bus_addr_t cz_fwctl; /* offset of firmware control */
160 };
161
162 int cz_match(struct device *, void *, void *);
163 void cz_attach(struct device *, struct device *, void *);
164 int cz_wait_pci_doorbell(struct cz_softc *, char *);
165
166 const struct cfattach cz_ca = {
167 sizeof(struct cz_softc), cz_match, cz_attach
168 };
169
170 void cz_reset_board(struct cz_softc *);
171 int cz_load_firmware(struct cz_softc *);
172
173 int cz_intr(void *);
174 void cz_poll(void *);
175 int cztty_transmit(struct cztty_softc *, struct tty *);
176 int cztty_receive(struct cztty_softc *, struct tty *);
177
178 struct cztty_softc * cztty_getttysoftc(dev_t dev);
179 int cztty_findmajor(void);
180 int cztty_major;
181 int cztty_attached_ttys;
182
183 cdev_decl(cztty);
184
185 void czttystart(struct tty *tp);
186 int czttyparam(struct tty *tp, struct termios *t);
187 void cztty_shutdown(struct cztty_softc *sc);
188 void cztty_modem(struct cztty_softc *sc, int onoff);
189 void cztty_break(struct cztty_softc *sc, int onoff);
190 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits);
191 int cztty_to_tiocm(struct cztty_softc *sc);
192 void cztty_diag(void *arg);
193
194 struct cfdriver cz_cd = {
195 NULL, "cz", DV_TTY
196 };
197
198 /*
199 * Macros to read and write the PLX.
200 */
201 #define CZ_PLX_READ(cz, reg) \
202 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg))
203 #define CZ_PLX_WRITE(cz, reg, val) \
204 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \
205 (reg), (val))
206
207 /*
208 * Macros to read and write the FPGA. We must already be in the FPGA
209 * window for this.
210 */
211 #define CZ_FPGA_READ(cz, reg) \
212 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg))
213 #define CZ_FPGA_WRITE(cz, reg, val) \
214 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))
215
216 /*
217 * Macros to read and write the firmware control structures in board RAM.
218 */
219 #define CZ_FWCTL_READ(cz, off) \
220 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \
221 (cz)->cz_fwctl + (off))
222
223 #define CZ_FWCTL_WRITE(cz, off, val) \
224 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \
225 (cz)->cz_fwctl + (off), (val))
226
227 /*
228 * Convenience macros for cztty routines. PLX window MUST be to RAM.
229 */
230 #define CZTTY_CHAN_READ(sc, off) \
231 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off))
232
233 #define CZTTY_CHAN_WRITE(sc, off, val) \
234 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \
235 (off), (val))
236
237 #define CZTTY_BUF_READ(sc, off) \
238 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off))
239
240 #define CZTTY_BUF_WRITE(sc, off, val) \
241 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \
242 (off), (val))
243
244 /*
245 * Convenience macros.
246 */
247 #define CZ_WIN_RAM(cz) \
248 do { \
249 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \
250 delay(100); \
251 } while (0)
252
253 #define CZ_WIN_FPGA(cz) \
254 do { \
255 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \
256 delay(100); \
257 } while (0)
258
259 /*****************************************************************************
260 * Cyclades-Z controller code starts here...
261 *****************************************************************************/
262
263 /*
264 * cz_match:
265 *
266 * Determine if the given PCI device is a Cyclades-Z board.
267 */
268 int
cz_match(struct device * parent,void * match,void * aux)269 cz_match(struct device *parent, void *match, void *aux)
270 {
271 struct pci_attach_args *pa = aux;
272
273 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES &&
274 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CYCLADES_CYCLOMZ_2)
275 return (1);
276 return (0);
277 }
278
279 /*
280 * cz_attach:
281 *
282 * A Cyclades-Z board was found; attach it.
283 */
284 void
cz_attach(struct device * parent,struct device * self,void * aux)285 cz_attach(struct device *parent, struct device *self, void *aux)
286 {
287 struct cz_softc *cz = (void *) self;
288 struct pci_attach_args *pa = aux;
289 pci_chipset_tag_t pc = pa->pa_pc;
290 pci_intr_handle_t ih;
291 const char *intrstr = NULL;
292 struct cztty_softc *sc;
293 struct tty *tp;
294 int i;
295
296 cz->cz_plx.plx_pc = pa->pa_pc;
297 cz->cz_plx.plx_tag = pa->pa_tag;
298
299 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR,
300 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
301 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) {
302 printf(": unable to map PLX registers\n");
303 return;
304 }
305 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0,
306 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
307 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) {
308 printf(": unable to map device window\n");
309 return;
310 }
311
312 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0);
313 cz->cz_nopenchan = 0;
314
315 /*
316 * Make sure that the board is completely stopped.
317 */
318 CZ_WIN_FPGA(cz);
319 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0);
320
321 /*
322 * Load the board's firmware.
323 */
324 if (cz_load_firmware(cz) != 0)
325 return;
326
327 /*
328 * Now that we're ready to roll, map and establish the interrupt
329 * handler.
330 */
331 if (pci_intr_map(pa, &ih) != 0) {
332 /*
333 * The common case is for Cyclades-Z boards to run
334 * in polling mode, and thus not have an interrupt
335 * mapped for them. Don't bother reporting that
336 * the interrupt is not mappable, since this isn't
337 * really an error.
338 */
339 cz->cz_ih = NULL;
340 goto polling_mode;
341 } else {
342 intrstr = pci_intr_string(pa->pa_pc, ih);
343 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY,
344 cz_intr, cz, cz->cz_dev.dv_xname);
345 }
346 if (cz->cz_ih == NULL) {
347 printf(": unable to establish interrupt");
348 if (intrstr != NULL)
349 printf(" at %s", intrstr);
350 printf("\n");
351 /* We will fall-back on polling mode. */
352 } else
353 printf(": %s\n", intrstr);
354
355 polling_mode:
356 if (cz->cz_ih == NULL) {
357 timeout_set(&cz->cz_timeout, cz_poll, cz);
358 printf("%s: polling mode, %d ms interval\n",
359 cz->cz_dev.dv_xname, CZ_POLL_MS);
360 }
361
362 if (cztty_major == 0)
363 cztty_major = cztty_findmajor();
364 /*
365 * Allocate sufficient pointers for the children and
366 * attach them. Set all ports to a reasonable initial
367 * configuration while we're at it:
368 *
369 * disabled
370 * 8N1
371 * default baud rate
372 * hardware flow control.
373 */
374 CZ_WIN_RAM(cz);
375
376 if (cz->cz_nchannels == 0) {
377 /* No channels? No more work to do! */
378 return;
379 }
380
381 cz->cz_ports = mallocarray(cz->cz_nchannels,
382 sizeof(struct cztty_softc), M_DEVBUF, M_WAITOK | M_ZERO);
383 cztty_attached_ttys += cz->cz_nchannels;
384
385 for (i = 0; i < cz->cz_nchannels; i++) {
386 sc = &cz->cz_ports[i];
387
388 sc->sc_channel = i;
389 sc->sc_chan_st = cz->cz_win_st;
390 sc->sc_parent = cz;
391
392 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh,
393 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0),
394 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) {
395 printf("%s: unable to subregion channel %d control\n",
396 cz->cz_dev.dv_xname, i);
397 sc->sc_channel = CZTTY_CHANNEL_DEAD;
398 continue;
399 }
400 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh,
401 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0),
402 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) {
403 printf("%s: unable to subregion channel %d buffer\n",
404 cz->cz_dev.dv_xname, i);
405 sc->sc_channel = CZTTY_CHANNEL_DEAD;
406 continue;
407 }
408
409 timeout_set(&sc->sc_diag_to, cztty_diag, sc);
410
411 tp = ttymalloc(0);
412 tp->t_dev = makedev(cztty_major,
413 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i);
414 tp->t_oproc = czttystart;
415 tp->t_param = czttyparam;
416
417 sc->sc_tty = tp;
418
419 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE);
420 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS);
421 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0);
422 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11);
423 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13);
424 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED);
425 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE);
426 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP);
427 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0);
428 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS);
429 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0);
430 }
431 }
432
433 /*
434 * cz_reset_board:
435 *
436 * Reset the board via the PLX.
437 */
438 void
cz_reset_board(struct cz_softc * cz)439 cz_reset_board(struct cz_softc *cz)
440 {
441 u_int32_t reg;
442
443 reg = CZ_PLX_READ(cz, PLX_CONTROL);
444 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR);
445 delay(1000);
446
447 CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
448 delay(1000);
449
450 /* Now reload the PLX from its EEPROM. */
451 reg = CZ_PLX_READ(cz, PLX_CONTROL);
452 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG);
453 delay(1000);
454 CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
455 }
456
457 /*
458 * cz_load_firmware:
459 *
460 * Load the ZFIRM firmware into the board's RAM and start it
461 * running.
462 */
463 int
cz_load_firmware(struct cz_softc * cz)464 cz_load_firmware(struct cz_softc *cz)
465 {
466 struct zfirm_header *zfh;
467 struct zfirm_config *zfc;
468 struct zfirm_block *zfb, *zblocks;
469 const u_int8_t *cp;
470 const char *board;
471 u_int32_t fid;
472 int i, j, nconfigs, nblocks, nbytes;
473
474 zfh = (struct zfirm_header *) cycladesz_firmware;
475
476 /* Find the config header. */
477 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) {
478 printf("%s: bad ZFIRM config offset: 0x%x\n",
479 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff));
480 return (EIO);
481 }
482 zfc = (struct zfirm_config *)(cycladesz_firmware +
483 letoh32(zfh->zfh_configoff));
484 nconfigs = letoh32(zfh->zfh_nconfig);
485
486 /* Locate the correct configuration for our board. */
487 for (i = 0; i < nconfigs; i++, zfc++) {
488 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 &&
489 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL)
490 break;
491 }
492 if (i == nconfigs) {
493 printf("%s: unable to locate config header\n",
494 cz->cz_dev.dv_xname);
495 return (EIO);
496 }
497
498 nblocks = letoh32(zfc->zfc_nblocks);
499 zblocks = (struct zfirm_block *)(cycladesz_firmware +
500 letoh32(zfh->zfh_blockoff));
501
502 /*
503 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if
504 * necessary.
505 */
506 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1
507 #if 0
508 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0)
509 #endif
510 ) {
511 #ifdef CZ_DEBUG
512 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname);
513 #endif
514 CZ_WIN_FPGA(cz);
515 for (i = 0; i < nblocks; i++) {
516 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */
517 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])];
518 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) {
519 nbytes = letoh32(zfb->zfb_size);
520 cp = &cycladesz_firmware[
521 letoh32(zfb->zfb_fileoff)];
522 for (j = 0; j < nbytes; j++, cp++) {
523 bus_space_write_1(cz->cz_win_st,
524 cz->cz_win_sh, 0, *cp);
525 /* FPGA needs 30-100us to settle. */
526 delay(10);
527 }
528 }
529 }
530 #ifdef CZ_DEBUG
531 printf("done\n");
532 #endif
533 }
534
535 /* Now load the firmware. */
536 CZ_WIN_RAM(cz);
537
538 for (i = 0; i < nblocks; i++) {
539 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */
540 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])];
541 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) {
542 const u_int32_t *lp;
543 u_int32_t ro = letoh32(zfb->zfb_ramoff);
544 nbytes = letoh32(zfb->zfb_size);
545 lp = (const u_int32_t *)
546 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)];
547 for (j = 0; j < nbytes; j += 4, lp++) {
548 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh,
549 ro + j, letoh32(*lp));
550 delay(10);
551 }
552 }
553 }
554
555 /* Now restart the MIPS. */
556 CZ_WIN_FPGA(cz);
557 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0);
558
559 /* Wait for the MIPS to start, then report the results. */
560 CZ_WIN_RAM(cz);
561
562 #ifdef CZ_DEBUG
563 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname);
564 #endif
565 for (i = 0; i < 100; i++) {
566 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh,
567 ZFIRM_SIG_OFF);
568 if (fid == ZFIRM_SIG) {
569 /* MIPS has booted. */
570 break;
571 } else if (fid == ZFIRM_HLT) {
572 /*
573 * The MIPS has halted, usually due to a power
574 * shortage on the expansion module.
575 */
576 printf("%s: MIPS halted; possible power supply "
577 "problem\n", cz->cz_dev.dv_xname);
578 return (EIO);
579 } else {
580 #ifdef CZ_DEBUG
581 if ((i % 8) == 0)
582 printf(".");
583 #endif
584 delay(250000);
585 }
586 }
587 #ifdef CZ_DEBUG
588 printf("\n");
589 #endif
590 if (i == 100) {
591 CZ_WIN_FPGA(cz);
592 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n",
593 cz->cz_dev.dv_xname, ZFIRM_SIG, fid);
594 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n",
595 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID),
596 CZ_FPGA_READ(cz, FPGA_VERSION));
597 return (EIO);
598 }
599
600 /*
601 * Locate the firmware control structures.
602 */
603 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh,
604 ZFIRM_CTRLADDR_OFF);
605 #ifdef CZ_DEBUG
606 printf("%s: FWCTL structure at offset 0x%08lx\n",
607 cz->cz_dev.dv_xname, cz->cz_fwctl);
608 #endif
609
610 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD);
611 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION);
612
613 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL);
614
615 switch (cz->cz_mailbox0) {
616 case MAILBOX0_8Zo_V1:
617 board = "Cyclades-8Zo ver. 1";
618 break;
619
620 case MAILBOX0_8Zo_V2:
621 board = "Cyclades-8Zo ver. 2";
622 break;
623
624 case MAILBOX0_Ze_V1:
625 board = "Cyclades-Ze";
626 break;
627
628 default:
629 board = "unknown Cyclades Z-series";
630 break;
631 }
632
633 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION);
634 printf("%s: %s, ", cz->cz_dev.dv_xname, board);
635 if (cz->cz_nchannels == 0)
636 printf("no channels attached, ");
637 else
638 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ",
639 cz->cz_nchannels, cztty_attached_ttys,
640 cztty_attached_ttys + (cz->cz_nchannels - 1));
641 printf("firmware %x.%x.%x\n",
642 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf);
643
644 return (0);
645 }
646
647 /*
648 * cz_poll:
649 *
650 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS
651 * ms.
652 */
653 void
cz_poll(void * arg)654 cz_poll(void *arg)
655 {
656 int s = spltty();
657 struct cz_softc *cz = arg;
658
659 cz_intr(cz);
660 timeout_add_msec(&cz->cz_timeout, CZ_POLL_MS);
661
662 splx(s);
663 }
664
665 /*
666 * cz_intr:
667 *
668 * Interrupt service routine.
669 *
670 * We either are receiving an interrupt directly from the board, or we are
671 * in polling mode and it's time to poll.
672 */
673 int
cz_intr(void * arg)674 cz_intr(void *arg)
675 {
676 int rval = 0;
677 u_int command, channel, param;
678 struct cz_softc *cz = arg;
679 struct cztty_softc *sc;
680 struct tty *tp;
681
682 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) {
683 rval = 1;
684 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL);
685 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM);
686
687 /* now clear this interrupt, possibly enabling another */
688 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command);
689
690 if (cz->cz_ports == NULL) {
691 #ifdef CZ_DEBUG
692 printf("%s: interrupt on channel %d, but no channels\n",
693 cz->cz_dev.dv_xname, channel);
694 #endif
695 continue;
696 }
697
698 sc = &cz->cz_ports[channel];
699
700 if (sc->sc_channel == CZTTY_CHANNEL_DEAD)
701 break;
702
703 tp = sc->sc_tty;
704
705 switch (command) {
706 case C_CM_TXFEMPTY: /* transmit cases */
707 case C_CM_TXBEMPTY:
708 case C_CM_TXLOWWM:
709 case C_CM_INTBACK:
710 if (!ISSET(tp->t_state, TS_ISOPEN)) {
711 #ifdef CZ_DEBUG
712 printf("%s: tx intr on closed channel %d\n",
713 cz->cz_dev.dv_xname, channel);
714 #endif
715 break;
716 }
717
718 if (cztty_transmit(sc, tp)) {
719 /*
720 * Do wakeup stuff here.
721 */
722 ttwakeup(tp);
723 wakeup(tp);
724 }
725 break;
726
727 case C_CM_RXNNDT: /* receive cases */
728 case C_CM_RXHIWM:
729 case C_CM_INTBACK2: /* from restart ?? */
730 #if 0
731 case C_CM_ICHAR:
732 #endif
733 if (!ISSET(tp->t_state, TS_ISOPEN)) {
734 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET,
735 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT));
736 break;
737 }
738
739 if (cztty_receive(sc, tp)) {
740 /*
741 * Do wakeup stuff here.
742 */
743 ttwakeup(tp);
744 wakeup(tp);
745 }
746 break;
747
748 case C_CM_MDCD:
749 if (!ISSET(tp->t_state, TS_ISOPEN))
750 break;
751
752 (void) (*linesw[tp->t_line].l_modem)(tp,
753 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc,
754 CHNCTL_RS_STATUS)));
755 break;
756
757 case C_CM_MDSR:
758 case C_CM_MRI:
759 case C_CM_MCTS:
760 case C_CM_MRTS:
761 break;
762
763 case C_CM_IOCTLW:
764 break;
765
766 case C_CM_PR_ERROR:
767 sc->sc_parity_errors++;
768 goto error_common;
769
770 case C_CM_FR_ERROR:
771 sc->sc_framing_errors++;
772 goto error_common;
773
774 case C_CM_OVR_ERROR:
775 sc->sc_overflows++;
776 error_common:
777 if (sc->sc_errors++ == 0)
778 timeout_add_sec(&sc->sc_diag_to, 60);
779 break;
780
781 case C_CM_RXBRK:
782 if (!ISSET(tp->t_state, TS_ISOPEN))
783 break;
784
785 /*
786 * A break is a \000 character with TTY_FE error
787 * flags set. So TTY_FE by itself works.
788 */
789 (*linesw[tp->t_line].l_rint)(TTY_FE, tp);
790 ttwakeup(tp);
791 wakeup(tp);
792 break;
793
794 default:
795 #ifdef CZ_DEBUG
796 printf("%s: channel %d: Unknown interrupt 0x%x\n",
797 cz->cz_dev.dv_xname, sc->sc_channel, command);
798 #endif
799 break;
800 }
801 }
802
803 return (rval);
804 }
805
806 /*
807 * cz_wait_pci_doorbell:
808 *
809 * Wait for the pci doorbell to be clear - wait for pending
810 * activity to drain.
811 */
812 int
cz_wait_pci_doorbell(struct cz_softc * cz,char * wstring)813 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring)
814 {
815 int error;
816
817 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) {
818 error = tsleep_nsec(cz, TTIPRI | PCATCH, wstring,
819 MSEC_TO_NSEC(10));
820 if ((error != 0) && (error != EWOULDBLOCK))
821 return (error);
822 }
823 return (0);
824 }
825
826 /*****************************************************************************
827 * Cyclades-Z TTY code starts here...
828 *****************************************************************************/
829
830 #define CZTTYDIALOUT_MASK 0x80
831
832 #define CZTTY_CZ(sc) ((sc)->sc_parent)
833
834 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev)
835
836 struct cztty_softc *
cztty_getttysoftc(dev_t dev)837 cztty_getttysoftc(dev_t dev)
838 {
839 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK;
840 struct cz_softc *cz;
841
842 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) {
843 k = j;
844 cz = (struct cz_softc *)device_lookup(&cz_cd, i);
845 if (cz == NULL)
846 continue;
847 if (cz->cz_ports == NULL)
848 continue;
849 j += cz->cz_nchannels;
850 if (j > u)
851 break;
852 }
853
854 if (i >= cz_cd.cd_ndevs)
855 return (NULL);
856 else
857 return (&cz->cz_ports[u - k]);
858 }
859
860 int
cztty_findmajor(void)861 cztty_findmajor(void)
862 {
863 int maj;
864
865 for (maj = 0; maj < nchrdev; maj++) {
866 if (cdevsw[maj].d_open == czttyopen)
867 break;
868 }
869
870 return (maj == nchrdev) ? 0 : maj;
871 }
872
873 /*
874 * czttytty:
875 *
876 * Return a pointer to our tty.
877 */
878 struct tty *
czttytty(dev_t dev)879 czttytty(dev_t dev)
880 {
881 struct cztty_softc *sc = CZTTY_SOFTC(dev);
882
883 #ifdef DIAGNOSTIC
884 if (sc == NULL)
885 panic("czttytty");
886 #endif
887
888 return (sc->sc_tty);
889 }
890
891 /*
892 * cztty_shutdown:
893 *
894 * Shut down a port.
895 */
896 void
cztty_shutdown(struct cztty_softc * sc)897 cztty_shutdown(struct cztty_softc *sc)
898 {
899 struct cz_softc *cz = CZTTY_CZ(sc);
900 struct tty *tp = sc->sc_tty;
901 int s;
902
903 s = spltty();
904
905 /* Clear any break condition set with TIOCSBRK. */
906 cztty_break(sc, 0);
907
908 /*
909 * Hang up if necessary. Wait a bit, so the other side has time to
910 * notice even if we immediately open the port again.
911 */
912 if (ISSET(tp->t_cflag, HUPCL)) {
913 cztty_modem(sc, 0);
914 tsleep_nsec(tp, TTIPRI, ttclos, SEC_TO_NSEC(1));
915 }
916
917 /* Disable the channel. */
918 cz_wait_pci_doorbell(cz, "czdis");
919 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE);
920 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
921 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL);
922
923 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) {
924 #ifdef CZ_DEBUG
925 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname);
926 #endif
927 timeout_del(&cz->cz_timeout);
928 }
929
930 splx(s);
931 }
932
933 /*
934 * czttyopen:
935 *
936 * Open a Cyclades-Z serial port.
937 */
938 int
czttyopen(dev_t dev,int flags,int mode,struct proc * p)939 czttyopen(dev_t dev, int flags, int mode, struct proc *p)
940 {
941 struct cztty_softc *sc = CZTTY_SOFTC(dev);
942 struct cz_softc *cz;
943 struct tty *tp;
944 int s, error;
945
946 if (sc == NULL)
947 return (ENXIO);
948
949 if (sc->sc_channel == CZTTY_CHANNEL_DEAD)
950 return (ENXIO);
951
952 cz = CZTTY_CZ(sc);
953 tp = sc->sc_tty;
954
955 if (ISSET(tp->t_state, TS_ISOPEN) &&
956 ISSET(tp->t_state, TS_XCLUDE) &&
957 suser(p) != 0)
958 return (EBUSY);
959
960 s = spltty();
961
962 /*
963 * Do the following iff this is a first open.
964 */
965 if (!ISSET(tp->t_state, TS_ISOPEN)) {
966 struct termios t;
967
968 tp->t_dev = dev;
969
970 /* If we're turning things on, enable interrupts */
971 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) {
972 #ifdef CZ_DEBUG
973 printf("%s: Enabling polling.\n",
974 cz->cz_dev.dv_xname);
975 #endif
976 timeout_add_msec(&cz->cz_timeout, CZ_POLL_MS);
977 }
978
979 /*
980 * Enable the channel. Don't actually ring the
981 * doorbell here; czttyparam() will do it for us.
982 */
983 cz_wait_pci_doorbell(cz, "czopen");
984
985 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE);
986
987 /*
988 * Initialize the termios status to the defaults. Add in the
989 * sticky bits from TIOCSFLAGS.
990 */
991 t.c_ispeed = 0;
992 t.c_ospeed = TTYDEF_SPEED;
993 t.c_cflag = TTYDEF_CFLAG;
994 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
995 SET(t.c_cflag, CLOCAL);
996 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
997 SET(t.c_cflag, CRTSCTS);
998
999 /*
1000 * Reset the input and output rings. Do this before
1001 * we call czttyparam(), as that function enables
1002 * the channel.
1003 */
1004 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET,
1005 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT));
1006 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT,
1007 CZTTY_BUF_READ(sc, BUFCTL_TX_GET));
1008
1009 /* Make sure czttyparam() will see changes. */
1010 tp->t_ospeed = 0;
1011 (void) czttyparam(tp, &t);
1012 tp->t_iflag = TTYDEF_IFLAG;
1013 tp->t_oflag = TTYDEF_OFLAG;
1014 tp->t_lflag = TTYDEF_LFLAG;
1015 ttychars(tp);
1016 ttsetwater(tp);
1017
1018 /*
1019 * Turn on DTR. We must always do this, even if carrier is not
1020 * present, because otherwise we'd have to use TIOCSDTR
1021 * immediately after setting CLOCAL, which applications do not
1022 * expect. We always assert DTR while the device is open
1023 * unless explicitly requested to deassert it.
1024 */
1025 cztty_modem(sc, 1);
1026 }
1027
1028 splx(s);
1029
1030 error = (*linesw[tp->t_line].l_open)(dev, tp, p);
1031 if (error)
1032 goto bad;
1033
1034 return (0);
1035
1036 bad:
1037 if (!ISSET(tp->t_state, TS_ISOPEN)) {
1038 /*
1039 * We failed to open the device, and nobody else had it opened.
1040 * Clean up the state as appropriate.
1041 */
1042 cztty_shutdown(sc);
1043 }
1044
1045 return (error);
1046 }
1047
1048 /*
1049 * czttyclose:
1050 *
1051 * Close a Cyclades-Z serial port.
1052 */
1053 int
czttyclose(dev_t dev,int flags,int mode,struct proc * p)1054 czttyclose(dev_t dev, int flags, int mode, struct proc *p)
1055 {
1056 struct cztty_softc *sc = CZTTY_SOFTC(dev);
1057 struct tty *tp = sc->sc_tty;
1058
1059 /* XXX This is for cons.c. */
1060 if (!ISSET(tp->t_state, TS_ISOPEN))
1061 return (0);
1062
1063 (*linesw[tp->t_line].l_close)(tp, flags, p);
1064 ttyclose(tp);
1065
1066 if (!ISSET(tp->t_state, TS_ISOPEN)) {
1067 /*
1068 * Although we got a last close, the device may still be in
1069 * use; e.g. if this was the dialout node, and there are still
1070 * processes waiting for carrier on the non-dialout node.
1071 */
1072 cztty_shutdown(sc);
1073 }
1074
1075 return (0);
1076 }
1077
1078 /*
1079 * czttyread:
1080 *
1081 * Read from a Cyclades-Z serial port.
1082 */
1083 int
czttyread(dev_t dev,struct uio * uio,int flags)1084 czttyread(dev_t dev, struct uio *uio, int flags)
1085 {
1086 struct cztty_softc *sc = CZTTY_SOFTC(dev);
1087 struct tty *tp = sc->sc_tty;
1088
1089 return ((*linesw[tp->t_line].l_read)(tp, uio, flags));
1090 }
1091
1092 /*
1093 * czttywrite:
1094 *
1095 * Write to a Cyclades-Z serial port.
1096 */
1097 int
czttywrite(dev_t dev,struct uio * uio,int flags)1098 czttywrite(dev_t dev, struct uio *uio, int flags)
1099 {
1100 struct cztty_softc *sc = CZTTY_SOFTC(dev);
1101 struct tty *tp = sc->sc_tty;
1102
1103 return ((*linesw[tp->t_line].l_write)(tp, uio, flags));
1104 }
1105
1106 /*
1107 * czttyioctl:
1108 *
1109 * Perform a control operation on a Cyclades-Z serial port.
1110 */
1111 int
czttyioctl(dev_t dev,u_long cmd,caddr_t data,int flag,struct proc * p)1112 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
1113 {
1114 struct cztty_softc *sc = CZTTY_SOFTC(dev);
1115 struct tty *tp = sc->sc_tty;
1116 int s, error;
1117
1118 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1119 if (error >= 0)
1120 return (error);
1121
1122 error = ttioctl(tp, cmd, data, flag, p);
1123 if (error >= 0)
1124 return (error);
1125
1126 error = 0;
1127
1128 s = spltty();
1129
1130 switch (cmd) {
1131 case TIOCSBRK:
1132 cztty_break(sc, 1);
1133 break;
1134
1135 case TIOCCBRK:
1136 cztty_break(sc, 0);
1137 break;
1138
1139 case TIOCGFLAGS:
1140 *(int *)data = sc->sc_swflags;
1141 break;
1142
1143 case TIOCSFLAGS:
1144 error = suser(p);
1145 if (error)
1146 break;
1147 sc->sc_swflags = *(int *)data;
1148 break;
1149
1150 case TIOCSDTR:
1151 cztty_modem(sc, 1);
1152 break;
1153
1154 case TIOCCDTR:
1155 cztty_modem(sc, 0);
1156 break;
1157
1158 case TIOCMSET:
1159 case TIOCMBIS:
1160 case TIOCMBIC:
1161 tiocm_to_cztty(sc, cmd, *(int *)data);
1162 break;
1163
1164 case TIOCMGET:
1165 *(int *)data = cztty_to_tiocm(sc);
1166 break;
1167
1168 default:
1169 error = ENOTTY;
1170 break;
1171 }
1172
1173 splx(s);
1174
1175 return (error);
1176 }
1177
1178 /*
1179 * cztty_break:
1180 *
1181 * Set or clear BREAK on a port.
1182 */
1183 void
cztty_break(struct cztty_softc * sc,int onoff)1184 cztty_break(struct cztty_softc *sc, int onoff)
1185 {
1186 struct cz_softc *cz = CZTTY_CZ(sc);
1187
1188 cz_wait_pci_doorbell(cz, "czbreak");
1189
1190 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
1191 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL,
1192 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK);
1193 }
1194
1195 /*
1196 * cztty_modem:
1197 *
1198 * Set or clear DTR on a port.
1199 */
1200 void
cztty_modem(struct cztty_softc * sc,int onoff)1201 cztty_modem(struct cztty_softc *sc, int onoff)
1202 {
1203 struct cz_softc *cz = CZTTY_CZ(sc);
1204
1205 if (sc->sc_rs_control_dtr == 0)
1206 return;
1207
1208 cz_wait_pci_doorbell(cz, "czmod");
1209
1210 if (onoff)
1211 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr;
1212 else
1213 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr;
1214 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control);
1215
1216 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
1217 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
1218 }
1219
1220 /*
1221 * tiocm_to_cztty:
1222 *
1223 * Process TIOCM* ioctls.
1224 */
1225 void
tiocm_to_cztty(struct cztty_softc * sc,u_long how,int ttybits)1226 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits)
1227 {
1228 struct cz_softc *cz = CZTTY_CZ(sc);
1229 u_int32_t czttybits;
1230
1231 czttybits = 0;
1232 if (ISSET(ttybits, TIOCM_DTR))
1233 SET(czttybits, C_RS_DTR);
1234 if (ISSET(ttybits, TIOCM_RTS))
1235 SET(czttybits, C_RS_RTS);
1236
1237 cz_wait_pci_doorbell(cz, "cztiocm");
1238
1239 switch (how) {
1240 case TIOCMBIC:
1241 CLR(sc->sc_chanctl_rs_control, czttybits);
1242 break;
1243
1244 case TIOCMBIS:
1245 SET(sc->sc_chanctl_rs_control, czttybits);
1246 break;
1247
1248 case TIOCMSET:
1249 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS);
1250 SET(sc->sc_chanctl_rs_control, czttybits);
1251 break;
1252 }
1253
1254 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control);
1255
1256 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
1257 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
1258 }
1259
1260 /*
1261 * cztty_to_tiocm:
1262 *
1263 * Process the TIOCMGET ioctl.
1264 */
1265 int
cztty_to_tiocm(struct cztty_softc * sc)1266 cztty_to_tiocm(struct cztty_softc *sc)
1267 {
1268 struct cz_softc *cz = CZTTY_CZ(sc);
1269 u_int32_t rs_status, op_mode;
1270 int ttybits = 0;
1271
1272 cz_wait_pci_doorbell(cz, "cztty");
1273
1274 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS);
1275 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE);
1276
1277 if (ISSET(rs_status, C_RS_RTS))
1278 SET(ttybits, TIOCM_RTS);
1279 if (ISSET(rs_status, C_RS_CTS))
1280 SET(ttybits, TIOCM_CTS);
1281 if (ISSET(rs_status, C_RS_DCD))
1282 SET(ttybits, TIOCM_CAR);
1283 if (ISSET(rs_status, C_RS_DTR))
1284 SET(ttybits, TIOCM_DTR);
1285 if (ISSET(rs_status, C_RS_RI))
1286 SET(ttybits, TIOCM_RNG);
1287 if (ISSET(rs_status, C_RS_DSR))
1288 SET(ttybits, TIOCM_DSR);
1289
1290 if (ISSET(op_mode, C_CH_ENABLE))
1291 SET(ttybits, TIOCM_LE);
1292
1293 return (ttybits);
1294 }
1295
1296 /*
1297 * czttyparam:
1298 *
1299 * Set Cyclades-Z serial port parameters from termios.
1300 *
1301 * XXX Should just copy the whole termios after making
1302 * XXX sure all the changes could be done.
1303 */
1304 int
czttyparam(struct tty * tp,struct termios * t)1305 czttyparam(struct tty *tp, struct termios *t)
1306 {
1307 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev);
1308 struct cz_softc *cz = CZTTY_CZ(sc);
1309 u_int32_t rs_status;
1310 int ospeed, cflag;
1311
1312 ospeed = t->c_ospeed;
1313 cflag = t->c_cflag;
1314
1315 /* Check requested parameters. */
1316 if (ospeed < 0)
1317 return (EINVAL);
1318 if (t->c_ispeed && t->c_ispeed != ospeed)
1319 return (EINVAL);
1320
1321 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) {
1322 SET(cflag, CLOCAL);
1323 CLR(cflag, HUPCL);
1324 }
1325
1326 /*
1327 * If there were no changes, don't do anything. This avoids dropping
1328 * input and improves performance when all we did was frob things like
1329 * VMIN and VTIME.
1330 */
1331 if (tp->t_ospeed == ospeed &&
1332 tp->t_cflag == cflag)
1333 return (0);
1334
1335 /* Data bits. */
1336 sc->sc_chanctl_comm_data_l = 0;
1337 switch (t->c_cflag & CSIZE) {
1338 case CS5:
1339 sc->sc_chanctl_comm_data_l |= C_DL_CS5;
1340 break;
1341
1342 case CS6:
1343 sc->sc_chanctl_comm_data_l |= C_DL_CS6;
1344 break;
1345
1346 case CS7:
1347 sc->sc_chanctl_comm_data_l |= C_DL_CS7;
1348 break;
1349
1350 case CS8:
1351 sc->sc_chanctl_comm_data_l |= C_DL_CS8;
1352 break;
1353 }
1354
1355 /* Stop bits. */
1356 if (t->c_cflag & CSTOPB) {
1357 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5)
1358 sc->sc_chanctl_comm_data_l |= C_DL_15STOP;
1359 else
1360 sc->sc_chanctl_comm_data_l |= C_DL_2STOP;
1361 } else
1362 sc->sc_chanctl_comm_data_l |= C_DL_1STOP;
1363
1364 /* Parity. */
1365 if (t->c_cflag & PARENB) {
1366 if (t->c_cflag & PARODD)
1367 sc->sc_chanctl_comm_parity = C_PR_ODD;
1368 else
1369 sc->sc_chanctl_comm_parity = C_PR_EVEN;
1370 } else
1371 sc->sc_chanctl_comm_parity = C_PR_NONE;
1372
1373 /*
1374 * Initialize flow control pins depending on the current flow control
1375 * mode.
1376 */
1377 if (ISSET(t->c_cflag, CRTSCTS)) {
1378 sc->sc_rs_control_dtr = C_RS_DTR;
1379 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS;
1380 } else if (ISSET(t->c_cflag, MDMBUF)) {
1381 sc->sc_rs_control_dtr = 0;
1382 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR;
1383 } else {
1384 /*
1385 * If no flow control, then always set RTS. This will make
1386 * the other side happy if it mistakenly thinks we're doing
1387 * RTS/CTS flow control.
1388 */
1389 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS;
1390 sc->sc_chanctl_hw_flow = 0;
1391 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR))
1392 SET(sc->sc_chanctl_rs_control, C_RS_RTS);
1393 else
1394 CLR(sc->sc_chanctl_rs_control, C_RS_RTS);
1395 }
1396
1397 /* Baud rate. */
1398 sc->sc_chanctl_comm_baud = ospeed;
1399
1400 /* Copy to tty. */
1401 tp->t_ispeed = 0;
1402 tp->t_ospeed = t->c_ospeed;
1403 tp->t_cflag = t->c_cflag;
1404
1405 /*
1406 * Now load the channel control structure.
1407 */
1408
1409 cz_wait_pci_doorbell(cz, "czparam");
1410
1411 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud);
1412 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l);
1413 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity);
1414 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow);
1415 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control);
1416
1417 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
1418 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW);
1419
1420 cz_wait_pci_doorbell(cz, "czparam");
1421
1422 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
1423 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
1424
1425 cz_wait_pci_doorbell(cz, "czparam");
1426
1427 /*
1428 * Update the tty layer's idea of the carrier bit, in case we changed
1429 * CLOCAL. We don't hang up here; we only do that by explicit
1430 * request.
1431 */
1432 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS);
1433 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD));
1434
1435 return (0);
1436 }
1437
1438 /*
1439 * czttystart:
1440 *
1441 * Start or restart transmission.
1442 */
1443 void
czttystart(struct tty * tp)1444 czttystart(struct tty *tp)
1445 {
1446 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev);
1447 int s;
1448
1449 s = spltty();
1450 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1451 goto out;
1452
1453 ttwakeupwr(tp);
1454 if (tp->t_outq.c_cc == 0)
1455 goto out;
1456
1457 cztty_transmit(sc, tp);
1458 out:
1459 splx(s);
1460 }
1461
1462 /*
1463 * czttystop:
1464 *
1465 * Stop output, e.g., for ^S or output flush.
1466 */
1467 int
czttystop(struct tty * tp,int flag)1468 czttystop(struct tty *tp, int flag)
1469 {
1470
1471 /*
1472 * XXX We don't do anything here, yet. Mostly, I don't know
1473 * XXX exactly how this should be implemented on this device.
1474 * XXX We've given a big chunk of data to the MIPS already,
1475 * XXX and I don't know how we request the MIPS to stop sending
1476 * XXX the data. So, punt for now. --thorpej
1477 */
1478 return (0);
1479 }
1480
1481 /*
1482 * cztty_diag:
1483 *
1484 * Issue a scheduled diagnostic message.
1485 */
1486 void
cztty_diag(void * arg)1487 cztty_diag(void *arg)
1488 {
1489 struct cztty_softc *sc = arg;
1490 struct cz_softc *cz = CZTTY_CZ(sc);
1491 u_int overflows, parity_errors, framing_errors;
1492 int s;
1493
1494 s = spltty();
1495
1496 overflows = sc->sc_overflows;
1497 sc->sc_overflows = 0;
1498
1499 parity_errors = sc->sc_parity_errors;
1500 sc->sc_parity_errors = 0;
1501
1502 framing_errors = sc->sc_framing_errors;
1503 sc->sc_framing_errors = 0;
1504
1505 sc->sc_errors = 0;
1506
1507 splx(s);
1508
1509 log(LOG_WARNING,
1510 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n",
1511 cz->cz_dev.dv_xname, sc->sc_channel,
1512 overflows, overflows == 1 ? "" : "s",
1513 parity_errors,
1514 framing_errors, framing_errors == 1 ? "" : "s");
1515 }
1516
1517 /*
1518 * tx and rx ring buffer size macros:
1519 *
1520 * The transmitter and receiver both use ring buffers. For each one, there
1521 * is a get (consumer) and a put (producer) offset. The get value is the
1522 * next byte to be read from the ring, and the put is the next one to be
1523 * put into the ring. get == put means the ring is empty.
1524 *
1525 * For each ring, the firmware controls one of (get, put) and this driver
1526 * controls the other. For transmission, this driver updates put to point
1527 * past the valid data, and the firmware moves get as bytes are sent. Likewise
1528 * for receive, the driver controls put, and this driver controls get.
1529 */
1530 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p)))
1531 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g)))
1532
1533 /*
1534 * cztty_transmit()
1535 *
1536 * Look at the tty for this port and start sending.
1537 */
1538 int
cztty_transmit(struct cztty_softc * sc,struct tty * tp)1539 cztty_transmit(struct cztty_softc *sc, struct tty *tp)
1540 {
1541 struct cz_softc *cz = CZTTY_CZ(sc);
1542 u_int move, get, put, size, address;
1543 #ifdef HOSTRAMCODE
1544 int error, done = 0;
1545 #else
1546 int done = 0;
1547 #endif
1548
1549 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE);
1550 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET);
1551 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT);
1552 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR);
1553
1554 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){
1555 #ifdef HOSTRAMCODE
1556 if (0) {
1557 move = min(tp->t_outq.c_cc, move);
1558 error = q_to_b(&tp->t_outq, 0, move);
1559 if (error != move) {
1560 printf("%s: channel %d: error moving to "
1561 "transmit buf\n", cz->cz_dev.dv_xname,
1562 sc->sc_channel);
1563 move = error;
1564 }
1565 } else {
1566 #endif
1567 move = min(ndqb(&tp->t_outq, 0), move);
1568 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh,
1569 address + put, tp->t_outq.c_cf, move);
1570 ndflush(&tp->t_outq, move);
1571 #ifdef HOSTRAMCODE
1572 }
1573 #endif
1574
1575 put = ((put + move) % size);
1576 done = 1;
1577 }
1578 if (done) {
1579 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put);
1580 }
1581 return (done);
1582 }
1583
1584 int
cztty_receive(struct cztty_softc * sc,struct tty * tp)1585 cztty_receive(struct cztty_softc *sc, struct tty *tp)
1586 {
1587 struct cz_softc *cz = CZTTY_CZ(sc);
1588 u_int get, put, size, address;
1589 int done = 0, ch;
1590
1591 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE);
1592 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET);
1593 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT);
1594 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR);
1595
1596 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) {
1597 #ifdef HOSTRAMCODE
1598 if (hostram)
1599 ch = ((char *)fifoaddr)[get];
1600 } else {
1601 #endif
1602 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh,
1603 address + get);
1604 #ifdef HOSTRAMCODE
1605 }
1606 #endif
1607 (*linesw[tp->t_line].l_rint)(ch, tp);
1608 get = (get + 1) % size;
1609 done = 1;
1610 }
1611 if (done) {
1612 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get);
1613 }
1614 return (done);
1615 }
1616