1 /** @file 2 Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller. 3 4 Copyright (c) 2013 - 2019 Intel Corporation. 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _MRC_WRAPPER_H 11 #define _MRC_WRAPPER_H 12 13 #include <Ppi/QNCMemoryInit.h> 14 #include "PlatformEarlyInit.h" 15 16 // 17 // Define the default memory areas required 18 // 19 #define EDKII_RESERVED_SIZE_PAGES 0x40 20 #define ACPI_NVS_SIZE_PAGES 0x40 21 #define RUNTIME_SERVICES_DATA_SIZE_PAGES 0xC0 22 #define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80 23 #define ACPI_RECLAIM_SIZE_PAGES 0x20 24 25 // 26 // Maximum number of "Socket Sets", where a "Socket Set is a set of matching 27 // DIMM's from the various channels 28 // 29 #define MAX_SOCKET_SETS 2 30 31 // 32 // Maximum number of memory ranges supported by the memory controller 33 // 34 #define MAX_RANGES (MAX_ROWS + 5) 35 36 // 37 // Min. of 48MB PEI phase 38 // 39 #define PEI_MIN_MEMORY_SIZE (6 * 0x800000) 40 #define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000) 41 42 #define PEI_MEMORY_RANGE_OPTION_ROM UINT32 43 #define PEI_MR_OPTION_ROM_NONE 0x00000000 44 45 // 46 // SMRAM Memory Range 47 // 48 #define PEI_MEMORY_RANGE_SMRAM UINT32 49 #define PEI_MR_SMRAM_ALL 0xFFFFFFFF 50 #define PEI_MR_SMRAM_NONE 0x00000000 51 #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000 52 #define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000 53 #define PEI_MR_SMRAM_ABSEG_MASK 0x00010000 54 #define PEI_MR_SMRAM_HSEG_MASK 0x00020000 55 #define PEI_MR_SMRAM_TSEG_MASK 0x00040000 56 // 57 // SMRAM Size is a multiple of 128KB. 58 // 59 #define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF 60 61 // 62 // Pci Memory Hole 63 // 64 #define PEI_MEMORY_RANGE_PCI_MEMORY UINT32 65 66 typedef enum { 67 Ignore, 68 Quick, 69 Sparse, 70 Extensive 71 } PEI_MEMORY_TEST_OP; 72 73 // 74 // MRC Params Variable structure. 75 // 76 77 typedef struct { 78 MrcTimings_t timings; // Actual MRC config values saved in variable store. 79 UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes. 80 } PLATFORM_VARIABLE_MEMORY_CONFIG_DATA; 81 82 /// 83 /// MRC Params Platform Data Flags bits 84 /// 85 #define PDAT_MRC_FLAG_ECC_EN BIT0 86 #define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1 87 #define PDAT_MRC_FLAG_MEMTEST_EN BIT2 88 #define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology. 89 #define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes. 90 91 /// 92 /// MRC Params Platform Data. 93 /// 94 typedef struct { 95 UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above. 96 UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED. 97 UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. 98 UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED. 99 UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. 100 UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED. 101 UINT8 ChanWidth; ///< 1=x16, others=RESERVED. 102 UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. 103 UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. 104 UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED. 105 UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. 106 UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. 107 UINT8 DramRttWrVal; ///< 0=off others=RESERVED. 108 UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. 109 UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. 110 UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED. 111 UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. 112 UINT32 tRAS; ///< ACT to PRE command period in picoseconds. 113 UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds. 114 UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. 115 UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. 116 UINT8 tCL; ///< DRAM CAS Latency in clocks. 117 } PDAT_MRC_ITEM; 118 119 // 120 // Memory range types 121 // 122 typedef enum { 123 DualChannelDdrMainMemory, 124 DualChannelDdrSmramCacheable, 125 DualChannelDdrSmramNonCacheable, 126 DualChannelDdrGraphicsMemoryCacheable, 127 DualChannelDdrGraphicsMemoryNonCacheable, 128 DualChannelDdrReservedMemory, 129 DualChannelDdrMaxMemoryRangeType 130 } PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE; 131 132 // 133 // Memory map range information 134 // 135 typedef struct { 136 EFI_PHYSICAL_ADDRESS PhysicalAddress; 137 EFI_PHYSICAL_ADDRESS CpuAddress; 138 EFI_PHYSICAL_ADDRESS RangeLength; 139 PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type; 140 } PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE; 141 142 // 143 // Function prototypes. 144 // 145 146 EFI_STATUS 147 InstallEfiMemory ( 148 IN EFI_PEI_SERVICES **PeiServices, 149 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, 150 IN EFI_BOOT_MODE BootMode, 151 IN UINT32 TotalMemorySize 152 ); 153 154 EFI_STATUS 155 InstallS3Memory ( 156 IN EFI_PEI_SERVICES **PeiServices, 157 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, 158 IN UINT32 TotalMemorySize 159 ); 160 161 EFI_STATUS 162 MemoryInit ( 163 IN EFI_PEI_SERVICES **PeiServices 164 ); 165 166 167 EFI_STATUS 168 LoadConfig ( 169 IN EFI_PEI_SERVICES **PeiServices, 170 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices, 171 IN OUT MRCParams_t *MrcData 172 ); 173 174 EFI_STATUS 175 SaveConfig ( 176 IN MRCParams_t *MrcData 177 ); 178 179 EFI_STATUS 180 GetMemoryMap ( 181 IN EFI_PEI_SERVICES **PeiServices, 182 IN UINT32 TotalMemorySize, 183 IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap, 184 IN OUT UINT8 *NumRanges 185 ); 186 187 EFI_STATUS 188 ChooseRanges ( 189 IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, 190 IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, 191 IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask 192 ); 193 194 EFI_STATUS 195 GetPlatformMemorySize ( 196 IN EFI_PEI_SERVICES **PeiServices, 197 IN EFI_BOOT_MODE BootMode, 198 IN OUT UINT64 *MemorySize 199 ); 200 201 EFI_STATUS 202 BaseMemoryTest ( 203 IN EFI_PEI_SERVICES **PeiServices, 204 IN EFI_PHYSICAL_ADDRESS BeginAddress, 205 IN UINT64 MemoryLength, 206 IN PEI_MEMORY_TEST_OP Operation, 207 OUT EFI_PHYSICAL_ADDRESS *ErrorAddress 208 ); 209 210 EFI_STATUS 211 SetPlatformImrPolicy ( 212 IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress, 213 IN UINT64 PeiMemoryLength 214 ); 215 216 VOID 217 EFIAPI 218 InfoPostInstallMemory ( 219 OUT UINT32 *RmuBaseAddressPtr OPTIONAL, 220 OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL, 221 OUT UINTN *NumSmramRegionsPtr OPTIONAL 222 ); 223 224 #endif 225