| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue17/ |
| H A D | cond_assign_sig.vhdl | 9 signal Clk : std_logic := '0' ; signal
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| H A D | cond_assign_proc.vhdl | 8 signal Clk : std_logic := '0' ; signal
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| H A D | cond_assign_var.vhdl | 9 signal Clk : std_logic := '0' ; signal
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue375/ |
| H A D | cond_assign_proc.vhdl | 9 signal Clk : std_logic := '0' ; signal
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/common/sync/ |
| H A D | Pulser.vhd | 48 Clk : in std_logic; port
180 signal Clk: std_logic := '0'; signal
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| /dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/ |
| H A D | code_hdl_models_GrayCounter.v | 15 input wire Clk); port
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| /dports/games/chessx/chessx-1.5.6/src/dialogs/ |
| H A D | commentdialog.h | 14 enum TimeMode { Egt, Emt, Clk}; enumerator
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/ticket104/ |
| H A D | bug_tb.vhd | 16 signal Clk : std_logic := '1'; signal
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_mem_slot.v | 11 input Clk; port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1131/ |
| H A D | dut.vhdl | 10 Clk : in std_logic; port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/simple_gemac/miim/ |
| H A D | eth_clockgen.v | 85 input Clk; // Input clock (Host clock) port
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| H A D | eth_shiftreg.v | 91 input Clk; // Input clock (Host clock) port
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| H A D | eth_outputcontrol.v | 86 input Clk; // Host Clock port
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| H A D | eth_miim.v | 121 input Clk; // Host Clock port
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| /dports/x11/eaglemode/eaglemode-0.95.0/include/emMain/ |
| H A D | emMainWindow.h | 110 emUInt64 Clk; variable
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ |
| H A D | ScsConfig.h | 69 MUX_GPIO_PARAM Clk; member
77 MUX_GPIO_PARAM Clk; member
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1051/ |
| H A D | psi_common_i2c_master_tb.vhd | 62 signal Clk : std_logic := '1'; signal
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| H A D | psi_common_i2c_master.vhd | 65 Clk : in std_logic; -- $$ type=clk; freq=125e6 $$ port
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 140 static int get_clk_range_index(u32 Clk) in get_clk_range_index()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 140 static int get_clk_range_index(u32 Clk) in get_clk_range_index()
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 140 static int get_clk_range_index(u32 Clk) in get_clk_range_index()
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| /dports/cad/ghdl/ghdl-1.0.0/src/synth/ |
| H A D | netlists-inference.adb | 805 Clk : Net; variable
924 Clk, En : Net; variable
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| H A D | netlists-memories.adb | 531 Clk, En : Net; variable
613 Clk, En : Net; variable
1018 Clk : Net; variable
1931 Clk : Net; variable
2032 Clk : Net; variable
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| /dports/games/libretro-bluemsx/blueMSX-libretro-faf470e/Src/IoDevice/ |
| H A D | Microwire93Cx6.c | 53 int Clk; member
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| /dports/cad/ghdl/ghdl-1.0.0/src/vhdl/ |
| H A D | vhdl-sem_psl.adb | 707 Clk : PSL_Node; variable
885 Clk : PSL_Node; variable
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