1 /* Declarations for Intel 80386 opcode table 2 Copyright (C) 2007-2020 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "opcode/i386.h" 22 #ifdef HAVE_LIMITS_H 23 #include <limits.h> 24 #endif 25 26 #ifndef CHAR_BIT 27 #define CHAR_BIT 8 28 #endif 29 30 /* Position of cpu flags bitfiled. */ 31 32 enum 33 { 34 /* i186 or better required */ 35 Cpu186 = 0, 36 /* i286 or better required */ 37 Cpu286, 38 /* i386 or better required */ 39 Cpu386, 40 /* i486 or better required */ 41 Cpu486, 42 /* i585 or better required */ 43 Cpu586, 44 /* i686 or better required */ 45 Cpu686, 46 /* CMOV Instruction support required */ 47 CpuCMOV, 48 /* FXSR Instruction support required */ 49 CpuFXSR, 50 /* CLFLUSH Instruction support required */ 51 CpuClflush, 52 /* NOP Instruction support required */ 53 CpuNop, 54 /* SYSCALL Instructions support required */ 55 CpuSYSCALL, 56 /* Floating point support required */ 57 Cpu8087, 58 /* i287 support required */ 59 Cpu287, 60 /* i387 support required */ 61 Cpu387, 62 /* i686 and floating point support required */ 63 Cpu687, 64 /* SSE3 and floating point support required */ 65 CpuFISTTP, 66 /* MMX support required */ 67 CpuMMX, 68 /* SSE support required */ 69 CpuSSE, 70 /* SSE2 support required */ 71 CpuSSE2, 72 /* 3dnow! support required */ 73 Cpu3dnow, 74 /* 3dnow! Extensions support required */ 75 Cpu3dnowA, 76 /* SSE3 support required */ 77 CpuSSE3, 78 /* VIA PadLock required */ 79 CpuPadLock, 80 /* AMD Secure Virtual Machine Ext-s required */ 81 CpuSVME, 82 /* VMX Instructions required */ 83 CpuVMX, 84 /* SMX Instructions required */ 85 CpuSMX, 86 /* SSSE3 support required */ 87 CpuSSSE3, 88 /* SSE4a support required */ 89 CpuSSE4a, 90 /* ABM New Instructions required */ 91 CpuABM, 92 /* SSE4.1 support required */ 93 CpuSSE4_1, 94 /* SSE4.2 support required */ 95 CpuSSE4_2, 96 /* AVX support required */ 97 CpuAVX, 98 /* AVX2 support required */ 99 CpuAVX2, 100 /* Intel AVX-512 Foundation Instructions support required */ 101 CpuAVX512F, 102 /* Intel AVX-512 Conflict Detection Instructions support required */ 103 CpuAVX512CD, 104 /* Intel AVX-512 Exponential and Reciprocal Instructions support 105 required */ 106 CpuAVX512ER, 107 /* Intel AVX-512 Prefetch Instructions support required */ 108 CpuAVX512PF, 109 /* Intel AVX-512 VL Instructions support required. */ 110 CpuAVX512VL, 111 /* Intel AVX-512 DQ Instructions support required. */ 112 CpuAVX512DQ, 113 /* Intel AVX-512 BW Instructions support required. */ 114 CpuAVX512BW, 115 /* Intel L1OM support required */ 116 CpuL1OM, 117 /* Intel K1OM support required */ 118 CpuK1OM, 119 /* Intel IAMCU support required */ 120 CpuIAMCU, 121 /* Xsave/xrstor New Instructions support required */ 122 CpuXsave, 123 /* Xsaveopt New Instructions support required */ 124 CpuXsaveopt, 125 /* AES support required */ 126 CpuAES, 127 /* PCLMUL support required */ 128 CpuPCLMUL, 129 /* FMA support required */ 130 CpuFMA, 131 /* FMA4 support required */ 132 CpuFMA4, 133 /* XOP support required */ 134 CpuXOP, 135 /* LWP support required */ 136 CpuLWP, 137 /* BMI support required */ 138 CpuBMI, 139 /* TBM support required */ 140 CpuTBM, 141 /* MOVBE Instruction support required */ 142 CpuMovbe, 143 /* CMPXCHG16B instruction support required. */ 144 CpuCX16, 145 /* EPT Instructions required */ 146 CpuEPT, 147 /* RDTSCP Instruction support required */ 148 CpuRdtscp, 149 /* FSGSBASE Instructions required */ 150 CpuFSGSBase, 151 /* RDRND Instructions required */ 152 CpuRdRnd, 153 /* F16C Instructions required */ 154 CpuF16C, 155 /* Intel BMI2 support required */ 156 CpuBMI2, 157 /* LZCNT support required */ 158 CpuLZCNT, 159 /* HLE support required */ 160 CpuHLE, 161 /* RTM support required */ 162 CpuRTM, 163 /* INVPCID Instructions required */ 164 CpuINVPCID, 165 /* VMFUNC Instruction required */ 166 CpuVMFUNC, 167 /* Intel MPX Instructions required */ 168 CpuMPX, 169 /* 64bit support available, used by -march= in assembler. */ 170 CpuLM, 171 /* RDRSEED instruction required. */ 172 CpuRDSEED, 173 /* Multi-presisionn add-carry instructions are required. */ 174 CpuADX, 175 /* Supports prefetchw and prefetch instructions. */ 176 CpuPRFCHW, 177 /* SMAP instructions required. */ 178 CpuSMAP, 179 /* SHA instructions required. */ 180 CpuSHA, 181 /* CLFLUSHOPT instruction required */ 182 CpuClflushOpt, 183 /* XSAVES/XRSTORS instruction required */ 184 CpuXSAVES, 185 /* XSAVEC instruction required */ 186 CpuXSAVEC, 187 /* PREFETCHWT1 instruction required */ 188 CpuPREFETCHWT1, 189 /* SE1 instruction required */ 190 CpuSE1, 191 /* CLWB instruction required */ 192 CpuCLWB, 193 /* Intel AVX-512 IFMA Instructions support required. */ 194 CpuAVX512IFMA, 195 /* Intel AVX-512 VBMI Instructions support required. */ 196 CpuAVX512VBMI, 197 /* Intel AVX-512 4FMAPS Instructions support required. */ 198 CpuAVX512_4FMAPS, 199 /* Intel AVX-512 4VNNIW Instructions support required. */ 200 CpuAVX512_4VNNIW, 201 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ 202 CpuAVX512_VPOPCNTDQ, 203 /* Intel AVX-512 VBMI2 Instructions support required. */ 204 CpuAVX512_VBMI2, 205 /* Intel AVX-512 VNNI Instructions support required. */ 206 CpuAVX512_VNNI, 207 /* Intel AVX-512 BITALG Instructions support required. */ 208 CpuAVX512_BITALG, 209 /* Intel AVX-512 BF16 Instructions support required. */ 210 CpuAVX512_BF16, 211 /* Intel AVX-512 VP2INTERSECT Instructions support required. */ 212 CpuAVX512_VP2INTERSECT, 213 /* mwaitx instruction required */ 214 CpuMWAITX, 215 /* Clzero instruction required */ 216 CpuCLZERO, 217 /* OSPKE instruction required */ 218 CpuOSPKE, 219 /* RDPID instruction required */ 220 CpuRDPID, 221 /* PTWRITE instruction required */ 222 CpuPTWRITE, 223 /* CET instructions support required */ 224 CpuIBT, 225 CpuSHSTK, 226 /* GFNI instructions required */ 227 CpuGFNI, 228 /* VAES instructions required */ 229 CpuVAES, 230 /* VPCLMULQDQ instructions required */ 231 CpuVPCLMULQDQ, 232 /* WBNOINVD instructions required */ 233 CpuWBNOINVD, 234 /* PCONFIG instructions required */ 235 CpuPCONFIG, 236 /* WAITPKG instructions required */ 237 CpuWAITPKG, 238 /* CLDEMOTE instruction required */ 239 CpuCLDEMOTE, 240 /* MOVDIRI instruction support required */ 241 CpuMOVDIRI, 242 /* MOVDIRR64B instruction required */ 243 CpuMOVDIR64B, 244 /* ENQCMD instruction required */ 245 CpuENQCMD, 246 /* RDPRU instruction required */ 247 CpuRDPRU, 248 /* MCOMMIT instruction required */ 249 CpuMCOMMIT, 250 /* 64bit support required */ 251 Cpu64, 252 /* Not supported in the 64bit mode */ 253 CpuNo64, 254 /* The last bitfield in i386_cpu_flags. */ 255 CpuMax = CpuNo64 256 }; 257 258 #define CpuNumOfUints \ 259 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 260 #define CpuNumOfBits \ 261 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 262 263 /* If you get a compiler error for zero width of the unused field, 264 comment it out. */ 265 #define CpuUnused (CpuMax + 1) 266 267 /* We can check if an instruction is available with array instead 268 of bitfield. */ 269 typedef union i386_cpu_flags 270 { 271 struct 272 { 273 unsigned int cpui186:1; 274 unsigned int cpui286:1; 275 unsigned int cpui386:1; 276 unsigned int cpui486:1; 277 unsigned int cpui586:1; 278 unsigned int cpui686:1; 279 unsigned int cpucmov:1; 280 unsigned int cpufxsr:1; 281 unsigned int cpuclflush:1; 282 unsigned int cpunop:1; 283 unsigned int cpusyscall:1; 284 unsigned int cpu8087:1; 285 unsigned int cpu287:1; 286 unsigned int cpu387:1; 287 unsigned int cpu687:1; 288 unsigned int cpufisttp:1; 289 unsigned int cpummx:1; 290 unsigned int cpusse:1; 291 unsigned int cpusse2:1; 292 unsigned int cpua3dnow:1; 293 unsigned int cpua3dnowa:1; 294 unsigned int cpusse3:1; 295 unsigned int cpupadlock:1; 296 unsigned int cpusvme:1; 297 unsigned int cpuvmx:1; 298 unsigned int cpusmx:1; 299 unsigned int cpussse3:1; 300 unsigned int cpusse4a:1; 301 unsigned int cpuabm:1; 302 unsigned int cpusse4_1:1; 303 unsigned int cpusse4_2:1; 304 unsigned int cpuavx:1; 305 unsigned int cpuavx2:1; 306 unsigned int cpuavx512f:1; 307 unsigned int cpuavx512cd:1; 308 unsigned int cpuavx512er:1; 309 unsigned int cpuavx512pf:1; 310 unsigned int cpuavx512vl:1; 311 unsigned int cpuavx512dq:1; 312 unsigned int cpuavx512bw:1; 313 unsigned int cpul1om:1; 314 unsigned int cpuk1om:1; 315 unsigned int cpuiamcu:1; 316 unsigned int cpuxsave:1; 317 unsigned int cpuxsaveopt:1; 318 unsigned int cpuaes:1; 319 unsigned int cpupclmul:1; 320 unsigned int cpufma:1; 321 unsigned int cpufma4:1; 322 unsigned int cpuxop:1; 323 unsigned int cpulwp:1; 324 unsigned int cpubmi:1; 325 unsigned int cputbm:1; 326 unsigned int cpumovbe:1; 327 unsigned int cpucx16:1; 328 unsigned int cpuept:1; 329 unsigned int cpurdtscp:1; 330 unsigned int cpufsgsbase:1; 331 unsigned int cpurdrnd:1; 332 unsigned int cpuf16c:1; 333 unsigned int cpubmi2:1; 334 unsigned int cpulzcnt:1; 335 unsigned int cpuhle:1; 336 unsigned int cpurtm:1; 337 unsigned int cpuinvpcid:1; 338 unsigned int cpuvmfunc:1; 339 unsigned int cpumpx:1; 340 unsigned int cpulm:1; 341 unsigned int cpurdseed:1; 342 unsigned int cpuadx:1; 343 unsigned int cpuprfchw:1; 344 unsigned int cpusmap:1; 345 unsigned int cpusha:1; 346 unsigned int cpuclflushopt:1; 347 unsigned int cpuxsaves:1; 348 unsigned int cpuxsavec:1; 349 unsigned int cpuprefetchwt1:1; 350 unsigned int cpuse1:1; 351 unsigned int cpuclwb:1; 352 unsigned int cpuavx512ifma:1; 353 unsigned int cpuavx512vbmi:1; 354 unsigned int cpuavx512_4fmaps:1; 355 unsigned int cpuavx512_4vnniw:1; 356 unsigned int cpuavx512_vpopcntdq:1; 357 unsigned int cpuavx512_vbmi2:1; 358 unsigned int cpuavx512_vnni:1; 359 unsigned int cpuavx512_bitalg:1; 360 unsigned int cpuavx512_bf16:1; 361 unsigned int cpuavx512_vp2intersect:1; 362 unsigned int cpumwaitx:1; 363 unsigned int cpuclzero:1; 364 unsigned int cpuospke:1; 365 unsigned int cpurdpid:1; 366 unsigned int cpuptwrite:1; 367 unsigned int cpuibt:1; 368 unsigned int cpushstk:1; 369 unsigned int cpugfni:1; 370 unsigned int cpuvaes:1; 371 unsigned int cpuvpclmulqdq:1; 372 unsigned int cpuwbnoinvd:1; 373 unsigned int cpupconfig:1; 374 unsigned int cpuwaitpkg:1; 375 unsigned int cpucldemote:1; 376 unsigned int cpumovdiri:1; 377 unsigned int cpumovdir64b:1; 378 unsigned int cpuenqcmd:1; 379 unsigned int cpurdpru:1; 380 unsigned int cpumcommit:1; 381 unsigned int cpu64:1; 382 unsigned int cpuno64:1; 383 #ifdef CpuUnused 384 unsigned int unused:(CpuNumOfBits - CpuUnused); 385 #endif 386 } bitfield; 387 unsigned int array[CpuNumOfUints]; 388 } i386_cpu_flags; 389 390 /* Position of opcode_modifier bits. */ 391 392 enum 393 { 394 /* has direction bit. */ 395 D = 0, 396 /* set if operands can be both bytes and words/dwords/qwords, encoded the 397 canonical way; the base_opcode field should hold the encoding for byte 398 operands */ 399 W, 400 /* load form instruction. Must be placed before store form. */ 401 Load, 402 /* insn has a modrm byte. */ 403 Modrm, 404 /* register is in low 3 bits of opcode */ 405 ShortForm, 406 /* special case for jump insns; value has to be 1 */ 407 #define JUMP 1 408 /* call and jump */ 409 #define JUMP_DWORD 2 410 /* loop and jecxz */ 411 #define JUMP_BYTE 3 412 /* special case for intersegment leaps/calls */ 413 #define JUMP_INTERSEGMENT 4 414 /* absolute address for jump */ 415 #define JUMP_ABSOLUTE 5 416 Jump, 417 /* FP insn memory format bit, sized by 0x4 */ 418 FloatMF, 419 /* src/dest swap for floats. */ 420 FloatR, 421 /* needs size prefix if in 32-bit mode */ 422 #define SIZE16 1 423 /* needs size prefix if in 16-bit mode */ 424 #define SIZE32 2 425 /* needs size prefix if in 64-bit mode */ 426 #define SIZE64 3 427 Size, 428 /* check register size. */ 429 CheckRegSize, 430 /* instruction ignores operand size prefix and in Intel mode ignores 431 mnemonic size suffix check. */ 432 IgnoreSize, 433 /* default insn size depends on mode */ 434 DefaultSize, 435 /* any memory size */ 436 Anysize, 437 /* b suffix on instruction illegal */ 438 No_bSuf, 439 /* w suffix on instruction illegal */ 440 No_wSuf, 441 /* l suffix on instruction illegal */ 442 No_lSuf, 443 /* s suffix on instruction illegal */ 444 No_sSuf, 445 /* q suffix on instruction illegal */ 446 No_qSuf, 447 /* long double suffix on instruction illegal */ 448 No_ldSuf, 449 /* instruction needs FWAIT */ 450 FWait, 451 /* IsString provides for a quick test for string instructions, and 452 its actual value also indicates which of the operands (if any) 453 requires use of the %es segment. */ 454 #define IS_STRING_ES_OP0 2 455 #define IS_STRING_ES_OP1 3 456 IsString, 457 /* RegMem is for instructions with a modrm byte where the register 458 destination operand should be encoded in the mod and regmem fields. 459 Normally, it will be encoded in the reg field. We add a RegMem 460 flag to indicate that it should be encoded in the regmem field. */ 461 RegMem, 462 /* quick test if branch instruction is MPX supported */ 463 BNDPrefixOk, 464 /* quick test if NOTRACK prefix is supported */ 465 NoTrackPrefixOk, 466 /* quick test for lockable instructions */ 467 IsLockable, 468 /* fake an extra reg operand for clr, imul and special register 469 processing for some instructions. */ 470 RegKludge, 471 /* An implicit xmm0 as the first operand */ 472 Implicit1stXmm0, 473 /* The HLE prefix is OK: 474 1. With a LOCK prefix. 475 2. With or without a LOCK prefix. 476 3. With a RELEASE (0xf3) prefix. 477 */ 478 #define HLEPrefixNone 0 479 #define HLEPrefixLock 1 480 #define HLEPrefixAny 2 481 #define HLEPrefixRelease 3 482 HLEPrefixOk, 483 /* An instruction on which a "rep" prefix is acceptable. */ 484 RepPrefixOk, 485 /* Convert to DWORD */ 486 ToDword, 487 /* Convert to QWORD */ 488 ToQword, 489 /* Address prefix changes register operand */ 490 AddrPrefixOpReg, 491 /* opcode is a prefix */ 492 IsPrefix, 493 /* instruction has extension in 8 bit imm */ 494 ImmExt, 495 /* instruction don't need Rex64 prefix. */ 496 NoRex64, 497 /* instruction require Rex64 prefix. */ 498 Rex64, 499 /* deprecated fp insn, gets a warning */ 500 Ugh, 501 /* insn has VEX prefix: 502 1: 128bit VEX prefix (or operand dependent). 503 2: 256bit VEX prefix. 504 3: Scalar VEX prefix. 505 */ 506 #define VEX128 1 507 #define VEX256 2 508 #define VEXScalar 3 509 Vex, 510 /* How to encode VEX.vvvv: 511 0: VEX.vvvv must be 1111b. 512 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where 513 the content of source registers will be preserved. 514 VEX.DDS. The second register operand is encoded in VEX.vvvv 515 where the content of first source register will be overwritten 516 by the result. 517 VEX.NDD2. The second destination register operand is encoded in 518 VEX.vvvv for instructions with 2 destination register operands. 519 For assembler, there are no difference between VEX.NDS, VEX.DDS 520 and VEX.NDD2. 521 2. VEX.NDD. Register destination is encoded in VEX.vvvv for 522 instructions with 1 destination register operand. 523 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one 524 of the operands can access a memory location. 525 */ 526 #define VEXXDS 1 527 #define VEXNDD 2 528 #define VEXLWP 3 529 VexVVVV, 530 /* How the VEX.W bit is used: 531 0: Set by the REX.W bit. 532 1: VEX.W0. Should always be 0. 533 2: VEX.W1. Should always be 1. 534 3: VEX.WIG. The VEX.W bit is ignored. 535 */ 536 #define VEXW0 1 537 #define VEXW1 2 538 #define VEXWIG 3 539 VexW, 540 /* VEX opcode prefix: 541 0: VEX 0x0F opcode prefix. 542 1: VEX 0x0F38 opcode prefix. 543 2: VEX 0x0F3A opcode prefix 544 3: XOP 0x08 opcode prefix. 545 4: XOP 0x09 opcode prefix 546 5: XOP 0x0A opcode prefix. 547 */ 548 #define VEX0F 0 549 #define VEX0F38 1 550 #define VEX0F3A 2 551 #define XOP08 3 552 #define XOP09 4 553 #define XOP0A 5 554 VexOpcode, 555 /* number of VEX source operands: 556 0: <= 2 source operands. 557 1: 2 XOP source operands. 558 2: 3 source operands. 559 */ 560 #define XOP2SOURCES 1 561 #define VEX3SOURCES 2 562 VexSources, 563 /* Instruction with vector SIB byte: 564 1: 128bit vector register. 565 2: 256bit vector register. 566 3: 512bit vector register. 567 */ 568 #define VecSIB128 1 569 #define VecSIB256 2 570 #define VecSIB512 3 571 VecSIB, 572 /* SSE to AVX support required */ 573 SSE2AVX, 574 /* No AVX equivalent */ 575 NoAVX, 576 577 /* insn has EVEX prefix: 578 1: 512bit EVEX prefix. 579 2: 128bit EVEX prefix. 580 3: 256bit EVEX prefix. 581 4: Length-ignored (LIG) EVEX prefix. 582 5: Length determined from actual operands. 583 */ 584 #define EVEX512 1 585 #define EVEX128 2 586 #define EVEX256 3 587 #define EVEXLIG 4 588 #define EVEXDYN 5 589 EVex, 590 591 /* AVX512 masking support: 592 1: Zeroing or merging masking depending on operands. 593 2: Merging-masking. 594 3: Both zeroing and merging masking. 595 */ 596 #define DYNAMIC_MASKING 1 597 #define MERGING_MASKING 2 598 #define BOTH_MASKING 3 599 Masking, 600 601 /* AVX512 broadcast support. The number of bytes to broadcast is 602 1 << (Broadcast - 1): 603 1: Byte broadcast. 604 2: Word broadcast. 605 3: Dword broadcast. 606 4: Qword broadcast. 607 */ 608 #define BYTE_BROADCAST 1 609 #define WORD_BROADCAST 2 610 #define DWORD_BROADCAST 3 611 #define QWORD_BROADCAST 4 612 Broadcast, 613 614 /* Static rounding control is supported. */ 615 StaticRounding, 616 617 /* Supress All Exceptions is supported. */ 618 SAE, 619 620 /* Compressed Disp8*N attribute. */ 621 #define DISP8_SHIFT_VL 7 622 Disp8MemShift, 623 624 /* Default mask isn't allowed. */ 625 NoDefMask, 626 627 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. 628 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). 629 */ 630 ImplicitQuadGroup, 631 632 /* Support encoding optimization. */ 633 Optimize, 634 635 /* AT&T mnemonic. */ 636 ATTMnemonic, 637 /* AT&T syntax. */ 638 ATTSyntax, 639 /* Intel syntax. */ 640 IntelSyntax, 641 /* AMD64. */ 642 AMD64, 643 /* Intel64. */ 644 Intel64, 645 /* The last bitfield in i386_opcode_modifier. */ 646 Opcode_Modifier_Num 647 }; 648 649 typedef struct i386_opcode_modifier 650 { 651 unsigned int d:1; 652 unsigned int w:1; 653 unsigned int load:1; 654 unsigned int modrm:1; 655 unsigned int shortform:1; 656 unsigned int jump:3; 657 unsigned int floatmf:1; 658 unsigned int floatr:1; 659 unsigned int size:2; 660 unsigned int checkregsize:1; 661 unsigned int ignoresize:1; 662 unsigned int defaultsize:1; 663 unsigned int anysize:1; 664 unsigned int no_bsuf:1; 665 unsigned int no_wsuf:1; 666 unsigned int no_lsuf:1; 667 unsigned int no_ssuf:1; 668 unsigned int no_qsuf:1; 669 unsigned int no_ldsuf:1; 670 unsigned int fwait:1; 671 unsigned int isstring:2; 672 unsigned int regmem:1; 673 unsigned int bndprefixok:1; 674 unsigned int notrackprefixok:1; 675 unsigned int islockable:1; 676 unsigned int regkludge:1; 677 unsigned int implicit1stxmm0:1; 678 unsigned int hleprefixok:2; 679 unsigned int repprefixok:1; 680 unsigned int todword:1; 681 unsigned int toqword:1; 682 unsigned int addrprefixopreg:1; 683 unsigned int isprefix:1; 684 unsigned int immext:1; 685 unsigned int norex64:1; 686 unsigned int rex64:1; 687 unsigned int ugh:1; 688 unsigned int vex:2; 689 unsigned int vexvvvv:2; 690 unsigned int vexw:2; 691 unsigned int vexopcode:3; 692 unsigned int vexsources:2; 693 unsigned int vecsib:2; 694 unsigned int sse2avx:1; 695 unsigned int noavx:1; 696 unsigned int evex:3; 697 unsigned int masking:2; 698 unsigned int broadcast:3; 699 unsigned int staticrounding:1; 700 unsigned int sae:1; 701 unsigned int disp8memshift:3; 702 unsigned int nodefmask:1; 703 unsigned int implicitquadgroup:1; 704 unsigned int optimize:1; 705 unsigned int attmnemonic:1; 706 unsigned int attsyntax:1; 707 unsigned int intelsyntax:1; 708 unsigned int amd64:1; 709 unsigned int intel64:1; 710 } i386_opcode_modifier; 711 712 /* Operand classes. */ 713 714 #define CLASS_WIDTH 4 715 enum operand_class 716 { 717 ClassNone, 718 Reg, /* GPRs and FP regs, distinguished by operand size */ 719 SReg, /* Segment register */ 720 RegCR, /* Control register */ 721 RegDR, /* Debug register */ 722 RegTR, /* Test register */ 723 RegMMX, /* MMX register */ 724 RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ 725 RegMask, /* Vector Mask register */ 726 RegBND, /* Bound register */ 727 }; 728 729 /* Special operand instances. */ 730 731 #define INSTANCE_WIDTH 3 732 enum operand_instance 733 { 734 InstanceNone, 735 Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ 736 RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ 737 RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ 738 RegB, /* %bl / %bx / %ebx / %rbx */ 739 }; 740 741 /* Position of operand_type bits. */ 742 743 enum 744 { 745 /* Class and Instance */ 746 ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, 747 /* 1 bit immediate */ 748 Imm1, 749 /* 8 bit immediate */ 750 Imm8, 751 /* 8 bit immediate sign extended */ 752 Imm8S, 753 /* 16 bit immediate */ 754 Imm16, 755 /* 32 bit immediate */ 756 Imm32, 757 /* 32 bit immediate sign extended */ 758 Imm32S, 759 /* 64 bit immediate */ 760 Imm64, 761 /* 8bit/16bit/32bit displacements are used in different ways, 762 depending on the instruction. For jumps, they specify the 763 size of the PC relative displacement, for instructions with 764 memory operand, they specify the size of the offset relative 765 to the base register, and for instructions with memory offset 766 such as `mov 1234,%al' they specify the size of the offset 767 relative to the segment base. */ 768 /* 8 bit displacement */ 769 Disp8, 770 /* 16 bit displacement */ 771 Disp16, 772 /* 32 bit displacement */ 773 Disp32, 774 /* 32 bit signed displacement */ 775 Disp32S, 776 /* 64 bit displacement */ 777 Disp64, 778 /* Register which can be used for base or index in memory operand. */ 779 BaseIndex, 780 /* BYTE size. */ 781 Byte, 782 /* WORD size. 2 byte */ 783 Word, 784 /* DWORD size. 4 byte */ 785 Dword, 786 /* FWORD size. 6 byte */ 787 Fword, 788 /* QWORD size. 8 byte */ 789 Qword, 790 /* TBYTE size. 10 byte */ 791 Tbyte, 792 /* XMMWORD size. */ 793 Xmmword, 794 /* YMMWORD size. */ 795 Ymmword, 796 /* ZMMWORD size. */ 797 Zmmword, 798 /* Unspecified memory size. */ 799 Unspecified, 800 801 /* The number of bits in i386_operand_type. */ 802 OTNum 803 }; 804 805 #define OTNumOfUints \ 806 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) 807 #define OTNumOfBits \ 808 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 809 810 /* If you get a compiler error for zero width of the unused field, 811 comment it out. */ 812 #define OTUnused OTNum 813 814 typedef union i386_operand_type 815 { 816 struct 817 { 818 unsigned int class:CLASS_WIDTH; 819 unsigned int instance:INSTANCE_WIDTH; 820 unsigned int imm1:1; 821 unsigned int imm8:1; 822 unsigned int imm8s:1; 823 unsigned int imm16:1; 824 unsigned int imm32:1; 825 unsigned int imm32s:1; 826 unsigned int imm64:1; 827 unsigned int disp8:1; 828 unsigned int disp16:1; 829 unsigned int disp32:1; 830 unsigned int disp32s:1; 831 unsigned int disp64:1; 832 unsigned int baseindex:1; 833 unsigned int byte:1; 834 unsigned int word:1; 835 unsigned int dword:1; 836 unsigned int fword:1; 837 unsigned int qword:1; 838 unsigned int tbyte:1; 839 unsigned int xmmword:1; 840 unsigned int ymmword:1; 841 unsigned int zmmword:1; 842 unsigned int unspecified:1; 843 #ifdef OTUnused 844 unsigned int unused:(OTNumOfBits - OTUnused); 845 #endif 846 } bitfield; 847 unsigned int array[OTNumOfUints]; 848 } i386_operand_type; 849 850 typedef struct insn_template 851 { 852 /* instruction name sans width suffix ("mov" for movl insns) */ 853 char *name; 854 855 /* base_opcode is the fundamental opcode byte without optional 856 prefix(es). */ 857 unsigned int base_opcode; 858 #define Opcode_D 0x2 /* Direction bit: 859 set if Reg --> Regmem; 860 unset if Regmem --> Reg. */ 861 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ 862 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ 863 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ 864 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ 865 866 /* extension_opcode is the 3 bit extension for group <n> insns. 867 This field is also used to store the 8-bit opcode suffix for the 868 AMD 3DNow! instructions. 869 If this template has no extension opcode (the usual case) use None 870 Instructions */ 871 unsigned short extension_opcode; 872 #define None 0xffff /* If no extension_opcode is possible. */ 873 874 /* Opcode length. */ 875 unsigned char opcode_length; 876 877 /* how many operands */ 878 unsigned char operands; 879 880 /* cpu feature flags */ 881 i386_cpu_flags cpu_flags; 882 883 /* the bits in opcode_modifier are used to generate the final opcode from 884 the base_opcode. These bits also are used to detect alternate forms of 885 the same instruction */ 886 i386_opcode_modifier opcode_modifier; 887 888 /* operand_types[i] describes the type of operand i. This is made 889 by OR'ing together all of the possible type masks. (e.g. 890 'operand_types[i] = Reg|Imm' specifies that operand i can be 891 either a register or an immediate operand. */ 892 i386_operand_type operand_types[MAX_OPERANDS]; 893 } 894 insn_template; 895 896 extern const insn_template i386_optab[]; 897 898 /* these are for register name --> number & type hash lookup */ 899 typedef struct 900 { 901 char *reg_name; 902 i386_operand_type reg_type; 903 unsigned char reg_flags; 904 #define RegRex 0x1 /* Extended register. */ 905 #define RegRex64 0x2 /* Extended 8 bit register. */ 906 #define RegVRex 0x4 /* Extended vector register. */ 907 unsigned char reg_num; 908 #define RegIP ((unsigned char ) ~0) 909 /* EIZ and RIZ are fake index registers. */ 910 #define RegIZ (RegIP - 1) 911 /* FLAT is a fake segment register (Intel mode). */ 912 #define RegFlat ((unsigned char) ~0) 913 signed char dw2_regnum[2]; 914 #define Dw2Inval (-1) 915 } 916 reg_entry; 917 918 /* Entries in i386_regtab. */ 919 #define REGNAM_AL 1 920 #define REGNAM_AX 25 921 #define REGNAM_EAX 41 922 923 extern const reg_entry i386_regtab[]; 924 extern const unsigned int i386_regtab_size; 925 926 typedef struct 927 { 928 char *seg_name; 929 unsigned int seg_prefix; 930 } 931 seg_entry; 932 933 extern const seg_entry cs; 934 extern const seg_entry ds; 935 extern const seg_entry ss; 936 extern const seg_entry es; 937 extern const seg_entry fs; 938 extern const seg_entry gs; 939