1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_USB_UHCI_H 27 #define _SYS_USB_UHCI_H 28 29 30 #include <sys/types.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Universal Host Controller Driver (UHCI) 38 * 39 * The UHCI driver is a driver which interfaces to the Universal 40 * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to 41 * the Host Controller is defined by the Universal Host Controller 42 * Interface spec. 43 */ 44 45 46 #define LEGACYMODE_REG_OFFSET 0xc0 47 #define LEGACYMODE_REG_INIT_VALUE 0xaf00 48 49 /* 50 * The register set of the UCHI controller 51 * This structure is laid out for proper alignment so no need to pack(1). 52 */ 53 typedef volatile struct hcr_regs { 54 uint16_t USBCMD; 55 uint16_t USBSTS; 56 uint16_t USBINTR; 57 uint16_t FRNUM; 58 uint32_t FRBASEADD; 59 uchar_t SOFMOD; 60 uchar_t rsvd[3]; 61 uint16_t PORTSC[2]; 62 } hc_regs_t; 63 64 /* 65 * #defines for the USB Command Register 66 */ 67 #define USBCMD_REG_MAXPKT_64 0x0080 68 #define USBCMD_REG_CONFIG_FLAG 0x0040 69 #define USBCMD_REG_SW_DEBUG 0x0020 70 #define USBCMD_REG_FGBL_RESUME 0x0010 71 #define USBCMD_REG_ENTER_GBL_SUSPEND 0x0008 72 #define USBCMD_REG_GBL_RESET 0x0004 73 #define USBCMD_REG_HC_RESET 0x0002 74 #define USBCMD_REG_HC_RUN 0x0001 75 76 77 /* 78 * #defines for the USB Status Register 79 */ 80 #define USBSTS_REG_HC_HALTED 0x0020 81 #define USBSTS_REG_HC_PROCESS_ERR 0x0010 82 #define USBSTS_REG_HOST_SYS_ERR 0x0008 83 #define USBSTS_REG_RESUME_DETECT 0x0004 84 #define USBSTS_REG_USB_ERR_INTR 0x0002 85 #define USBSTS_REG_USB_INTR 0x0001 86 87 /* 88 * #defines for the USB Root Hub Port Register 89 */ 90 #define HCR_PORT_CCS 0x1 91 #define HCR_PORT_CSC 0x2 92 #define HCR_PORT_ENABLE 0x4 93 #define HCR_PORT_ENDIS_CHG 0x8 94 #define HCR_PORT_LINE_STATSU 0x30 95 #define HCR_PORT_RESUME_DETECT 0x40 96 #define HCR_PORT_LSDA 0x100 97 #define HCR_PORT_RESET 0x200 98 #define HCR_PORT_SUSPEND 0x1000 99 100 /* 101 * #defines for USB Interrupt Enable Register 102 */ 103 #define USBINTR_REG_SPINT_EN 0x0008 104 #define USBINTR_REG_IOC_EN 0x0004 105 #define USBINTR_REG_RESUME_INT_EN 0x0002 106 #define USBINTR_REG_TOCRC_INT_EN 0x0001 107 108 #define ENABLE_ALL_INTRS 0x000F 109 #define DISABLE_ALL_INTRS 0x0000 110 #define UHCI_INTR_MASK 0x1f 111 112 113 #define SetReg32(hndl, addr, val) ddi_put32((hndl), \ 114 &(addr), (val)) 115 #define GetReg32(hndl, addr) ddi_get32((hndl), &(addr)) 116 117 #define SetQH32(ucp, addr, val) \ 118 SetReg32((ucp)->uhci_qh_pool_mem_handle, (addr), (val)) 119 #define GetQH32(ucp, addr) \ 120 GetReg32((ucp)->uhci_qh_pool_mem_handle, (addr)) 121 122 #define SetTD32(ucp, addr, val) \ 123 SetReg32((ucp)->uhci_td_pool_mem_handle, (addr), (val)) 124 #define GetTD32(ucp, addr) \ 125 GetReg32((ucp)->uhci_td_pool_mem_handle, (addr)) 126 127 #define SetFL32(ucp, addr, val) \ 128 SetReg32((ucp)->uhci_flt_mem_handle, (addr), (val)) 129 #define GetFL32(ucp, addr) \ 130 GetReg32((ucp)->uhci_flt_mem_handle, (addr)) 131 132 133 /* 134 * UHCI Queue Head structure, aligned on 16 byte boundary 135 */ 136 typedef struct uhci_qh { 137 /* Hardware controlled bits */ 138 uint32_t link_ptr; /* Next Queue Head / TD */ 139 uint32_t element_ptr; /* Next queue head / TD */ 140 141 /* Software controlled bits */ 142 uint16_t node; /* Node that its attached */ 143 uint16_t qh_flag; /* See below */ 144 145 struct uhci_qh *prev_qh; /* Pointer to Prev queue head */ 146 struct uhci_td *td_tailp; /* Pointer to the last TD of QH */ 147 struct uhci_bulk_isoc_xfer_info *bulk_xfer_info; 148 uint64_t __pad1; /* align to 16 bytes */ 149 } queue_head_t; 150 151 #define NUM_STATIC_NODES 63 152 #define NUM_INTR_QH_LISTS 64 153 #define NUM_FRAME_LST_ENTRIES 1024 154 #define TREE_HEIGHT 5 155 #define VIRTUAL_TREE_HEIGHT 5 156 #define SIZE_OF_FRAME_LST_TABLE 1024 * 4 157 158 #define HC_TD_HEAD 0x0 159 #define HC_QUEUE_HEAD 0x2 160 #define HC_DEPTH_FIRST 0x4 161 #define HC_END_OF_LIST 0x1 162 163 #define QUEUE_HEAD_FLAG_STATIC 0x1 164 #define QUEUE_HEAD_FLAG_FREE 0x2 165 #define QUEUE_HEAD_FLAG_BUSY 0x3 166 167 #define QH_LINK_PTR_MASK 0xFFFFFFF0 168 #define QH_ELEMENT_PTR_MASK 0xFFFFFFF0 169 #define FRAME_LST_PTR_MASK 0xFFFFFFF0 170 171 172 #define GetField(u, td, f, o, l) \ 173 ((GetTD32(u, (td)->f) >> (o)) & ((1U<<l)-1)) 174 175 #define SetField(u, td, f, o, l, v) \ 176 SetTD32(u, (td)->f, \ 177 (GetTD32(u, (td)->f) & ~(((1U<<l)-1) << o)) | \ 178 (((v) & ((1U<<l)-1)) << o)) 179 180 #define GetTD_alen(u, td) GetField((u), (td), dw2, 0, 11) 181 #define GetTD_status(u, td) GetField((u), (td), dw2, 16, 8) 182 #define GetTD_ioc(u, td) GetField((u), (td), dw2, 24, 1) 183 #define GetTD_iso(u, td) GetField((u), (td), dw2, 25, 1) 184 #define GetTD_ls(u, td) GetField((u), (td), dw2, 26, 1) 185 #define GetTD_c_err(u, td) GetField((u), (td), dw2, 27, 2) 186 #define GetTD_spd(u, td) GetField((u), (td), dw2, 29, 1) 187 #define GetTD_PID(u, td) GetField((u), (td), dw3, 0, 8) 188 #define GetTD_devaddr(u, td) GetField((u), (td), dw3, 8, 7) 189 #define GetTD_endpt(u, td) GetField((u), (td), dw3, 15, 4) 190 #define GetTD_dtogg(u, td) GetField((u), (td), dw3, 19, 1) 191 #define GetTD_mlen(u, td) GetField((u), (td), dw3, 21, 11) 192 193 #define SetTD_alen(u, td, v) SetField((u), (td), dw2, 0, 11, (v)) 194 #define SetTD_status(u, td, v) SetField((u), (td), dw2, 16, 8, (v)) 195 #define SetTD_ioc(u, td, v) SetField((u), (td), dw2, 24, 1, (v)) 196 #define SetTD_iso(u, td, v) SetField((u), (td), dw2, 25, 1, (v)) 197 #define SetTD_ls(u, td, v) SetField((u), (td), dw2, 26, 1, (v)) 198 #define SetTD_c_err(u, td, v) SetField((u), (td), dw2, 27, 2, (v)) 199 #define SetTD_spd(u, td, v) SetField((u), (td), dw2, 29, 1, (v)) 200 #define SetTD_PID(u, td, v) SetField((u), (td), dw3, 0, 8, (v)) 201 #define SetTD_devaddr(u, td, v) SetField((u), (td), dw3, 8, 7, (v)) 202 #define SetTD_endpt(u, td, v) SetField((u), (td), dw3, 15, 4, (v)) 203 #define SetTD_dtogg(u, td, v) SetField((u), (td), dw3, 19, 1, (v)) 204 #define SetTD_mlen(u, td, v) SetField((u), (td), dw3, 21, 11, (v)) 205 206 /* 207 * UHCI Transfer Descriptor structure, aligned on 16 byte boundary 208 */ 209 typedef struct uhci_td { 210 211 /* Information required by HC for executing the request */ 212 /* Pointer to the next TD/QH */ 213 uint32_t link_ptr; 214 uint32_t dw2; 215 uint32_t dw3; 216 /* Data buffer address */ 217 uint32_t buffer_address; 218 219 /* Information required by HCD for managing the request */ 220 struct uhci_td *qh_td_prev; 221 struct uhci_td *tw_td_next; 222 struct uhci_td *outst_td_next; 223 struct uhci_td *outst_td_prev; 224 struct uhci_trans_wrapper *tw; 225 struct uhci_td *isoc_next; 226 struct uhci_td *isoc_prev; 227 ushort_t isoc_pkt_index; 228 ushort_t flag; 229 uint_t starting_frame; 230 uint_t _pad[3]; /* 16 byte alignment */ 231 } uhci_td_t; 232 233 #define TD_FLAG_FREE 0x1 234 #define TD_FLAG_BUSY 0x2 235 #define TD_FLAG_DUMMY 0x3 236 237 #define INTERRUPT_ON_COMPLETION 0x1 238 #define END_POINT_ADDRESS_MASK 0xF 239 #define UHCI_MAX_ERR_COUNT 3 240 #define MAX_NUM_BULK_TDS_PER_XFER 128 241 242 /* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */ 243 #define UHCI_TD_ACTIVE 0x80 244 #define UHCI_TD_STALLED 0x40 245 #define UHCI_TD_DATA_BUFFER_ERR 0x20 246 #define UHCI_TD_BABBLE_ERR 0x10 247 #define UHCI_TD_NAK_RECEIVED 0x08 248 #define UHCI_TD_CRC_TIMEOUT 0x04 249 #define UHCI_TD_BITSTUFF_ERR 0x02 250 251 #define TD_INACTIVE 0x7F 252 #define TD_STATUS_MASK 0x76 253 #define ZERO_LENGTH 0x7FF 254 255 #define PID_SETUP 0x2D 256 #define PID_IN 0x69 257 #define PID_OUT 0xe1 258 259 #define SETUP_SIZE 8 260 261 #define SETUP 0x11 262 #define DATA 0x12 263 #define STATUS 0x13 264 265 #define UHCI_INVALID_PTR NULL 266 #define LOW_SPEED_DEVICE 1 267 268 /* 269 * These provide synchronization between TD deletions. 270 */ 271 #define UHCI_NOT_CLAIMED 0x0 272 #define UHCI_INTR_HDLR_CLAIMED 0x1 273 #define UHCI_MODIFY_TD_BITS_CLAIMED 0x2 274 #define UHCI_TIMEOUT_HDLR_CLAIMED 0x3 275 276 277 /* 278 * Structure for Bulk and Isoc TD pools 279 */ 280 typedef struct uhci_bulk_isoc_td_pool { 281 caddr_t pool_addr; 282 ddi_dma_cookie_t cookie; /* DMA cookie */ 283 ddi_dma_handle_t dma_handle; /* DMA handle */ 284 ddi_acc_handle_t mem_handle; /* Memory handle */ 285 ushort_t num_tds; 286 } uhci_bulk_isoc_td_pool_t; 287 288 /* 289 * Structure for Bulk and Isoc transfers 290 */ 291 typedef struct uhci_bulk_isoc_xfer_info { 292 uhci_bulk_isoc_td_pool_t *td_pools; 293 ushort_t num_pools; 294 ushort_t num_tds; 295 } uhci_bulk_isoc_xfer_t; 296 297 /* 298 * Structure for Isoc DMA buffer 299 * One Isoc transfer includes multiple Isoc packets. 300 * One DMA buffer is allocated for one packet each. 301 */ 302 typedef struct uhci_isoc_buf { 303 caddr_t buf_addr; /* Starting buffer address */ 304 ddi_dma_cookie_t cookie; /* DMA cookie */ 305 ddi_dma_handle_t dma_handle; /* DMA handle */ 306 ddi_acc_handle_t mem_handle; /* Memory handle */ 307 size_t length; /* Buffer length */ 308 ushort_t index; 309 } uhci_isoc_buf_t; 310 311 /* 312 * Macros related to ISOC transfers 313 */ 314 #define UHCI_SIZE_OF_HW_FRNUM 11 315 #define UHCI_BIT_10_MASK 0x400 316 #define UHCI_MAX_ISOC_FRAMES 1024 317 #define UHCI_MAX_ISOC_PKTS 256 318 #define UHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 319 320 #define FRNUM_MASK 0x3FF 321 #define SW_FRNUM_MASK 0xFFFFFFFFFFFFF800 322 #define INVALID_FRNUM 0 323 #define FRNUM_OFFSET 5 324 #define MAX_FRAME_NUM 1023 325 326 typedef uint32_t frame_lst_table_t; 327 328 /* 329 * Bandwidth allocation 330 * The following definitions are used during bandwidth 331 * calculations for a given endpoint maximum packet size. 332 */ 333 #define MAX_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 334 #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 335 #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 336 #define SOF 6 /* Length in bytes of SOF */ 337 #define EOF 2 /* Length in bytes of EOF */ 338 339 /* 340 * Minimum polling interval for low speed endpoint 341 * 342 * According USB Specifications, a full-speed endpoint can specify 343 * a desired polling interval 1ms to 255ms and a low speed endpoints 344 * are limited to specifying only 10ms to 255ms. But some old keyboards 345 * and mice uses polling interval of 8ms. For compatibility purpose, 346 * we are using polling interval between 8ms and 255ms for low speed 347 * endpoints. 348 */ 349 #define MIN_LOW_SPEED_POLL_INTERVAL 8 350 351 /* 352 * For non-periodic transfers, reserve at least for one low-speed device 353 * transaction and according to USB Bandwidth Analysis white paper, it 354 * comes around 12% of USB frame time. Then periodic transfers will get 355 * 88% of USB frame time. 356 */ 357 #define MAX_PERIODIC_BANDWIDTH (((MAX_BUS_BANDWIDTH - SOF - EOF)*88)/100) 358 359 /* 360 * The following are the protocol overheads in terms of Bytes for the 361 * different transfer types. All these protocol overhead values are 362 * derived from the 5.9.3 section of USB Specification and with the 363 * help of Bandwidth Analysis white paper which is posted on the USB 364 * developer forum. 365 */ 366 #define FS_NON_ISOC_PROTO_OVERHEAD 14 367 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 368 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 369 #define LOW_SPEED_PROTO_OVERHEAD 97 370 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 371 372 /* 373 * The Host Controller (HC) delays are the USB host controller specific 374 * delays. The value shown below is the host controller delay for the 375 * Sand core USB host controller. 376 */ 377 #define HOST_CONTROLLER_DELAY 18 378 379 /* 380 * The low speed clock below represents that to transmit one low-speed 381 * bit takes eight times more than one full speed bit time. 382 */ 383 #define LOW_SPEED_CLOCK 8 384 385 /* the 16 byte alignment is required for every TD and QH start addr */ 386 #define UHCI_QH_ALIGN_SZ 16 387 #define UHCI_TD_ALIGN_SZ 16 388 389 #ifdef __cplusplus 390 } 391 #endif 392 393 #endif /* _SYS_USB_UHCI_H */ 394