1 /* $NetBSD: dc_ddc_types.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef DC_DDC_TYPES_H_ 28 #define DC_DDC_TYPES_H_ 29 30 enum aux_transaction_type { 31 AUX_TRANSACTION_TYPE_DP, 32 AUX_TRANSACTION_TYPE_I2C 33 }; 34 35 36 enum i2caux_transaction_action { 37 I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00, 38 I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10, 39 I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20, 40 41 I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40, 42 I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50, 43 I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60, 44 45 I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80, 46 I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90 47 }; 48 49 enum aux_channel_operation_result { 50 AUX_CHANNEL_OPERATION_SUCCEEDED, 51 AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN, 52 AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY, 53 AUX_CHANNEL_OPERATION_FAILED_TIMEOUT, 54 AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON, 55 AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE 56 }; 57 58 59 struct aux_request_transaction_data { 60 enum aux_transaction_type type; 61 enum i2caux_transaction_action action; 62 /* 20-bit AUX channel transaction address */ 63 uint32_t address; 64 /* delay, in 100-microsecond units */ 65 uint8_t delay; 66 uint32_t length; 67 uint8_t *data; 68 }; 69 70 enum aux_transaction_reply { 71 AUX_TRANSACTION_REPLY_AUX_ACK = 0x00, 72 AUX_TRANSACTION_REPLY_AUX_NACK = 0x01, 73 AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02, 74 AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK = 0x04, 75 AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER = 0x08, 76 77 AUX_TRANSACTION_REPLY_I2C_ACK = 0x00, 78 AUX_TRANSACTION_REPLY_I2C_NACK = 0x10, 79 AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20, 80 81 AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40, 82 83 AUX_TRANSACTION_REPLY_INVALID = 0xFF 84 }; 85 86 struct aux_reply_transaction_data { 87 enum aux_transaction_reply status; 88 uint32_t length; 89 uint8_t *data; 90 }; 91 92 struct i2c_payload { 93 bool write; 94 uint8_t address; 95 uint32_t length; 96 uint8_t *data; 97 }; 98 99 enum i2c_command_engine { 100 I2C_COMMAND_ENGINE_DEFAULT, 101 I2C_COMMAND_ENGINE_SW, 102 I2C_COMMAND_ENGINE_HW 103 }; 104 105 struct i2c_command { 106 struct i2c_payload *payloads; 107 uint8_t number_of_payloads; 108 109 enum i2c_command_engine engine; 110 111 /* expressed in KHz 112 * zero means "use default value" */ 113 uint32_t speed; 114 }; 115 116 struct gpio_ddc_hw_info { 117 bool hw_supported; 118 uint32_t ddc_channel; 119 }; 120 121 struct ddc { 122 struct gpio *pin_data; 123 struct gpio *pin_clock; 124 struct gpio_ddc_hw_info hw_info; 125 struct dc_context *ctx; 126 }; 127 128 union ddc_wa { 129 struct { 130 uint32_t DP_SKIP_POWER_OFF:1; 131 uint32_t DP_AUX_POWER_UP_WA_DELAY:1; 132 } bits; 133 uint32_t raw; 134 }; 135 136 struct ddc_flags { 137 uint8_t EDID_QUERY_DONE_ONCE:1; 138 uint8_t IS_INTERNAL_DISPLAY:1; 139 uint8_t FORCE_READ_REPEATED_START:1; 140 uint8_t EDID_STRESS_READ:1; 141 142 }; 143 144 enum ddc_transaction_type { 145 DDC_TRANSACTION_TYPE_NONE = 0, 146 DDC_TRANSACTION_TYPE_I2C, 147 DDC_TRANSACTION_TYPE_I2C_OVER_AUX, 148 DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER, 149 DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER 150 }; 151 152 enum display_dongle_type { 153 DISPLAY_DONGLE_NONE = 0, 154 /* Active converter types*/ 155 DISPLAY_DONGLE_DP_VGA_CONVERTER, 156 DISPLAY_DONGLE_DP_DVI_CONVERTER, 157 DISPLAY_DONGLE_DP_HDMI_CONVERTER, 158 /* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/ 159 DISPLAY_DONGLE_DP_DVI_DONGLE, 160 DISPLAY_DONGLE_DP_HDMI_DONGLE, 161 /* Other types of dongle*/ 162 DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE, 163 }; 164 165 struct ddc_service { 166 struct ddc *ddc_pin; 167 struct ddc_flags flags; 168 union ddc_wa wa; 169 enum ddc_transaction_type transaction_type; 170 enum display_dongle_type dongle_type; 171 struct dc_context *ctx; 172 struct dc_link *link; 173 174 uint32_t address; 175 uint32_t edid_buf_len; 176 uint8_t edid_buf[DC_MAX_EDID_BUFFER_SIZE]; 177 }; 178 179 #endif /* DC_DDC_TYPES_H_ */ 180