1 /* $NetBSD: ddc_service_types.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef __DAL_DDC_SERVICE_TYPES_H__ 28 #define __DAL_DDC_SERVICE_TYPES_H__ 29 30 /* 0010FA dongles (ST Micro) external converter chip id */ 31 #define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA 32 /* 0022B9 external converter chip id */ 33 #define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9 34 #define DP_BRANCH_DEVICE_ID_00001A 0x00001A 35 #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1 36 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24 37 #define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C 38 39 enum ddc_result { 40 DDC_RESULT_UNKNOWN = 0, 41 DDC_RESULT_SUCESSFULL, 42 DDC_RESULT_FAILED_CHANNEL_BUSY, 43 DDC_RESULT_FAILED_TIMEOUT, 44 DDC_RESULT_FAILED_PROTOCOL_ERROR, 45 DDC_RESULT_FAILED_NACK, 46 DDC_RESULT_FAILED_INCOMPLETE, 47 DDC_RESULT_FAILED_OPERATION, 48 DDC_RESULT_FAILED_INVALID_OPERATION, 49 DDC_RESULT_FAILED_BUFFER_OVERFLOW, 50 DDC_RESULT_FAILED_HPD_DISCON 51 }; 52 53 enum ddc_service_type { 54 DDC_SERVICE_TYPE_CONNECTOR, 55 DDC_SERVICE_TYPE_DISPLAY_PORT_MST, 56 }; 57 58 /** 59 * display sink capability 60 */ 61 struct display_sink_capability { 62 /* dongle type (DP converter, CV smart dongle) */ 63 enum display_dongle_type dongle_type; 64 65 /********************************************************** 66 capabilities going INTO SINK DEVICE (stream capabilities) 67 **********************************************************/ 68 /* Dongle's downstream count. */ 69 uint32_t downstrm_sink_count; 70 /* Is dongle's downstream count info field (downstrm_sink_count) 71 * valid. */ 72 bool downstrm_sink_count_valid; 73 74 /* Maximum additional audio delay in microsecond (us) */ 75 uint32_t additional_audio_delay; 76 /* Audio latency value in microsecond (us) */ 77 uint32_t audio_latency; 78 /* Interlace video latency value in microsecond (us) */ 79 uint32_t video_latency_interlace; 80 /* Progressive video latency value in microsecond (us) */ 81 uint32_t video_latency_progressive; 82 /* Dongle caps: Maximum pixel clock supported over dongle for HDMI */ 83 uint32_t max_hdmi_pixel_clock; 84 /* Dongle caps: Maximum deep color supported over dongle for HDMI */ 85 enum dc_color_depth max_hdmi_deep_color; 86 87 /************************************************************ 88 capabilities going OUT OF SOURCE DEVICE (link capabilities) 89 ************************************************************/ 90 /* support for Spread Spectrum(SS) */ 91 bool ss_supported; 92 /* DP link settings (laneCount, linkRate, Spread) */ 93 uint32_t dp_link_lane_count; 94 uint32_t dp_link_rate; 95 uint32_t dp_link_spead; 96 97 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 98 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 99 bool is_dp_hdmi_s3d_converter; 100 /* to check if we have queried the display capability 101 * for eDP panel already. */ 102 bool is_edp_sink_cap_valid; 103 104 enum ddc_transaction_type transaction_type; 105 enum signal_type signal; 106 }; 107 108 struct av_sync_data { 109 uint8_t av_granularity;/* DPCD 00023h */ 110 uint8_t aud_dec_lat1;/* DPCD 00024h */ 111 uint8_t aud_dec_lat2;/* DPCD 00025h */ 112 uint8_t aud_pp_lat1;/* DPCD 00026h */ 113 uint8_t aud_pp_lat2;/* DPCD 00027h */ 114 uint8_t vid_inter_lat;/* DPCD 00028h */ 115 uint8_t vid_prog_lat;/* DPCD 00029h */ 116 uint8_t aud_del_ins1;/* DPCD 0002Bh */ 117 uint8_t aud_del_ins2;/* DPCD 0002Ch */ 118 uint8_t aud_del_ins3;/* DPCD 0002Dh */ 119 }; 120 121 /*Travis*/ 122 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; 123 /*Nutmeg*/ 124 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; 125 /*DP to Dual link DVI converter*/ 126 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; 127 128 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ 129