1 /*	$NetBSD: drm_dp_helper.h,v 1.9 2021/12/19 12:41:54 riastradh Exp $	*/
2 
3 /*
4  * Copyright © 2008 Keith Packard
5  *
6  * Permission to use, copy, modify, distribute, and sell this software and its
7  * documentation for any purpose is hereby granted without fee, provided that
8  * the above copyright notice appear in all copies and that both that copyright
9  * notice and this permission notice appear in supporting documentation, and
10  * that the name of the copyright holders not be used in advertising or
11  * publicity pertaining to distribution of the software without specific,
12  * written prior permission.  The copyright holders make no representations
13  * about the suitability of this software for any purpose.  It is provided "as
14  * is" without express or implied warranty.
15  *
16  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
17  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
18  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
19  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
20  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
21  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
22  * OF THIS SOFTWARE.
23  */
24 
25 #ifndef _DRM_DP_HELPER_H_
26 #define _DRM_DP_HELPER_H_
27 
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/types.h>
31 #include <linux/workqueue.h>
32 
33 struct seq_file;
34 
35 /*
36  * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
37  * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
38  * 1.0 devices basically don't exist in the wild.
39  *
40  * Abbreviations, in chronological order:
41  *
42  * eDP: Embedded DisplayPort version 1
43  * DPI: DisplayPort Interoperability Guideline v1.1a
44  * 1.2: DisplayPort 1.2
45  * MST: Multistream Transport - part of DP 1.2a
46  *
47  * 1.2 formally includes both eDP and DPI definitions.
48  */
49 
50 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
51 #define DP_MSA_MISC_SYNC_CLOCK			(1 << 0)
52 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN	(1 << 8)
53 #define DP_MSA_MISC_STEREO_NO_3D		(0 << 9)
54 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE	(1 << 9)
55 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE	(3 << 9)
56 /* bits per component for non-RAW */
57 #define DP_MSA_MISC_6_BPC			(0 << 5)
58 #define DP_MSA_MISC_8_BPC			(1 << 5)
59 #define DP_MSA_MISC_10_BPC			(2 << 5)
60 #define DP_MSA_MISC_12_BPC			(3 << 5)
61 #define DP_MSA_MISC_16_BPC			(4 << 5)
62 /* bits per component for RAW */
63 #define DP_MSA_MISC_RAW_6_BPC			(1 << 5)
64 #define DP_MSA_MISC_RAW_7_BPC			(2 << 5)
65 #define DP_MSA_MISC_RAW_8_BPC			(3 << 5)
66 #define DP_MSA_MISC_RAW_10_BPC			(4 << 5)
67 #define DP_MSA_MISC_RAW_12_BPC			(5 << 5)
68 #define DP_MSA_MISC_RAW_14_BPC			(6 << 5)
69 #define DP_MSA_MISC_RAW_16_BPC			(7 << 5)
70 /* pixel encoding/colorimetry format */
71 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
72 	((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
73 #define DP_MSA_MISC_COLOR_RGB			_DP_MSA_MISC_COLOR(0, 0, 0, 0)
74 #define DP_MSA_MISC_COLOR_CEA_RGB		_DP_MSA_MISC_COLOR(0, 0, 1, 0)
75 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED	_DP_MSA_MISC_COLOR(0, 3, 0, 0)
76 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT	_DP_MSA_MISC_COLOR(0, 3, 0, 1)
77 #define DP_MSA_MISC_COLOR_Y_ONLY		_DP_MSA_MISC_COLOR(1, 0, 0, 0)
78 #define DP_MSA_MISC_COLOR_RAW			_DP_MSA_MISC_COLOR(1, 1, 0, 0)
79 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601	_DP_MSA_MISC_COLOR(0, 1, 1, 0)
80 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709	_DP_MSA_MISC_COLOR(0, 1, 1, 1)
81 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601	_DP_MSA_MISC_COLOR(0, 2, 1, 0)
82 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709	_DP_MSA_MISC_COLOR(0, 2, 1, 1)
83 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601	_DP_MSA_MISC_COLOR(0, 1, 0, 0)
84 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709	_DP_MSA_MISC_COLOR(0, 1, 0, 1)
85 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601	_DP_MSA_MISC_COLOR(0, 2, 0, 0)
86 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709	_DP_MSA_MISC_COLOR(0, 2, 0, 1)
87 #define DP_MSA_MISC_COLOR_OPRGB			_DP_MSA_MISC_COLOR(0, 0, 1, 1)
88 #define DP_MSA_MISC_COLOR_DCI_P3		_DP_MSA_MISC_COLOR(0, 3, 1, 0)
89 #define DP_MSA_MISC_COLOR_COLOR_PROFILE		_DP_MSA_MISC_COLOR(0, 3, 1, 1)
90 #define DP_MSA_MISC_COLOR_VSC_SDP		(1 << 14)
91 
92 #define DP_AUX_MAX_PAYLOAD_BYTES	16
93 
94 #define DP_AUX_I2C_WRITE		0x0
95 #define DP_AUX_I2C_READ			0x1
96 #define DP_AUX_I2C_WRITE_STATUS_UPDATE	0x2
97 #define DP_AUX_I2C_MOT			0x4
98 #define DP_AUX_NATIVE_WRITE		0x8
99 #define DP_AUX_NATIVE_READ		0x9
100 
101 #define DP_AUX_NATIVE_REPLY_ACK		(0x0 << 0)
102 #define DP_AUX_NATIVE_REPLY_NACK	(0x1 << 0)
103 #define DP_AUX_NATIVE_REPLY_DEFER	(0x2 << 0)
104 #define DP_AUX_NATIVE_REPLY_MASK	(0x3 << 0)
105 
106 #define DP_AUX_I2C_REPLY_ACK		(0x0 << 2)
107 #define DP_AUX_I2C_REPLY_NACK		(0x1 << 2)
108 #define DP_AUX_I2C_REPLY_DEFER		(0x2 << 2)
109 #define DP_AUX_I2C_REPLY_MASK		(0x3 << 2)
110 
111 /* AUX CH addresses */
112 /* DPCD */
113 #define DP_DPCD_REV                         0x000
114 # define DP_DPCD_REV_10                     0x10
115 # define DP_DPCD_REV_11                     0x11
116 # define DP_DPCD_REV_12                     0x12
117 # define DP_DPCD_REV_13                     0x13
118 # define DP_DPCD_REV_14                     0x14
119 
120 #define DP_MAX_LINK_RATE                    0x001
121 
122 #define DP_MAX_LANE_COUNT                   0x002
123 # define DP_MAX_LANE_COUNT_MASK		    0x1f
124 # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
125 # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
126 
127 #define DP_MAX_DOWNSPREAD                   0x003
128 # define DP_MAX_DOWNSPREAD_0_5		    (1 << 0)
129 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
130 # define DP_TPS4_SUPPORTED                  (1 << 7)
131 
132 #define DP_NORP                             0x004
133 
134 #define DP_DOWNSTREAMPORT_PRESENT           0x005
135 # define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
136 # define DP_DWN_STRM_PORT_TYPE_MASK         0x06
137 # define DP_DWN_STRM_PORT_TYPE_DP           (0 << 1)
138 # define DP_DWN_STRM_PORT_TYPE_ANALOG       (1 << 1)
139 # define DP_DWN_STRM_PORT_TYPE_TMDS         (2 << 1)
140 # define DP_DWN_STRM_PORT_TYPE_OTHER        (3 << 1)
141 # define DP_FORMAT_CONVERSION               (1 << 3)
142 # define DP_DETAILED_CAP_INFO_AVAILABLE	    (1 << 4) /* DPI */
143 
144 #define DP_MAIN_LINK_CHANNEL_CODING         0x006
145 # define DP_CAP_ANSI_8B10B		    (1 << 0)
146 
147 #define DP_DOWN_STREAM_PORT_COUNT	    0x007
148 # define DP_PORT_COUNT_MASK		    0x0f
149 # define DP_MSA_TIMING_PAR_IGNORED	    (1 << 6) /* eDP */
150 # define DP_OUI_SUPPORT			    (1 << 7)
151 
152 #define DP_RECEIVE_PORT_0_CAP_0		    0x008
153 # define DP_LOCAL_EDID_PRESENT		    (1 << 1)
154 # define DP_ASSOCIATED_TO_PRECEDING_PORT    (1 << 2)
155 
156 #define DP_RECEIVE_PORT_0_BUFFER_SIZE	    0x009
157 
158 #define DP_RECEIVE_PORT_1_CAP_0		    0x00a
159 #define DP_RECEIVE_PORT_1_BUFFER_SIZE       0x00b
160 
161 #define DP_I2C_SPEED_CAP		    0x00c    /* DPI */
162 # define DP_I2C_SPEED_1K		    0x01
163 # define DP_I2C_SPEED_5K		    0x02
164 # define DP_I2C_SPEED_10K		    0x04
165 # define DP_I2C_SPEED_100K		    0x08
166 # define DP_I2C_SPEED_400K		    0x10
167 # define DP_I2C_SPEED_1M		    0x20
168 
169 #define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
170 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP   (1 << 0)
171 # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
172 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
173 
174 #define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
175 # define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
176 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT	(1 << 7) /* DP 1.3 */
177 
178 #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
179 # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
180 # define DP_ALTERNATE_I2C_PATTERN_CAP	    (1 << 1)
181 
182 #define DP_SUPPORTED_LINK_RATES		    0x010 /* eDP 1.4 */
183 # define DP_MAX_SUPPORTED_RATES		     8	    /* 16-bit little-endian */
184 
185 /* Multiple stream transport */
186 #define DP_FAUX_CAP			    0x020   /* 1.2 */
187 # define DP_FAUX_CAP_1			    (1 << 0)
188 
189 #define DP_MSTM_CAP			    0x021   /* 1.2 */
190 # define DP_MST_CAP			    (1 << 0)
191 
192 #define DP_NUMBER_OF_AUDIO_ENDPOINTS	    0x022   /* 1.2 */
193 
194 /* AV_SYNC_DATA_BLOCK                                  1.2 */
195 #define DP_AV_GRANULARITY		    0x023
196 # define DP_AG_FACTOR_MASK		    (0xf << 0)
197 # define DP_AG_FACTOR_3MS		    (0 << 0)
198 # define DP_AG_FACTOR_2MS		    (1 << 0)
199 # define DP_AG_FACTOR_1MS		    (2 << 0)
200 # define DP_AG_FACTOR_500US		    (3 << 0)
201 # define DP_AG_FACTOR_200US		    (4 << 0)
202 # define DP_AG_FACTOR_100US		    (5 << 0)
203 # define DP_AG_FACTOR_10US		    (6 << 0)
204 # define DP_AG_FACTOR_1US		    (7 << 0)
205 # define DP_VG_FACTOR_MASK		    (0xf << 4)
206 # define DP_VG_FACTOR_3MS		    (0 << 4)
207 # define DP_VG_FACTOR_2MS		    (1 << 4)
208 # define DP_VG_FACTOR_1MS		    (2 << 4)
209 # define DP_VG_FACTOR_500US		    (3 << 4)
210 # define DP_VG_FACTOR_200US		    (4 << 4)
211 # define DP_VG_FACTOR_100US		    (5 << 4)
212 
213 #define DP_AUD_DEC_LAT0			    0x024
214 #define DP_AUD_DEC_LAT1			    0x025
215 
216 #define DP_AUD_PP_LAT0			    0x026
217 #define DP_AUD_PP_LAT1			    0x027
218 
219 #define DP_VID_INTER_LAT		    0x028
220 
221 #define DP_VID_PROG_LAT			    0x029
222 
223 #define DP_REP_LAT			    0x02a
224 
225 #define DP_AUD_DEL_INS0			    0x02b
226 #define DP_AUD_DEL_INS1			    0x02c
227 #define DP_AUD_DEL_INS2			    0x02d
228 /* End of AV_SYNC_DATA_BLOCK */
229 
230 #define DP_RECEIVER_ALPM_CAP		    0x02e   /* eDP 1.4 */
231 # define DP_ALPM_CAP			    (1 << 0)
232 
233 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP   0x02f   /* eDP 1.4 */
234 # define DP_AUX_FRAME_SYNC_CAP		    (1 << 0)
235 
236 #define DP_GUID				    0x030   /* 1.2 */
237 
238 #define DP_DSC_SUPPORT                      0x060   /* DP 1.4 */
239 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
240 
241 #define DP_DSC_REV                          0x061
242 # define DP_DSC_MAJOR_MASK                  (0xf << 0)
243 # define DP_DSC_MINOR_MASK                  (0xf << 4)
244 # define DP_DSC_MAJOR_SHIFT                 0
245 # define DP_DSC_MINOR_SHIFT                 4
246 
247 #define DP_DSC_RC_BUF_BLK_SIZE              0x062
248 # define DP_DSC_RC_BUF_BLK_SIZE_1           0x0
249 # define DP_DSC_RC_BUF_BLK_SIZE_4           0x1
250 # define DP_DSC_RC_BUF_BLK_SIZE_16          0x2
251 # define DP_DSC_RC_BUF_BLK_SIZE_64          0x3
252 
253 #define DP_DSC_RC_BUF_SIZE                  0x063
254 
255 #define DP_DSC_SLICE_CAP_1                  0x064
256 # define DP_DSC_1_PER_DP_DSC_SINK           (1 << 0)
257 # define DP_DSC_2_PER_DP_DSC_SINK           (1 << 1)
258 # define DP_DSC_4_PER_DP_DSC_SINK           (1 << 3)
259 # define DP_DSC_6_PER_DP_DSC_SINK           (1 << 4)
260 # define DP_DSC_8_PER_DP_DSC_SINK           (1 << 5)
261 # define DP_DSC_10_PER_DP_DSC_SINK          (1 << 6)
262 # define DP_DSC_12_PER_DP_DSC_SINK          (1 << 7)
263 
264 #define DP_DSC_LINE_BUF_BIT_DEPTH           0x065
265 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK     (0xf << 0)
266 # define DP_DSC_LINE_BUF_BIT_DEPTH_9        0x0
267 # define DP_DSC_LINE_BUF_BIT_DEPTH_10       0x1
268 # define DP_DSC_LINE_BUF_BIT_DEPTH_11       0x2
269 # define DP_DSC_LINE_BUF_BIT_DEPTH_12       0x3
270 # define DP_DSC_LINE_BUF_BIT_DEPTH_13       0x4
271 # define DP_DSC_LINE_BUF_BIT_DEPTH_14       0x5
272 # define DP_DSC_LINE_BUF_BIT_DEPTH_15       0x6
273 # define DP_DSC_LINE_BUF_BIT_DEPTH_16       0x7
274 # define DP_DSC_LINE_BUF_BIT_DEPTH_8        0x8
275 
276 #define DP_DSC_BLK_PREDICTION_SUPPORT       0x066
277 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
278 
279 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
280 
281 #define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
282 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0)
283 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
284 
285 #define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
286 # define DP_DSC_RGB                         (1 << 0)
287 # define DP_DSC_YCbCr444                    (1 << 1)
288 # define DP_DSC_YCbCr422_Simple             (1 << 2)
289 # define DP_DSC_YCbCr422_Native             (1 << 3)
290 # define DP_DSC_YCbCr420_Native             (1 << 4)
291 
292 #define DP_DSC_DEC_COLOR_DEPTH_CAP          0x06A
293 # define DP_DSC_8_BPC                       (1 << 1)
294 # define DP_DSC_10_BPC                      (1 << 2)
295 # define DP_DSC_12_BPC                      (1 << 3)
296 
297 #define DP_DSC_PEAK_THROUGHPUT              0x06B
298 # define DP_DSC_THROUGHPUT_MODE_0_MASK      (0xf << 0)
299 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT     0
300 # define DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED 0
301 # define DP_DSC_THROUGHPUT_MODE_0_340       (1 << 0)
302 # define DP_DSC_THROUGHPUT_MODE_0_400       (2 << 0)
303 # define DP_DSC_THROUGHPUT_MODE_0_450       (3 << 0)
304 # define DP_DSC_THROUGHPUT_MODE_0_500       (4 << 0)
305 # define DP_DSC_THROUGHPUT_MODE_0_550       (5 << 0)
306 # define DP_DSC_THROUGHPUT_MODE_0_600       (6 << 0)
307 # define DP_DSC_THROUGHPUT_MODE_0_650       (7 << 0)
308 # define DP_DSC_THROUGHPUT_MODE_0_700       (8 << 0)
309 # define DP_DSC_THROUGHPUT_MODE_0_750       (9 << 0)
310 # define DP_DSC_THROUGHPUT_MODE_0_800       (10 << 0)
311 # define DP_DSC_THROUGHPUT_MODE_0_850       (11 << 0)
312 # define DP_DSC_THROUGHPUT_MODE_0_900       (12 << 0)
313 # define DP_DSC_THROUGHPUT_MODE_0_950       (13 << 0)
314 # define DP_DSC_THROUGHPUT_MODE_0_1000      (14 << 0)
315 # define DP_DSC_THROUGHPUT_MODE_0_170       (15 << 0) /* 1.4a */
316 # define DP_DSC_THROUGHPUT_MODE_1_MASK      (0xf << 4)
317 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT     4
318 # define DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED 0
319 # define DP_DSC_THROUGHPUT_MODE_1_340       (1 << 4)
320 # define DP_DSC_THROUGHPUT_MODE_1_400       (2 << 4)
321 # define DP_DSC_THROUGHPUT_MODE_1_450       (3 << 4)
322 # define DP_DSC_THROUGHPUT_MODE_1_500       (4 << 4)
323 # define DP_DSC_THROUGHPUT_MODE_1_550       (5 << 4)
324 # define DP_DSC_THROUGHPUT_MODE_1_600       (6 << 4)
325 # define DP_DSC_THROUGHPUT_MODE_1_650       (7 << 4)
326 # define DP_DSC_THROUGHPUT_MODE_1_700       (8 << 4)
327 # define DP_DSC_THROUGHPUT_MODE_1_750       (9 << 4)
328 # define DP_DSC_THROUGHPUT_MODE_1_800       (10 << 4)
329 # define DP_DSC_THROUGHPUT_MODE_1_850       (11 << 4)
330 # define DP_DSC_THROUGHPUT_MODE_1_900       (12 << 4)
331 # define DP_DSC_THROUGHPUT_MODE_1_950       (13 << 4)
332 # define DP_DSC_THROUGHPUT_MODE_1_1000      (14 << 4)
333 # define DP_DSC_THROUGHPUT_MODE_1_170       (15 << 4)
334 
335 #define DP_DSC_MAX_SLICE_WIDTH              0x06C
336 #define DP_DSC_MIN_SLICE_WIDTH_VALUE        2560
337 #define DP_DSC_SLICE_WIDTH_MULTIPLIER       320
338 
339 #define DP_DSC_SLICE_CAP_2                  0x06D
340 # define DP_DSC_16_PER_DP_DSC_SINK          (1 << 0)
341 # define DP_DSC_20_PER_DP_DSC_SINK          (1 << 1)
342 # define DP_DSC_24_PER_DP_DSC_SINK          (1 << 2)
343 
344 #define DP_DSC_BITS_PER_PIXEL_INC           0x06F
345 # define DP_DSC_BITS_PER_PIXEL_1_16         0x0
346 # define DP_DSC_BITS_PER_PIXEL_1_8          0x1
347 # define DP_DSC_BITS_PER_PIXEL_1_4          0x2
348 # define DP_DSC_BITS_PER_PIXEL_1_2          0x3
349 # define DP_DSC_BITS_PER_PIXEL_1            0x4
350 
351 #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
352 # define DP_PSR_IS_SUPPORTED                1
353 # define DP_PSR2_IS_SUPPORTED		    2	    /* eDP 1.4 */
354 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED  3	    /* eDP 1.4a */
355 
356 #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
357 # define DP_PSR_NO_TRAIN_ON_EXIT            1
358 # define DP_PSR_SETUP_TIME_330              (0 << 1)
359 # define DP_PSR_SETUP_TIME_275              (1 << 1)
360 # define DP_PSR_SETUP_TIME_220              (2 << 1)
361 # define DP_PSR_SETUP_TIME_165              (3 << 1)
362 # define DP_PSR_SETUP_TIME_110              (4 << 1)
363 # define DP_PSR_SETUP_TIME_55               (5 << 1)
364 # define DP_PSR_SETUP_TIME_0                (6 << 1)
365 # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
366 # define DP_PSR_SETUP_TIME_SHIFT            1
367 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
368 # define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
369 
370 #define DP_PSR2_SU_X_GRANULARITY	    0x072 /* eDP 1.4b */
371 #define DP_PSR2_SU_Y_GRANULARITY	    0x074 /* eDP 1.4b */
372 
373 /*
374  * 0x80-0x8f describe downstream port capabilities, but there are two layouts
375  * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
376  * each port's descriptor is one byte wide.  If it was set, each port's is
377  * four bytes wide, starting with the one byte from the base info.  As of
378  * DP interop v1.1a only VGA defines additional detail.
379  */
380 
381 /* offset 0 */
382 #define DP_DOWNSTREAM_PORT_0		    0x80
383 # define DP_DS_PORT_TYPE_MASK		    (7 << 0)
384 # define DP_DS_PORT_TYPE_DP		    0
385 # define DP_DS_PORT_TYPE_VGA		    1
386 # define DP_DS_PORT_TYPE_DVI		    2
387 # define DP_DS_PORT_TYPE_HDMI		    3
388 # define DP_DS_PORT_TYPE_NON_EDID	    4
389 # define DP_DS_PORT_TYPE_DP_DUALMODE        5
390 # define DP_DS_PORT_TYPE_WIRELESS           6
391 # define DP_DS_PORT_HPD			    (1 << 3)
392 /* offset 1 for VGA is maximum megapixels per second / 8 */
393 /* offset 2 */
394 # define DP_DS_MAX_BPC_MASK	            (3 << 0)
395 # define DP_DS_8BPC		            0
396 # define DP_DS_10BPC		            1
397 # define DP_DS_12BPC		            2
398 # define DP_DS_16BPC		            3
399 
400 /* DP Forward error Correction Registers */
401 #define DP_FEC_CAPABILITY		    0x090    /* 1.4 */
402 # define DP_FEC_CAPABLE			    (1 << 0)
403 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
404 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
405 # define DP_FEC_BIT_ERROR_COUNT_CAP	    (1 << 3)
406 
407 /* DP Extended DSC Capabilities */
408 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
409 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
410 #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
411 
412 /* link configuration */
413 #define	DP_LINK_BW_SET		            0x100
414 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
415 # define DP_LINK_BW_1_62		    0x06
416 # define DP_LINK_BW_2_7			    0x0a
417 # define DP_LINK_BW_5_4			    0x14    /* 1.2 */
418 # define DP_LINK_BW_8_1			    0x1e    /* 1.4 */
419 
420 #define DP_LANE_COUNT_SET	            0x101
421 # define DP_LANE_COUNT_MASK		    0x0f
422 # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
423 
424 #define DP_TRAINING_PATTERN_SET	            0x102
425 # define DP_TRAINING_PATTERN_DISABLE	    0
426 # define DP_TRAINING_PATTERN_1		    1
427 # define DP_TRAINING_PATTERN_2		    2
428 # define DP_TRAINING_PATTERN_3		    3	    /* 1.2 */
429 # define DP_TRAINING_PATTERN_4              7       /* 1.4 */
430 # define DP_TRAINING_PATTERN_MASK	    0x3
431 # define DP_TRAINING_PATTERN_MASK_1_4	    0xf
432 
433 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
434 # define DP_LINK_QUAL_PATTERN_11_DISABLE    (0 << 2)
435 # define DP_LINK_QUAL_PATTERN_11_D10_2	    (1 << 2)
436 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
437 # define DP_LINK_QUAL_PATTERN_11_PRBS7	    (3 << 2)
438 # define DP_LINK_QUAL_PATTERN_11_MASK	    (3 << 2)
439 
440 # define DP_RECOVERED_CLOCK_OUT_EN	    (1 << 4)
441 # define DP_LINK_SCRAMBLING_DISABLE	    (1 << 5)
442 
443 # define DP_SYMBOL_ERROR_COUNT_BOTH	    (0 << 6)
444 # define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
445 # define DP_SYMBOL_ERROR_COUNT_SYMBOL	    (2 << 6)
446 # define DP_SYMBOL_ERROR_COUNT_MASK	    (3 << 6)
447 
448 #define DP_TRAINING_LANE0_SET		    0x103
449 #define DP_TRAINING_LANE1_SET		    0x104
450 #define DP_TRAINING_LANE2_SET		    0x105
451 #define DP_TRAINING_LANE3_SET		    0x106
452 
453 # define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
454 # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
455 # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
456 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
457 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
458 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
459 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
460 
461 # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
462 # define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
463 # define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
464 # define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
465 # define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
466 
467 # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
468 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
469 
470 #define DP_DOWNSPREAD_CTRL		    0x107
471 # define DP_SPREAD_AMP_0_5		    (1 << 4)
472 # define DP_MSA_TIMING_PAR_IGNORE_EN	    (1 << 7) /* eDP */
473 
474 #define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
475 # define DP_SET_ANSI_8B10B		    (1 << 0)
476 
477 #define DP_I2C_SPEED_CONTROL_STATUS	    0x109   /* DPI */
478 /* bitmask as for DP_I2C_SPEED_CAP */
479 
480 #define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
481 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
482 # define DP_FRAMING_CHANGE_ENABLE	    (1 << 1)
483 # define DP_PANEL_SELF_TEST_ENABLE	    (1 << 7)
484 
485 #define DP_LINK_QUAL_LANE0_SET		    0x10b   /* DPCD >= 1.2 */
486 #define DP_LINK_QUAL_LANE1_SET		    0x10c
487 #define DP_LINK_QUAL_LANE2_SET		    0x10d
488 #define DP_LINK_QUAL_LANE3_SET		    0x10e
489 # define DP_LINK_QUAL_PATTERN_DISABLE	    0
490 # define DP_LINK_QUAL_PATTERN_D10_2	    1
491 # define DP_LINK_QUAL_PATTERN_ERROR_RATE    2
492 # define DP_LINK_QUAL_PATTERN_PRBS7	    3
493 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM  4
494 # define DP_LINK_QUAL_PATTERN_HBR2_EYE      5
495 # define DP_LINK_QUAL_PATTERN_MASK	    7
496 
497 #define DP_TRAINING_LANE0_1_SET2	    0x10f
498 #define DP_TRAINING_LANE2_3_SET2	    0x110
499 # define DP_LANE02_POST_CURSOR2_SET_MASK    (3 << 0)
500 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
501 # define DP_LANE13_POST_CURSOR2_SET_MASK    (3 << 4)
502 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
503 
504 #define DP_MSTM_CTRL			    0x111   /* 1.2 */
505 # define DP_MST_EN			    (1 << 0)
506 # define DP_UP_REQ_EN			    (1 << 1)
507 # define DP_UPSTREAM_IS_SRC		    (1 << 2)
508 
509 #define DP_AUDIO_DELAY0			    0x112   /* 1.2 */
510 #define DP_AUDIO_DELAY1			    0x113
511 #define DP_AUDIO_DELAY2			    0x114
512 
513 #define DP_LINK_RATE_SET		    0x115   /* eDP 1.4 */
514 # define DP_LINK_RATE_SET_SHIFT		    0
515 # define DP_LINK_RATE_SET_MASK		    (7 << 0)
516 
517 #define DP_RECEIVER_ALPM_CONFIG		    0x116   /* eDP 1.4 */
518 # define DP_ALPM_ENABLE			    (1 << 0)
519 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE  (1 << 1)
520 
521 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF  0x117   /* eDP 1.4 */
522 # define DP_AUX_FRAME_SYNC_ENABLE	    (1 << 0)
523 # define DP_IRQ_HPD_ENABLE		    (1 << 1)
524 
525 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED	    0x118   /* 1.2 */
526 # define DP_PWR_NOT_NEEDED		    (1 << 0)
527 
528 #define DP_FEC_CONFIGURATION		    0x120    /* 1.4 */
529 # define DP_FEC_READY			    (1 << 0)
530 # define DP_FEC_ERR_COUNT_SEL_MASK	    (7 << 1)
531 # define DP_FEC_ERR_COUNT_DIS		    (0 << 1)
532 # define DP_FEC_UNCORR_BLK_ERROR_COUNT	    (1 << 1)
533 # define DP_FEC_CORR_BLK_ERROR_COUNT	    (2 << 1)
534 # define DP_FEC_BIT_ERROR_COUNT		    (3 << 1)
535 # define DP_FEC_LANE_SELECT_MASK	    (3 << 4)
536 # define DP_FEC_LANE_0_SELECT		    (0 << 4)
537 # define DP_FEC_LANE_1_SELECT		    (1 << 4)
538 # define DP_FEC_LANE_2_SELECT		    (2 << 4)
539 # define DP_FEC_LANE_3_SELECT		    (3 << 4)
540 
541 #define DP_AUX_FRAME_SYNC_VALUE		    0x15c   /* eDP 1.4 */
542 # define DP_AUX_FRAME_SYNC_VALID	    (1 << 0)
543 
544 #define DP_DSC_ENABLE                       0x160   /* DP 1.4 */
545 # define DP_DECOMPRESSION_EN                (1 << 0)
546 
547 #define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
548 # define DP_PSR_ENABLE			    (1 << 0)
549 # define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)
550 # define DP_PSR_CRC_VERIFICATION	    (1 << 2)
551 # define DP_PSR_FRAME_CAPTURE		    (1 << 3)
552 # define DP_PSR_SELECTIVE_UPDATE	    (1 << 4)
553 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS     (1 << 5)
554 # define DP_PSR_ENABLE_PSR2		    (1 << 6) /* eDP 1.4a */
555 
556 #define DP_ADAPTER_CTRL			    0x1a0
557 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
558 
559 #define DP_BRANCH_DEVICE_CTRL		    0x1a1
560 # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
561 
562 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
563 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
564 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
565 
566 #define DP_SINK_COUNT			    0x200
567 /* prior to 1.2 bit 7 was reserved mbz */
568 # define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
569 # define DP_SINK_CP_READY		    (1 << 6)
570 
571 #define DP_DEVICE_SERVICE_IRQ_VECTOR	    0x201
572 # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
573 # define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
574 # define DP_CP_IRQ			    (1 << 2)
575 # define DP_MCCS_IRQ			    (1 << 3)
576 # define DP_DOWN_REP_MSG_RDY		    (1 << 4) /* 1.2 MST */
577 # define DP_UP_REQ_MSG_RDY		    (1 << 5) /* 1.2 MST */
578 # define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
579 
580 #define DP_LANE0_1_STATUS		    0x202
581 #define DP_LANE2_3_STATUS		    0x203
582 # define DP_LANE_CR_DONE		    (1 << 0)
583 # define DP_LANE_CHANNEL_EQ_DONE	    (1 << 1)
584 # define DP_LANE_SYMBOL_LOCKED		    (1 << 2)
585 
586 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |		\
587 			    DP_LANE_CHANNEL_EQ_DONE |	\
588 			    DP_LANE_SYMBOL_LOCKED)
589 
590 #define DP_LANE_ALIGN_STATUS_UPDATED	    0x204
591 
592 #define DP_INTERLANE_ALIGN_DONE		    (1 << 0)
593 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
594 #define DP_LINK_STATUS_UPDATED		    (1 << 7)
595 
596 #define DP_SINK_STATUS			    0x205
597 
598 #define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
599 #define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)
600 
601 #define DP_ADJUST_REQUEST_LANE0_1	    0x206
602 #define DP_ADJUST_REQUEST_LANE2_3	    0x207
603 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
604 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
605 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
606 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
607 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
608 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
609 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
610 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
611 
612 #define DP_ADJUST_REQUEST_POST_CURSOR2      0x20c
613 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK  0x03
614 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
615 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK  0x0c
616 # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
617 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK  0x30
618 # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
619 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK  0xc0
620 # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
621 
622 #define DP_TEST_REQUEST			    0x218
623 # define DP_TEST_LINK_TRAINING		    (1 << 0)
624 # define DP_TEST_LINK_VIDEO_PATTERN	    (1 << 1)
625 # define DP_TEST_LINK_EDID_READ		    (1 << 2)
626 # define DP_TEST_LINK_PHY_TEST_PATTERN	    (1 << 3) /* DPCD >= 1.1 */
627 # define DP_TEST_LINK_FAUX_PATTERN	    (1 << 4) /* DPCD >= 1.2 */
628 # define DP_TEST_LINK_AUDIO_PATTERN         (1 << 5) /* DPCD >= 1.2 */
629 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO  (1 << 6) /* DPCD >= 1.2 */
630 
631 #define DP_TEST_LINK_RATE		    0x219
632 # define DP_LINK_RATE_162		    (0x6)
633 # define DP_LINK_RATE_27		    (0xa)
634 
635 #define DP_TEST_LANE_COUNT		    0x220
636 
637 #define DP_TEST_PATTERN			    0x221
638 # define DP_NO_TEST_PATTERN                 0x0
639 # define DP_COLOR_RAMP                      0x1
640 # define DP_BLACK_AND_WHITE_VERTICAL_LINES  0x2
641 # define DP_COLOR_SQUARE                    0x3
642 
643 #define DP_TEST_H_TOTAL_HI                  0x222
644 #define DP_TEST_H_TOTAL_LO                  0x223
645 
646 #define DP_TEST_V_TOTAL_HI                  0x224
647 #define DP_TEST_V_TOTAL_LO                  0x225
648 
649 #define DP_TEST_H_START_HI                  0x226
650 #define DP_TEST_H_START_LO                  0x227
651 
652 #define DP_TEST_V_START_HI                  0x228
653 #define DP_TEST_V_START_LO                  0x229
654 
655 #define DP_TEST_HSYNC_HI                    0x22A
656 # define DP_TEST_HSYNC_POLARITY             (1 << 7)
657 # define DP_TEST_HSYNC_WIDTH_HI_MASK        (127 << 0)
658 #define DP_TEST_HSYNC_WIDTH_LO              0x22B
659 
660 #define DP_TEST_VSYNC_HI                    0x22C
661 # define DP_TEST_VSYNC_POLARITY             (1 << 7)
662 # define DP_TEST_VSYNC_WIDTH_HI_MASK        (127 << 0)
663 #define DP_TEST_VSYNC_WIDTH_LO              0x22D
664 
665 #define DP_TEST_H_WIDTH_HI                  0x22E
666 #define DP_TEST_H_WIDTH_LO                  0x22F
667 
668 #define DP_TEST_V_HEIGHT_HI                 0x230
669 #define DP_TEST_V_HEIGHT_LO                 0x231
670 
671 #define DP_TEST_MISC0                       0x232
672 # define DP_TEST_SYNC_CLOCK                 (1 << 0)
673 # define DP_TEST_COLOR_FORMAT_MASK          (3 << 1)
674 # define DP_TEST_COLOR_FORMAT_SHIFT         1
675 # define DP_COLOR_FORMAT_RGB                (0 << 1)
676 # define DP_COLOR_FORMAT_YCbCr422           (1 << 1)
677 # define DP_COLOR_FORMAT_YCbCr444           (2 << 1)
678 # define DP_TEST_DYNAMIC_RANGE_VESA         (0 << 3)
679 # define DP_TEST_DYNAMIC_RANGE_CEA          (1 << 3)
680 # define DP_TEST_YCBCR_COEFFICIENTS         (1 << 4)
681 # define DP_YCBCR_COEFFICIENTS_ITU601       (0 << 4)
682 # define DP_YCBCR_COEFFICIENTS_ITU709       (1 << 4)
683 # define DP_TEST_BIT_DEPTH_MASK             (7 << 5)
684 # define DP_TEST_BIT_DEPTH_SHIFT            5
685 # define DP_TEST_BIT_DEPTH_6                (0 << 5)
686 # define DP_TEST_BIT_DEPTH_8                (1 << 5)
687 # define DP_TEST_BIT_DEPTH_10               (2 << 5)
688 # define DP_TEST_BIT_DEPTH_12               (3 << 5)
689 # define DP_TEST_BIT_DEPTH_16               (4 << 5)
690 
691 #define DP_TEST_MISC1                       0x233
692 # define DP_TEST_REFRESH_DENOMINATOR        (1 << 0)
693 # define DP_TEST_INTERLACED                 (1 << 1)
694 
695 #define DP_TEST_REFRESH_RATE_NUMERATOR      0x234
696 
697 #define DP_TEST_MISC0                       0x232
698 
699 #define DP_TEST_CRC_R_CR		    0x240
700 #define DP_TEST_CRC_G_Y			    0x242
701 #define DP_TEST_CRC_B_CB		    0x244
702 
703 #define DP_TEST_SINK_MISC		    0x246
704 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
705 # define DP_TEST_COUNT_MASK		    0xf
706 
707 #define DP_TEST_PHY_PATTERN                 0x248
708 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
709 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
710 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
711 #define	DP_TEST_80BIT_CUSTOM_PATTERN_31_24  0x253
712 #define	DP_TEST_80BIT_CUSTOM_PATTERN_39_32  0x254
713 #define	DP_TEST_80BIT_CUSTOM_PATTERN_47_40  0x255
714 #define	DP_TEST_80BIT_CUSTOM_PATTERN_55_48  0x256
715 #define	DP_TEST_80BIT_CUSTOM_PATTERN_63_56  0x257
716 #define	DP_TEST_80BIT_CUSTOM_PATTERN_71_64  0x258
717 #define	DP_TEST_80BIT_CUSTOM_PATTERN_79_72  0x259
718 
719 #define DP_TEST_RESPONSE		    0x260
720 # define DP_TEST_ACK			    (1 << 0)
721 # define DP_TEST_NAK			    (1 << 1)
722 # define DP_TEST_EDID_CHECKSUM_WRITE	    (1 << 2)
723 
724 #define DP_TEST_EDID_CHECKSUM		    0x261
725 
726 #define DP_TEST_SINK			    0x270
727 # define DP_TEST_SINK_START		    (1 << 0)
728 #define DP_TEST_AUDIO_MODE		    0x271
729 #define DP_TEST_AUDIO_PATTERN_TYPE	    0x272
730 #define DP_TEST_AUDIO_PERIOD_CH1	    0x273
731 #define DP_TEST_AUDIO_PERIOD_CH2	    0x274
732 #define DP_TEST_AUDIO_PERIOD_CH3	    0x275
733 #define DP_TEST_AUDIO_PERIOD_CH4	    0x276
734 #define DP_TEST_AUDIO_PERIOD_CH5	    0x277
735 #define DP_TEST_AUDIO_PERIOD_CH6	    0x278
736 #define DP_TEST_AUDIO_PERIOD_CH7	    0x279
737 #define DP_TEST_AUDIO_PERIOD_CH8	    0x27A
738 
739 #define DP_FEC_STATUS			    0x280    /* 1.4 */
740 # define DP_FEC_DECODE_EN_DETECTED	    (1 << 0)
741 # define DP_FEC_DECODE_DIS_DETECTED	    (1 << 1)
742 
743 #define DP_FEC_ERROR_COUNT_LSB		    0x0281    /* 1.4 */
744 
745 #define DP_FEC_ERROR_COUNT_MSB		    0x0282    /* 1.4 */
746 # define DP_FEC_ERROR_COUNT_MASK	    0x7F
747 # define DP_FEC_ERR_COUNT_VALID		    (1 << 7)
748 
749 #define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
750 # define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
751 # define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
752 
753 #define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
754 /* up to ID_SLOT_63 at 0x2ff */
755 
756 #define DP_SOURCE_OUI			    0x300
757 #define DP_SINK_OUI			    0x400
758 #define DP_BRANCH_OUI			    0x500
759 #define DP_BRANCH_ID                        0x503
760 #define DP_BRANCH_REVISION_START            0x509
761 #define DP_BRANCH_HW_REV                    0x509
762 #define DP_BRANCH_SW_REV                    0x50A
763 
764 #define DP_SET_POWER                        0x600
765 # define DP_SET_POWER_D0                    0x1
766 # define DP_SET_POWER_D3                    0x2
767 # define DP_SET_POWER_MASK                  0x3
768 # define DP_SET_POWER_D3_AUX_ON             0x5
769 
770 #define DP_EDP_DPCD_REV			    0x700    /* eDP 1.2 */
771 # define DP_EDP_11			    0x00
772 # define DP_EDP_12			    0x01
773 # define DP_EDP_13			    0x02
774 # define DP_EDP_14			    0x03
775 # define DP_EDP_14a                         0x04    /* eDP 1.4a */
776 # define DP_EDP_14b                         0x05    /* eDP 1.4b */
777 
778 #define DP_EDP_GENERAL_CAP_1		    0x701
779 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP		(1 << 0)
780 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP		(1 << 1)
781 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP		(1 << 2)
782 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP		(1 << 3)
783 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP		(1 << 4)
784 # define DP_EDP_FRC_ENABLE_CAP				(1 << 5)
785 # define DP_EDP_COLOR_ENGINE_CAP			(1 << 6)
786 # define DP_EDP_SET_POWER_CAP				(1 << 7)
787 
788 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP     0x702
789 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP	(1 << 0)
790 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP	(1 << 1)
791 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT		(1 << 2)
792 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP		(1 << 3)
793 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP	(1 << 4)
794 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP		(1 << 5)
795 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP			(1 << 6)
796 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP		(1 << 7)
797 
798 #define DP_EDP_GENERAL_CAP_2		    0x703
799 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED		(1 << 0)
800 
801 #define DP_EDP_GENERAL_CAP_3		    0x704    /* eDP 1.4 */
802 # define DP_EDP_X_REGION_CAP_MASK			(0xf << 0)
803 # define DP_EDP_X_REGION_CAP_SHIFT			0
804 # define DP_EDP_Y_REGION_CAP_MASK			(0xf << 4)
805 # define DP_EDP_Y_REGION_CAP_SHIFT			4
806 
807 #define DP_EDP_DISPLAY_CONTROL_REGISTER     0x720
808 # define DP_EDP_BACKLIGHT_ENABLE			(1 << 0)
809 # define DP_EDP_BLACK_VIDEO_ENABLE			(1 << 1)
810 # define DP_EDP_FRC_ENABLE				(1 << 2)
811 # define DP_EDP_COLOR_ENGINE_ENABLE			(1 << 3)
812 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE		(1 << 7)
813 
814 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER  0x721
815 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK		(3 << 0)
816 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM		(0 << 0)
817 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET		(1 << 0)
818 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD		(2 << 0)
819 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT		(3 << 0)
820 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE	(1 << 2)
821 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE		(1 << 3)
822 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE		(1 << 4)
823 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE		(1 << 5)
824 # define DP_EDP_UPDATE_REGION_BRIGHTNESS		(1 << 6) /* eDP 1.4 */
825 
826 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB     0x722
827 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB     0x723
828 
829 #define DP_EDP_PWMGEN_BIT_COUNT             0x724
830 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN     0x725
831 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX     0x726
832 # define DP_EDP_PWMGEN_BIT_COUNT_MASK       (0x1f << 0)
833 
834 #define DP_EDP_BACKLIGHT_CONTROL_STATUS     0x727
835 
836 #define DP_EDP_BACKLIGHT_FREQ_SET           0x728
837 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ     27000
838 
839 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB   0x72a
840 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID   0x72b
841 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB   0x72c
842 
843 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB   0x72d
844 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID   0x72e
845 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB   0x72f
846 
847 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET   0x732
848 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET   0x733
849 
850 #define DP_EDP_REGIONAL_BACKLIGHT_BASE      0x740    /* eDP 1.4 */
851 #define DP_EDP_REGIONAL_BACKLIGHT_0	    0x741    /* eDP 1.4 */
852 
853 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
854 #define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
855 #define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
856 #define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */
857 
858 #define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */
859 /* 0-5 sink count */
860 # define DP_SINK_COUNT_CP_READY             (1 << 6)
861 
862 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
863 
864 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
865 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE    (1 << 0)
866 # define DP_LOCK_ACQUISITION_REQUEST         (1 << 1)
867 # define DP_CEC_IRQ                          (1 << 2)
868 
869 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
870 
871 #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
872 # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
873 # define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
874 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
875 
876 #define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
877 # define DP_PSR_CAPS_CHANGE                 (1 << 0)
878 
879 #define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
880 # define DP_PSR_SINK_INACTIVE               0
881 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
882 # define DP_PSR_SINK_ACTIVE_RFB             2
883 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
884 # define DP_PSR_SINK_ACTIVE_RESYNC          4
885 # define DP_PSR_SINK_INTERNAL_ERROR         7
886 # define DP_PSR_SINK_STATE_MASK             0x07
887 
888 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK		0x2009 /* edp 1.4 */
889 # define DP_MAX_RESYNC_FRAME_COUNT_MASK			(0xf << 0)
890 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT		0
891 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK	(0xf << 4)
892 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT	4
893 
894 #define DP_LAST_RECEIVED_PSR_SDP	    0x200a /* eDP 1.2 */
895 # define DP_PSR_STATE_BIT		    (1 << 0) /* eDP 1.2 */
896 # define DP_UPDATE_RFB_BIT		    (1 << 1) /* eDP 1.2 */
897 # define DP_CRC_VALID_BIT		    (1 << 2) /* eDP 1.2 */
898 # define DP_SU_VALID			    (1 << 3) /* eDP 1.4 */
899 # define DP_FIRST_SCAN_LINE_SU_REGION	    (1 << 4) /* eDP 1.4 */
900 # define DP_LAST_SCAN_LINE_SU_REGION	    (1 << 5) /* eDP 1.4 */
901 # define DP_Y_COORDINATE_VALID		    (1 << 6) /* eDP 1.4a */
902 
903 #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
904 # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
905 
906 #define DP_LANE0_1_STATUS_ESI                  0x200c /* status same as 0x202 */
907 #define DP_LANE2_3_STATUS_ESI                  0x200d /* status same as 0x203 */
908 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI       0x200e /* status same as 0x204 */
909 #define DP_SINK_STATUS_ESI                     0x200f /* status same as 0x205 */
910 
911 #define DP_DP13_DPCD_REV                    0x2200
912 #define DP_DP13_MAX_LINK_RATE               0x2201
913 
914 #define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
915 # define DP_GTC_CAP					(1 << 0)  /* DP 1.3 */
916 # define DP_SST_SPLIT_SDP_CAP				(1 << 1)  /* DP 1.4 */
917 # define DP_AV_SYNC_CAP					(1 << 2)  /* DP 1.3 */
918 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED	(1 << 3)  /* DP 1.3 */
919 # define DP_VSC_EXT_VESA_SDP_SUPPORTED			(1 << 4)  /* DP 1.4 */
920 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED		(1 << 5)  /* DP 1.4 */
921 # define DP_VSC_EXT_CEA_SDP_SUPPORTED			(1 << 6)  /* DP 1.4 */
922 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED		(1 << 7)  /* DP 1.4 */
923 
924 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
925 #define DP_CEC_TUNNELING_CAPABILITY            0x3000
926 # define DP_CEC_TUNNELING_CAPABLE               (1 << 0)
927 # define DP_CEC_SNOOPING_CAPABLE                (1 << 1)
928 # define DP_CEC_MULTIPLE_LA_CAPABLE             (1 << 2)
929 
930 #define DP_CEC_TUNNELING_CONTROL               0x3001
931 # define DP_CEC_TUNNELING_ENABLE                (1 << 0)
932 # define DP_CEC_SNOOPING_ENABLE                 (1 << 1)
933 
934 #define DP_CEC_RX_MESSAGE_INFO                 0x3002
935 # define DP_CEC_RX_MESSAGE_LEN_MASK             (0xf << 0)
936 # define DP_CEC_RX_MESSAGE_LEN_SHIFT            0
937 # define DP_CEC_RX_MESSAGE_HPD_STATE            (1 << 4)
938 # define DP_CEC_RX_MESSAGE_HPD_LOST             (1 << 5)
939 # define DP_CEC_RX_MESSAGE_ACKED                (1 << 6)
940 # define DP_CEC_RX_MESSAGE_ENDED                (1 << 7)
941 
942 #define DP_CEC_TX_MESSAGE_INFO                 0x3003
943 # define DP_CEC_TX_MESSAGE_LEN_MASK             (0xf << 0)
944 # define DP_CEC_TX_MESSAGE_LEN_SHIFT            0
945 # define DP_CEC_TX_RETRY_COUNT_MASK             (0x7 << 4)
946 # define DP_CEC_TX_RETRY_COUNT_SHIFT            4
947 # define DP_CEC_TX_MESSAGE_SEND                 (1 << 7)
948 
949 #define DP_CEC_TUNNELING_IRQ_FLAGS             0x3004
950 # define DP_CEC_RX_MESSAGE_INFO_VALID           (1 << 0)
951 # define DP_CEC_RX_MESSAGE_OVERFLOW             (1 << 1)
952 # define DP_CEC_TX_MESSAGE_SENT                 (1 << 4)
953 # define DP_CEC_TX_LINE_ERROR                   (1 << 5)
954 # define DP_CEC_TX_ADDRESS_NACK_ERROR           (1 << 6)
955 # define DP_CEC_TX_DATA_NACK_ERROR              (1 << 7)
956 
957 #define DP_CEC_LOGICAL_ADDRESS_MASK            0x300E /* 0x300F word */
958 # define DP_CEC_LOGICAL_ADDRESS_0               (1 << 0)
959 # define DP_CEC_LOGICAL_ADDRESS_1               (1 << 1)
960 # define DP_CEC_LOGICAL_ADDRESS_2               (1 << 2)
961 # define DP_CEC_LOGICAL_ADDRESS_3               (1 << 3)
962 # define DP_CEC_LOGICAL_ADDRESS_4               (1 << 4)
963 # define DP_CEC_LOGICAL_ADDRESS_5               (1 << 5)
964 # define DP_CEC_LOGICAL_ADDRESS_6               (1 << 6)
965 # define DP_CEC_LOGICAL_ADDRESS_7               (1 << 7)
966 #define DP_CEC_LOGICAL_ADDRESS_MASK_2          0x300F /* 0x300E word */
967 # define DP_CEC_LOGICAL_ADDRESS_8               (1 << 0)
968 # define DP_CEC_LOGICAL_ADDRESS_9               (1 << 1)
969 # define DP_CEC_LOGICAL_ADDRESS_10              (1 << 2)
970 # define DP_CEC_LOGICAL_ADDRESS_11              (1 << 3)
971 # define DP_CEC_LOGICAL_ADDRESS_12              (1 << 4)
972 # define DP_CEC_LOGICAL_ADDRESS_13              (1 << 5)
973 # define DP_CEC_LOGICAL_ADDRESS_14              (1 << 6)
974 # define DP_CEC_LOGICAL_ADDRESS_15              (1 << 7)
975 
976 #define DP_CEC_RX_MESSAGE_BUFFER               0x3010
977 #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
978 #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
979 
980 #define DP_AUX_HDCP_BKSV		0x68000
981 #define DP_AUX_HDCP_RI_PRIME		0x68005
982 #define DP_AUX_HDCP_AKSV		0x68007
983 #define DP_AUX_HDCP_AN			0x6800C
984 #define DP_AUX_HDCP_V_PRIME(h)		(0x68014 + h * 4)
985 #define DP_AUX_HDCP_BCAPS		0x68028
986 # define DP_BCAPS_REPEATER_PRESENT	BIT(1)
987 # define DP_BCAPS_HDCP_CAPABLE		BIT(0)
988 #define DP_AUX_HDCP_BSTATUS		0x68029
989 # define DP_BSTATUS_REAUTH_REQ		BIT(3)
990 # define DP_BSTATUS_LINK_FAILURE	BIT(2)
991 # define DP_BSTATUS_R0_PRIME_READY	BIT(1)
992 # define DP_BSTATUS_READY		BIT(0)
993 #define DP_AUX_HDCP_BINFO		0x6802A
994 #define DP_AUX_HDCP_KSV_FIFO		0x6802C
995 #define DP_AUX_HDCP_AINFO		0x6803B
996 
997 /* DP HDCP2.2 parameter offsets in DPCD address space */
998 #define DP_HDCP_2_2_REG_RTX_OFFSET		0x69000
999 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET		0x69008
1000 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET		0x6900B
1001 #define DP_HDCP_2_2_REG_RRX_OFFSET		0x69215
1002 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET		0x6921D
1003 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET		0x69220
1004 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET	0x692A0
1005 #define DP_HDCP_2_2_REG_M_OFFSET		0x692B0
1006 #define DP_HDCP_2_2_REG_HPRIME_OFFSET		0x692C0
1007 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET	0x692E0
1008 #define DP_HDCP_2_2_REG_RN_OFFSET		0x692F0
1009 #define DP_HDCP_2_2_REG_LPRIME_OFFSET		0x692F8
1010 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET		0x69318
1011 #define	DP_HDCP_2_2_REG_RIV_OFFSET		0x69328
1012 #define DP_HDCP_2_2_REG_RXINFO_OFFSET		0x69330
1013 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET	0x69332
1014 #define DP_HDCP_2_2_REG_VPRIME_OFFSET		0x69335
1015 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET	0x69345
1016 #define DP_HDCP_2_2_REG_V_OFFSET		0x693E0
1017 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET	0x693F0
1018 #define DP_HDCP_2_2_REG_K_OFFSET		0x693F3
1019 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET	0x693F5
1020 #define DP_HDCP_2_2_REG_MPRIME_OFFSET		0x69473
1021 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET		0x69493
1022 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET	0x69494
1023 #define DP_HDCP_2_2_REG_DBG_OFFSET		0x69518
1024 
1025 /* Link Training (LT)-tunable PHY Repeaters */
1026 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1027 #define DP_MAX_LINK_RATE_PHY_REPEATER			    0xf0001 /* 1.4a */
1028 #define DP_PHY_REPEATER_CNT				    0xf0002 /* 1.3 */
1029 #define DP_PHY_REPEATER_MODE				    0xf0003 /* 1.3 */
1030 #define DP_MAX_LANE_COUNT_PHY_REPEATER			    0xf0004 /* 1.4a */
1031 #define DP_Repeater_FEC_CAPABILITY			    0xf0004 /* 1.4 */
1032 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT		    0xf0005 /* 1.4a */
1033 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1		    0xf0010 /* 1.3 */
1034 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1		    0xf0011 /* 1.3 */
1035 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1		    0xf0012 /* 1.3 */
1036 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1		    0xf0013 /* 1.3 */
1037 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1		    0xf0014 /* 1.3 */
1038 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1	    0xf0020 /* 1.4a */
1039 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1		    0xf0021 /* 1.4a */
1040 #define DP_LANE0_1_STATUS_PHY_REPEATER1			    0xf0030 /* 1.3 */
1041 #define DP_LANE2_3_STATUS_PHY_REPEATER1			    0xf0031 /* 1.3 */
1042 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1	    0xf0032 /* 1.3 */
1043 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1		    0xf0033 /* 1.3 */
1044 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1		    0xf0034 /* 1.3 */
1045 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1	    0xf0035 /* 1.3 */
1046 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1	    0xf0037 /* 1.3 */
1047 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1	    0xf0039 /* 1.3 */
1048 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1	    0xf003b /* 1.3 */
1049 #define DP_FEC_STATUS_PHY_REPEATER1			    0xf0290 /* 1.4 */
1050 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1                    0xf0291 /* 1.4 */
1051 #define DP_FEC_CAPABILITY_PHY_REPEATER1                     0xf0294 /* 1.4a */
1052 
1053 /* Repeater modes */
1054 #define DP_PHY_REPEATER_MODE_TRANSPARENT		    0x55    /* 1.3 */
1055 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT		    0xaa    /* 1.3 */
1056 
1057 /* DP HDCP message start offsets in DPCD address space */
1058 #define DP_HDCP_2_2_AKE_INIT_OFFSET		DP_HDCP_2_2_REG_RTX_OFFSET
1059 #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET	DP_HDCP_2_2_REG_CERT_RX_OFFSET
1060 #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET	DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1061 #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET	DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1062 #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET	DP_HDCP_2_2_REG_HPRIME_OFFSET
1063 #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1064 						DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1065 #define DP_HDCP_2_2_LC_INIT_OFFSET		DP_HDCP_2_2_REG_RN_OFFSET
1066 #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET	DP_HDCP_2_2_REG_LPRIME_OFFSET
1067 #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET		DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1068 #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET	DP_HDCP_2_2_REG_RXINFO_OFFSET
1069 #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET		DP_HDCP_2_2_REG_V_OFFSET
1070 #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET	DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1071 #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET	DP_HDCP_2_2_REG_MPRIME_OFFSET
1072 
1073 #define HDCP_2_2_DP_RXSTATUS_LEN		1
1074 #define HDCP_2_2_DP_RXSTATUS_READY(x)		((x) & BIT(0))
1075 #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)		((x) & BIT(1))
1076 #define HDCP_2_2_DP_RXSTATUS_PAIRING(x)		((x) & BIT(2))
1077 #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x)	((x) & BIT(3))
1078 #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)	((x) & BIT(4))
1079 
1080 /* DP 1.2 Sideband message defines */
1081 /* peer device type - DP 1.2a Table 2-92 */
1082 #define DP_PEER_DEVICE_NONE		0x0
1083 #define DP_PEER_DEVICE_SOURCE_OR_SST	0x1
1084 #define DP_PEER_DEVICE_MST_BRANCHING	0x2
1085 #define DP_PEER_DEVICE_SST_SINK		0x3
1086 #define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
1087 
1088 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1089 #define DP_GET_MSG_TRANSACTION_VERSION	0x00 /* DP 1.3 */
1090 #define DP_LINK_ADDRESS			0x01
1091 #define DP_CONNECTION_STATUS_NOTIFY	0x02
1092 #define DP_ENUM_PATH_RESOURCES		0x10
1093 #define DP_ALLOCATE_PAYLOAD		0x11
1094 #define DP_QUERY_PAYLOAD		0x12
1095 #define DP_RESOURCE_STATUS_NOTIFY	0x13
1096 #define DP_CLEAR_PAYLOAD_ID_TABLE	0x14
1097 #define DP_REMOTE_DPCD_READ		0x20
1098 #define DP_REMOTE_DPCD_WRITE		0x21
1099 #define DP_REMOTE_I2C_READ		0x22
1100 #define DP_REMOTE_I2C_WRITE		0x23
1101 #define DP_POWER_UP_PHY			0x24
1102 #define DP_POWER_DOWN_PHY		0x25
1103 #define DP_SINK_EVENT_NOTIFY		0x30
1104 #define DP_QUERY_STREAM_ENC_STATUS	0x38
1105 
1106 /* DP 1.2 MST sideband reply types */
1107 #define DP_SIDEBAND_REPLY_ACK		0x00
1108 #define DP_SIDEBAND_REPLY_NAK		0x01
1109 
1110 /* DP 1.2 MST sideband nak reasons - table 2.84 */
1111 #define DP_NAK_WRITE_FAILURE		0x01
1112 #define DP_NAK_INVALID_READ		0x02
1113 #define DP_NAK_CRC_FAILURE		0x03
1114 #define DP_NAK_BAD_PARAM		0x04
1115 #define DP_NAK_DEFER			0x05
1116 #define DP_NAK_LINK_FAILURE		0x06
1117 #define DP_NAK_NO_RESOURCES		0x07
1118 #define DP_NAK_DPCD_FAIL		0x08
1119 #define DP_NAK_I2C_NAK			0x09
1120 #define DP_NAK_ALLOCATE_FAIL		0x0a
1121 
1122 #define MODE_I2C_START	1
1123 #define MODE_I2C_WRITE	2
1124 #define MODE_I2C_READ	4
1125 #define MODE_I2C_STOP	8
1126 
1127 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1128 #define DP_MST_PHYSICAL_PORT_0 0
1129 #define DP_MST_LOGICAL_PORT_0 8
1130 
1131 #define DP_LINK_STATUS_SIZE	   6
1132 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1133 			  int lane_count);
1134 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1135 			      int lane_count);
1136 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1137 				     int lane);
1138 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1139 					  int lane);
1140 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
1141 					 unsigned int lane);
1142 
1143 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
1144 #define DP_RECEIVER_CAP_SIZE		0xf
1145 #define DP_DSC_RECEIVER_CAP_SIZE        0xf
1146 #define EDP_PSR_RECEIVER_CAP_SIZE	2
1147 #define EDP_DISPLAY_CTL_CAP_SIZE	3
1148 
1149 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1150 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1151 
1152 u8 drm_dp_link_rate_to_bw_code(int link_rate);
1153 int drm_dp_bw_code_to_link_rate(u8 link_bw);
1154 
1155 #define DP_SDP_AUDIO_TIMESTAMP		0x01
1156 #define DP_SDP_AUDIO_STREAM		0x02
1157 #define DP_SDP_EXTENSION		0x04 /* DP 1.1 */
1158 #define DP_SDP_AUDIO_COPYMANAGEMENT	0x05 /* DP 1.2 */
1159 #define DP_SDP_ISRC			0x06 /* DP 1.2 */
1160 #define DP_SDP_VSC			0x07 /* DP 1.2 */
1161 #define DP_SDP_CAMERA_GENERIC(i)	(0x08 + (i)) /* 0-7, DP 1.3 */
1162 #define DP_SDP_PPS			0x10 /* DP 1.4 */
1163 #define DP_SDP_VSC_EXT_VESA		0x20 /* DP 1.4 */
1164 #define DP_SDP_VSC_EXT_CEA		0x21 /* DP 1.4 */
1165 /* 0x80+ CEA-861 infoframe types */
1166 
1167 /**
1168  * struct dp_sdp_header - DP secondary data packet header
1169  * @HB0: Secondary Data Packet ID
1170  * @HB1: Secondary Data Packet Type
1171  * @HB2: Secondary Data Packet Specific header, Byte 0
1172  * @HB3: Secondary Data packet Specific header, Byte 1
1173  */
1174 struct dp_sdp_header {
1175 	u8 HB0;
1176 	u8 HB1;
1177 	u8 HB2;
1178 	u8 HB3;
1179 } __packed;
1180 
1181 #define EDP_SDP_HEADER_REVISION_MASK		0x1F
1182 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES	0x1F
1183 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1184 
1185 /**
1186  * struct dp_sdp - DP secondary data packet
1187  * @sdp_header: DP secondary data packet header
1188  * @db: DP secondaray data packet data blocks
1189  * VSC SDP Payload for PSR
1190  * db[0]: Stereo Interface
1191  * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1192  * db[2]: CRC value bits 7:0 of the R or Cr component
1193  * db[3]: CRC value bits 15:8 of the R or Cr component
1194  * db[4]: CRC value bits 7:0 of the G or Y component
1195  * db[5]: CRC value bits 15:8 of the G or Y component
1196  * db[6]: CRC value bits 7:0 of the B or Cb component
1197  * db[7]: CRC value bits 15:8 of the B or Cb component
1198  * db[8] - db[31]: Reserved
1199  * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1200  * db[0] - db[15]: Reserved
1201  * db[16]: Pixel Encoding and Colorimetry Formats
1202  * db[17]: Dynamic Range and Component Bit Depth
1203  * db[18]: Content Type
1204  * db[19] - db[31]: Reserved
1205  */
1206 struct dp_sdp {
1207 	struct dp_sdp_header sdp_header;
1208 	u8 db[32];
1209 } __packed;
1210 
1211 #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
1212 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
1213 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
1214 
1215 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1216 
1217 static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1218 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1219 {
1220 	return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1221 }
1222 
1223 static inline u8
drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1224 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1225 {
1226 	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1227 }
1228 
1229 static inline bool
drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1230 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1231 {
1232 	return dpcd[DP_DPCD_REV] >= 0x11 &&
1233 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1234 }
1235 
1236 static inline bool
drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1237 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1238 {
1239 	return dpcd[DP_DPCD_REV] >= 0x11 &&
1240 		(dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1241 }
1242 
1243 static inline bool
drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1244 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1245 {
1246 	return dpcd[DP_DPCD_REV] >= 0x12 &&
1247 		dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1248 }
1249 
1250 static inline bool
drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1251 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1252 {
1253 	return dpcd[DP_DPCD_REV] >= 0x14 &&
1254 		dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1255 }
1256 
1257 static inline u8
drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1258 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1259 {
1260 	return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1261 		DP_TRAINING_PATTERN_MASK;
1262 }
1263 
1264 static inline bool
drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1265 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1266 {
1267 	return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1268 }
1269 
1270 /* DP/eDP DSC support */
1271 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1272 				   bool is_edp);
1273 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1274 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1275 					 u8 dsc_bpc[3]);
1276 
1277 static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1278 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1279 {
1280 	return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1281 		DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1282 }
1283 
1284 static inline u16
drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1285 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1286 {
1287 	return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1288 		(dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1289 		 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1290 		 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1291 }
1292 
1293 static inline u32
drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1294 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1295 {
1296 	/* Max Slicewidth = Number of Pixels * 320 */
1297 	return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1298 		DP_DSC_SLICE_WIDTH_MULTIPLIER;
1299 }
1300 
1301 /* Forward Error Correction Support on DP 1.4 */
1302 static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)1303 drm_dp_sink_supports_fec(const u8 fec_capable)
1304 {
1305 	return fec_capable & DP_FEC_CAPABLE;
1306 }
1307 
1308 static inline bool
drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1309 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1310 {
1311 	return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1312 }
1313 
1314 static inline bool
drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])1315 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1316 {
1317 	return dpcd[DP_EDP_CONFIGURATION_CAP] &
1318 			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1319 }
1320 
1321 /*
1322  * DisplayPort AUX channel
1323  */
1324 
1325 /**
1326  * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1327  * @address: address of the (first) register to access
1328  * @request: contains the type of transaction (see DP_AUX_* macros)
1329  * @reply: upon completion, contains the reply type of the transaction
1330  * @buffer: pointer to a transmission or reception buffer
1331  * @size: size of @buffer
1332  */
1333 struct drm_dp_aux_msg {
1334 	unsigned int address;
1335 	u8 request;
1336 	u8 reply;
1337 	void *buffer;
1338 	size_t size;
1339 };
1340 
1341 struct cec_adapter;
1342 struct edid;
1343 struct drm_connector;
1344 
1345 /**
1346  * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1347  * @lock: mutex protecting this struct
1348  * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1349  * @connector: the connector this CEC adapter is associated with
1350  * @unregister_work: unregister the CEC adapter
1351  */
1352 struct drm_dp_aux_cec {
1353 	struct mutex lock;
1354 	struct cec_adapter *adap;
1355 	struct drm_connector *connector;
1356 	struct delayed_work unregister_work;
1357 };
1358 
1359 /**
1360  * struct drm_dp_aux - DisplayPort AUX channel
1361  * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1362  * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1363  * @dev: pointer to struct device that is the parent for this AUX channel
1364  * @crtc: backpointer to the crtc that is currently using this AUX channel
1365  * @hw_mutex: internal mutex used for locking transfers
1366  * @crc_work: worker that captures CRCs for each frame
1367  * @crc_count: counter of captured frame CRCs
1368  * @transfer: transfers a message representing a single AUX transaction
1369  *
1370  * The .dev field should be set to a pointer to the device that implements
1371  * the AUX channel.
1372  *
1373  * The .name field may be used to specify the name of the I2C adapter. If set to
1374  * NULL, dev_name() of .dev will be used.
1375  *
1376  * Drivers provide a hardware-specific implementation of how transactions
1377  * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1378  * structure describing the transaction is passed into this function. Upon
1379  * success, the implementation should return the number of payload bytes
1380  * that were transferred, or a negative error-code on failure. Helpers
1381  * propagate errors from the .transfer() function, with the exception of
1382  * the -EBUSY error, which causes a transaction to be retried. On a short,
1383  * helpers will return -EPROTO to make it simpler to check for failure.
1384  *
1385  * An AUX channel can also be used to transport I2C messages to a sink. A
1386  * typical application of that is to access an EDID that's present in the
1387  * sink device. The .transfer() function can also be used to execute such
1388  * transactions. The drm_dp_aux_register() function registers an I2C
1389  * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1390  * should call drm_dp_aux_unregister() to remove the I2C adapter.
1391  * The I2C adapter uses long transfers by default; if a partial response is
1392  * received, the adapter will drop down to the size given by the partial
1393  * response for this transaction only.
1394  *
1395  * Note that the aux helper code assumes that the .transfer() function
1396  * only modifies the reply field of the drm_dp_aux_msg structure.  The
1397  * retry logic and i2c helpers assume this is the case.
1398  */
1399 struct drm_dp_aux {
1400 	const char *name;
1401 	struct i2c_adapter ddc;
1402 	struct device *dev;
1403 	struct drm_crtc *crtc;
1404 	struct mutex hw_mutex;
1405 	struct work_struct crc_work;
1406 	u8 crc_count;
1407 	ssize_t (*transfer)(struct drm_dp_aux *aux,
1408 			    struct drm_dp_aux_msg *msg);
1409 	/**
1410 	 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1411 	 */
1412 	unsigned i2c_nack_count;
1413 	/**
1414 	 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1415 	 */
1416 	unsigned i2c_defer_count;
1417 	/**
1418 	 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1419 	 */
1420 	struct drm_dp_aux_cec cec;
1421 	/**
1422 	 * @is_remote: Is this AUX CH actually using sideband messaging.
1423 	 */
1424 	bool is_remote;
1425 };
1426 
1427 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1428 			 void *buffer, size_t size);
1429 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1430 			  void *buffer, size_t size);
1431 
1432 /**
1433  * drm_dp_dpcd_readb() - read a single byte from the DPCD
1434  * @aux: DisplayPort AUX channel
1435  * @offset: address of the register to read
1436  * @valuep: location where the value of the register will be stored
1437  *
1438  * Returns the number of bytes transferred (1) on success, or a negative
1439  * error code on failure.
1440  */
drm_dp_dpcd_readb(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)1441 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1442 					unsigned int offset, u8 *valuep)
1443 {
1444 	return drm_dp_dpcd_read(aux, offset, valuep, 1);
1445 }
1446 
1447 /**
1448  * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1449  * @aux: DisplayPort AUX channel
1450  * @offset: address of the register to write
1451  * @value: value to write to the register
1452  *
1453  * Returns the number of bytes transferred (1) on success, or a negative
1454  * error code on failure.
1455  */
drm_dp_dpcd_writeb(struct drm_dp_aux * aux,unsigned int offset,u8 value)1456 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1457 					 unsigned int offset, u8 value)
1458 {
1459 	return drm_dp_dpcd_write(aux, offset, &value, 1);
1460 }
1461 
1462 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1463 				 u8 status[DP_LINK_STATUS_SIZE]);
1464 
1465 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1466 				const u8 port_cap[4]);
1467 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1468 			      const u8 port_cap[4]);
1469 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1470 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1471 			     const u8 port_cap[4], struct drm_dp_aux *aux);
1472 
1473 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
1474 void drm_dp_aux_init(struct drm_dp_aux *aux);
1475 void drm_dp_aux_fini(struct drm_dp_aux *aux);
1476 int drm_dp_aux_register(struct drm_dp_aux *aux);
1477 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1478 
1479 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1480 int drm_dp_stop_crc(struct drm_dp_aux *aux);
1481 
1482 struct drm_dp_dpcd_ident {
1483 	u8 oui[3];
1484 	u8 device_id[6];
1485 	u8 hw_rev;
1486 	u8 sw_major_rev;
1487 	u8 sw_minor_rev;
1488 } __packed;
1489 
1490 /**
1491  * struct drm_dp_desc - DP branch/sink device descriptor
1492  * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1493  * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1494  */
1495 struct drm_dp_desc {
1496 	struct drm_dp_dpcd_ident ident;
1497 	u32 quirks;
1498 };
1499 
1500 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1501 		     bool is_branch);
1502 
1503 /**
1504  * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1505  *
1506  * Display Port sink and branch devices in the wild have a variety of bugs, try
1507  * to collect them here. The quirks are shared, but it's up to the drivers to
1508  * implement workarounds for them.
1509  */
1510 enum drm_dp_quirk {
1511 	/**
1512 	 * @DP_DPCD_QUIRK_CONSTANT_N:
1513 	 *
1514 	 * The device requires main link attributes Mvid and Nvid to be limited
1515 	 * to 16 bits. So will give a constant value (0x8000) for compatability.
1516 	 */
1517 	DP_DPCD_QUIRK_CONSTANT_N,
1518 	/**
1519 	 * @DP_DPCD_QUIRK_NO_PSR:
1520 	 *
1521 	 * The device does not support PSR even if reports that it supports or
1522 	 * driver still need to implement proper handling for such device.
1523 	 */
1524 	DP_DPCD_QUIRK_NO_PSR,
1525 	/**
1526 	 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
1527 	 *
1528 	 * The device does not set SINK_COUNT to a non-zero value.
1529 	 * The driver should ignore SINK_COUNT during detection.
1530 	 */
1531 	DP_DPCD_QUIRK_NO_SINK_COUNT,
1532 	/**
1533 	 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
1534 	 *
1535 	 * The device supports MST DSC despite not supporting Virtual DPCD.
1536 	 * The DSC caps can be read from the physical aux instead.
1537 	 */
1538 	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
1539 };
1540 
1541 /**
1542  * drm_dp_has_quirk() - does the DP device have a specific quirk
1543  * @desc: Device decriptor filled by drm_dp_read_desc()
1544  * @quirk: Quirk to query for
1545  *
1546  * Return true if DP device identified by @desc has @quirk.
1547  */
1548 static inline bool
drm_dp_has_quirk(const struct drm_dp_desc * desc,enum drm_dp_quirk quirk)1549 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1550 {
1551 	return desc->quirks & BIT(quirk);
1552 }
1553 
1554 #ifdef CONFIG_DRM_DP_CEC
1555 void drm_dp_cec_irq(struct drm_dp_aux *aux);
1556 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1557 				   struct drm_connector *connector);
1558 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
1559 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
1560 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
1561 #else
drm_dp_cec_irq(struct drm_dp_aux * aux)1562 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
1563 {
1564 }
1565 
1566 static inline void
drm_dp_cec_register_connector(struct drm_dp_aux * aux,struct drm_connector * connector)1567 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1568 			      struct drm_connector *connector)
1569 {
1570 }
1571 
drm_dp_cec_unregister_connector(struct drm_dp_aux * aux)1572 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
1573 {
1574 }
1575 
drm_dp_cec_set_edid(struct drm_dp_aux * aux,const struct edid * edid)1576 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
1577 				       const struct edid *edid)
1578 {
1579 }
1580 
drm_dp_cec_unset_edid(struct drm_dp_aux * aux)1581 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
1582 {
1583 }
1584 
1585 #endif
1586 
1587 #endif /* _DRM_DP_HELPER_H_ */
1588