1 /* $OpenBSD: atavar.h,v 1.23 2024/05/13 01:15:50 jsg Exp $ */ 2 /* $NetBSD: atavar.h,v 1.13 1999/03/10 13:11:43 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _DEV_ATA_ATAVAR_H_ 30 #define _DEV_ATA_ATAVAR_H_ 31 32 /* High-level functions and structures used by both ATA and ATAPI devices */ 33 #include <dev/ata/atareg.h> 34 35 /* Datas common to drives and controller drivers */ 36 struct ata_drive_datas { 37 u_int8_t drive; /* drive number */ 38 int8_t ata_vers; /* ATA version supported */ 39 u_int16_t drive_flags; /* bitmask for drives present/absent and cap */ 40 #define DRIVE_ATA 0x0001 41 #define DRIVE_ATAPI 0x0002 42 #define DRIVE_OLD 0x0004 43 #define DRIVE (DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD) 44 #define DRIVE_CAP32 0x0008 45 #define DRIVE_DMA 0x0010 46 #define DRIVE_UDMA 0x0020 47 #define DRIVE_MODE 0x0040 /* the drive reported its mode */ 48 #define DRIVE_RESET 0x0080 /* reset the drive state at next xfer */ 49 #define DRIVE_DMAERR 0x0100 /* Udma transfer had crc error, don't try DMA */ 50 #define DRIVE_DSCBA 0x0200 /* DSC in buffer availability mode */ 51 #define DRIVE_DSCWAIT 0x0400 /* In wait for DSC to be asserted */ 52 #define DRIVE_DEVICE_RESET 0x0800 /* Drive supports DEVICE RESET command */ 53 #define DRIVE_SATA 0x1000 /* SATA drive */ 54 /* 55 * Current setting of drive's PIO, DMA and UDMA modes. 56 * Is initialised by the disks drivers at attach time, and may be 57 * changed later by the controller's code if needed 58 */ 59 u_int8_t PIO_mode; /* Current setting of drive's PIO mode */ 60 u_int8_t DMA_mode; /* Current setting of drive's DMA mode */ 61 u_int8_t UDMA_mode; /* Current setting of drive's UDMA mode */ 62 /* Supported modes for this drive */ 63 u_int8_t PIO_cap; /* supported drive's PIO mode */ 64 u_int8_t DMA_cap; /* supported drive's DMA mode */ 65 u_int8_t UDMA_cap; /* supported drive's UDMA mode */ 66 /* 67 * Drive state. This is drive-type (ATA or ATAPI) dependant 68 * This is reset to 0 after a channel reset. 69 */ 70 u_int8_t state; 71 72 #define ACAP_LEN 0x01 /* 16 byte commands */ 73 #define ACAP_DSC 0x02 /* use DSC signalling */ 74 /* 0x20-0x40 reserved for ATAPI_CFG_DRQ_MASK */ 75 u_int8_t atapi_cap; 76 77 /* Keeps track of the number of resets that have occurred in a row 78 without a successful command completion. */ 79 u_int8_t n_resets; 80 u_int8_t n_dmaerrs; 81 u_int32_t n_xfers; 82 #define NERRS_MAX 4 83 #define NXFER 1000 84 85 char drive_name[31]; 86 int cf_flags; 87 void *chnl_softc; /* channel softc */ 88 89 struct ataparams id; 90 }; 91 92 /* ATA/ATAPI common attachment data */ 93 struct ata_atapi_attach { 94 u_int8_t aa_type; /* Type of device */ 95 #define T_ATA 0 96 #define T_ATAPI 1 97 u_int8_t aa_channel; /* controller's channel */ 98 u_int8_t aa_openings; /* Number of simultaneous commands possible */ 99 struct ata_drive_datas *aa_drv_data; 100 void *aa_bus_private; /* info specific to this bus */ 101 }; 102 103 /* User config flags that force (or disable) the use of a mode */ 104 #define ATA_CONFIG_PIO_MODES 0x0007 105 #define ATA_CONFIG_PIO_SET 0x0008 106 #define ATA_CONFIG_PIO_OFF 0 107 #define ATA_CONFIG_DMA_MODES 0x0070 108 #define ATA_CONFIG_DMA_SET 0x0080 109 #define ATA_CONFIG_DMA_DISABLE 0x0070 110 #define ATA_CONFIG_DMA_OFF 4 111 #define ATA_CONFIG_UDMA_MODES 0x0700 112 #define ATA_CONFIG_UDMA_SET 0x0800 113 #define ATA_CONFIG_UDMA_DISABLE 0x0700 114 #define ATA_CONFIG_UDMA_OFF 8 115 116 /* 117 * ATA/ATAPI commands description 118 * 119 * This structure defines the interface between the ATA/ATAPI device driver 120 * and the controller for short commands. It contains the command's parameter, 121 * the len of data's to read/write (if any), and a function to call upon 122 * completion. 123 * If no sleep is allowed, the driver can poll for command completion. 124 * Once the command completed, if the error registed is valid, the flag 125 * AT_ERROR is set and the error register value is copied to r_error . 126 * A separate interface is needed for read/write or ATAPI packet commands 127 * (which need multiple interrupts per commands). 128 */ 129 struct wdc_command { 130 u_int8_t r_command; /* Parameters to upload to registers */ 131 u_int8_t r_head; 132 u_int16_t r_cyl; 133 u_int8_t r_sector; 134 u_int8_t r_count; 135 u_int8_t r_features; 136 u_int8_t r_st_bmask; /* status register mask to wait for before command */ 137 u_int8_t r_st_pmask; /* status register mask to wait for after command */ 138 u_int8_t r_error; /* error register after command done */ 139 volatile u_int16_t flags; 140 #define AT_READ 0x0001 /* There is data to read */ 141 #define AT_WRITE 0x0002 /* There is data to write (excl. with AT_READ) */ 142 #define AT_WAIT 0x0008 /* wait in controller code for command completion */ 143 #define AT_POLL 0x0010 /* poll for command completion (no interrupts) */ 144 #define AT_DONE 0x0020 /* command is done */ 145 #define AT_ERROR 0x0040 /* command is done with error */ 146 #define AT_TIMEOU 0x0080 /* command timed out */ 147 #define AT_DF 0x0100 /* Drive fault */ 148 #define AT_READREG 0x0200 /* Read registers on completion */ 149 int timeout; /* timeout (in ms) */ 150 void *data; /* Data buffer address */ 151 int bcount; /* number of bytes to transfer */ 152 void (*callback)(void *); /* command to call once command completed */ 153 void *callback_arg; /* argument passed to *callback() */ 154 }; 155 156 extern int at_poll; 157 158 int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*); 159 #define WDC_COMPLETE 0x01 160 #define WDC_QUEUED 0x02 161 #define WDC_TRY_AGAIN 0x03 162 163 void wdc_probe_caps(struct ata_drive_datas*, struct ataparams *); 164 void wdc_print_caps(struct ata_drive_datas*); 165 int wdc_downgrade_mode(struct ata_drive_datas*); 166 167 void wdc_reset_channel(struct ata_drive_datas *, int); 168 169 int wdc_ata_addref(struct ata_drive_datas *); 170 void wdc_ata_delref(struct ata_drive_datas *); 171 172 int ata_get_params(struct ata_drive_datas*, u_int8_t, 173 struct ataparams *); 174 int ata_set_mode(struct ata_drive_datas*, u_int8_t, u_int8_t); 175 /* return code for these cmds */ 176 #define CMD_OK 0 177 #define CMD_ERR 1 178 #define CMD_AGAIN 2 179 180 void ata_dmaerr(struct ata_drive_datas *); 181 void ata_perror(struct ata_drive_datas *, int, char *, size_t); 182 183 #endif /* !_DEV_ATA_ATAVAR_H_ */ 184