1 /** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11 /* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36 #ifndef _DRM_H_ 37 #define _DRM_H_ 38 39 #if defined(__KERNEL__) || defined(__DragonFly__) 40 41 #include <linux/types.h> 42 #include <asm/ioctl.h> 43 typedef unsigned int drm_handle_t; 44 45 #else /* One of the BSDs */ 46 47 #include <sys/ioccom.h> 48 #include <sys/types.h> 49 typedef int8_t __s8; 50 typedef uint8_t __u8; 51 typedef int16_t __s16; 52 typedef uint16_t __u16; 53 typedef int32_t __s32; 54 typedef uint32_t __u32; 55 typedef int64_t __s64; 56 typedef uint64_t __u64; 57 typedef size_t __kernel_size_t; 58 typedef unsigned long drm_handle_t; 59 60 #endif 61 62 #if defined(__cplusplus) 63 extern "C" { 64 #endif 65 66 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 67 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 68 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 69 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 70 71 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 72 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 73 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 74 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 75 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 76 77 typedef unsigned int drm_context_t; 78 typedef unsigned int drm_drawable_t; 79 typedef unsigned int drm_magic_t; 80 81 /** 82 * Cliprect. 83 * 84 * \warning: If you change this structure, make sure you change 85 * XF86DRIClipRectRec in the server as well 86 * 87 * \note KW: Actually it's illegal to change either for 88 * backwards-compatibility reasons. 89 */ 90 struct drm_clip_rect { 91 unsigned short x1; 92 unsigned short y1; 93 unsigned short x2; 94 unsigned short y2; 95 }; 96 97 /** 98 * Drawable information. 99 */ 100 struct drm_drawable_info { 101 unsigned int num_rects; 102 struct drm_clip_rect *rects; 103 }; 104 105 /** 106 * Texture region, 107 */ 108 struct drm_tex_region { 109 unsigned char next; 110 unsigned char prev; 111 unsigned char in_use; 112 unsigned char padding; 113 unsigned int age; 114 }; 115 116 /** 117 * Hardware lock. 118 * 119 * The lock structure is a simple cache-line aligned integer. To avoid 120 * processor bus contention on a multiprocessor system, there should not be any 121 * other data stored in the same cache line. 122 */ 123 struct drm_hw_lock { 124 __volatile__ unsigned int lock; /**< lock variable */ 125 char padding[60]; /**< Pad to cache line */ 126 }; 127 128 /** 129 * DRM_IOCTL_VERSION ioctl argument type. 130 * 131 * \sa drmGetVersion(). 132 */ 133 struct drm_version { 134 int version_major; /**< Major version */ 135 int version_minor; /**< Minor version */ 136 int version_patchlevel; /**< Patch level */ 137 __kernel_size_t name_len; /**< Length of name buffer */ 138 char __user *name; /**< Name of driver */ 139 __kernel_size_t date_len; /**< Length of date buffer */ 140 char __user *date; /**< User-space buffer to hold date */ 141 __kernel_size_t desc_len; /**< Length of desc buffer */ 142 char __user *desc; /**< User-space buffer to hold desc */ 143 }; 144 145 /** 146 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 147 * 148 * \sa drmGetBusid() and drmSetBusId(). 149 */ 150 struct drm_unique { 151 __kernel_size_t unique_len; /**< Length of unique */ 152 char __user *unique; /**< Unique name for driver instantiation */ 153 }; 154 155 struct drm_list { 156 int count; /**< Length of user-space structures */ 157 struct drm_version __user *version; 158 }; 159 160 struct drm_block { 161 int unused; 162 }; 163 164 /** 165 * DRM_IOCTL_CONTROL ioctl argument type. 166 * 167 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 168 */ 169 struct drm_control { 170 enum { 171 DRM_ADD_COMMAND, 172 DRM_RM_COMMAND, 173 DRM_INST_HANDLER, 174 DRM_UNINST_HANDLER 175 } func; 176 int irq; 177 }; 178 179 /** 180 * Type of memory to map. 181 */ 182 enum drm_map_type { 183 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 184 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 185 _DRM_SHM = 2, /**< shared, cached */ 186 _DRM_AGP = 3, /**< AGP/GART */ 187 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 188 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 189 }; 190 191 /** 192 * Memory mapping flags. 193 */ 194 enum drm_map_flags { 195 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 196 _DRM_READ_ONLY = 0x02, 197 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 198 _DRM_KERNEL = 0x08, /**< kernel requires access */ 199 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 200 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 201 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 202 _DRM_DRIVER = 0x80 /**< Managed by driver */ 203 }; 204 205 struct drm_ctx_priv_map { 206 unsigned int ctx_id; /**< Context requesting private mapping */ 207 void *handle; /**< Handle of map */ 208 }; 209 210 /** 211 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 212 * argument type. 213 * 214 * \sa drmAddMap(). 215 */ 216 struct drm_map { 217 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 218 unsigned long size; /**< Requested physical size (bytes) */ 219 enum drm_map_type type; /**< Type of memory to map */ 220 enum drm_map_flags flags; /**< Flags */ 221 void *handle; /**< User-space: "Handle" to pass to mmap() */ 222 /**< Kernel-space: kernel-virtual address */ 223 int mtrr; /**< MTRR slot used */ 224 /* Private data */ 225 }; 226 227 /** 228 * DRM_IOCTL_GET_CLIENT ioctl argument type. 229 */ 230 struct drm_client { 231 int idx; /**< Which client desired? */ 232 int auth; /**< Is client authenticated? */ 233 unsigned long pid; /**< Process ID */ 234 unsigned long uid; /**< User ID */ 235 unsigned long magic; /**< Magic */ 236 unsigned long iocs; /**< Ioctl count */ 237 }; 238 239 enum drm_stat_type { 240 _DRM_STAT_LOCK, 241 _DRM_STAT_OPENS, 242 _DRM_STAT_CLOSES, 243 _DRM_STAT_IOCTLS, 244 _DRM_STAT_LOCKS, 245 _DRM_STAT_UNLOCKS, 246 _DRM_STAT_VALUE, /**< Generic value */ 247 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 248 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 249 250 _DRM_STAT_IRQ, /**< IRQ */ 251 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 252 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 253 _DRM_STAT_DMA, /**< DMA */ 254 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 255 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 256 /* Add to the *END* of the list */ 257 }; 258 259 /** 260 * DRM_IOCTL_GET_STATS ioctl argument type. 261 */ 262 struct drm_stats { 263 unsigned long count; 264 struct { 265 unsigned long value; 266 enum drm_stat_type type; 267 } data[15]; 268 }; 269 270 /** 271 * Hardware locking flags. 272 */ 273 enum drm_lock_flags { 274 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 275 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 276 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 277 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 278 /* These *HALT* flags aren't supported yet 279 -- they will be used to support the 280 full-screen DGA-like mode. */ 281 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 282 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 283 }; 284 285 /** 286 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 287 * 288 * \sa drmGetLock() and drmUnlock(). 289 */ 290 struct drm_lock { 291 int context; 292 enum drm_lock_flags flags; 293 }; 294 295 /** 296 * DMA flags 297 * 298 * \warning 299 * These values \e must match xf86drm.h. 300 * 301 * \sa drm_dma. 302 */ 303 enum drm_dma_flags { 304 /* Flags for DMA buffer dispatch */ 305 _DRM_DMA_BLOCK = 0x01, /**< 306 * Block until buffer dispatched. 307 * 308 * \note The buffer may not yet have 309 * been processed by the hardware -- 310 * getting a hardware lock with the 311 * hardware quiescent will ensure 312 * that the buffer has been 313 * processed. 314 */ 315 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 316 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 317 318 /* Flags for DMA buffer request */ 319 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 320 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 321 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 322 }; 323 324 /** 325 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 326 * 327 * \sa drmAddBufs(). 328 */ 329 struct drm_buf_desc { 330 int count; /**< Number of buffers of this size */ 331 int size; /**< Size in bytes */ 332 int low_mark; /**< Low water mark */ 333 int high_mark; /**< High water mark */ 334 enum { 335 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 336 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 337 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 338 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 339 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 340 } flags; 341 unsigned long agp_start; /**< 342 * Start address of where the AGP buffers are 343 * in the AGP aperture 344 */ 345 }; 346 347 /** 348 * DRM_IOCTL_INFO_BUFS ioctl argument type. 349 */ 350 struct drm_buf_info { 351 int count; /**< Entries in list */ 352 struct drm_buf_desc __user *list; 353 }; 354 355 /** 356 * DRM_IOCTL_FREE_BUFS ioctl argument type. 357 */ 358 struct drm_buf_free { 359 int count; 360 int __user *list; 361 }; 362 363 /** 364 * Buffer information 365 * 366 * \sa drm_buf_map. 367 */ 368 struct drm_buf_pub { 369 int idx; /**< Index into the master buffer list */ 370 int total; /**< Buffer size */ 371 int used; /**< Amount of buffer in use (for DMA) */ 372 void __user *address; /**< Address of buffer */ 373 }; 374 375 /** 376 * DRM_IOCTL_MAP_BUFS ioctl argument type. 377 */ 378 struct drm_buf_map { 379 int count; /**< Length of the buffer list */ 380 #ifdef __cplusplus 381 void __user *virt; 382 #else 383 void __user *virtual; /**< Mmap'd area in user-virtual */ 384 #endif 385 struct drm_buf_pub __user *list; /**< Buffer information */ 386 }; 387 388 /** 389 * DRM_IOCTL_DMA ioctl argument type. 390 * 391 * Indices here refer to the offset into the buffer list in drm_buf_get. 392 * 393 * \sa drmDMA(). 394 */ 395 struct drm_dma { 396 int context; /**< Context handle */ 397 int send_count; /**< Number of buffers to send */ 398 int __user *send_indices; /**< List of handles to buffers */ 399 int __user *send_sizes; /**< Lengths of data to send */ 400 enum drm_dma_flags flags; /**< Flags */ 401 int request_count; /**< Number of buffers requested */ 402 int request_size; /**< Desired size for buffers */ 403 int __user *request_indices; /**< Buffer information */ 404 int __user *request_sizes; 405 int granted_count; /**< Number of buffers granted */ 406 }; 407 408 enum drm_ctx_flags { 409 _DRM_CONTEXT_PRESERVED = 0x01, 410 _DRM_CONTEXT_2DONLY = 0x02 411 }; 412 413 /** 414 * DRM_IOCTL_ADD_CTX ioctl argument type. 415 * 416 * \sa drmCreateContext() and drmDestroyContext(). 417 */ 418 struct drm_ctx { 419 drm_context_t handle; 420 enum drm_ctx_flags flags; 421 }; 422 423 /** 424 * DRM_IOCTL_RES_CTX ioctl argument type. 425 */ 426 struct drm_ctx_res { 427 int count; 428 struct drm_ctx __user *contexts; 429 }; 430 431 /** 432 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 433 */ 434 struct drm_draw { 435 drm_drawable_t handle; 436 }; 437 438 /** 439 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 440 */ 441 typedef enum { 442 DRM_DRAWABLE_CLIPRECTS 443 } drm_drawable_info_type_t; 444 445 struct drm_update_draw { 446 drm_drawable_t handle; 447 unsigned int type; 448 unsigned int num; 449 unsigned long long data; 450 }; 451 452 /** 453 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 454 */ 455 struct drm_auth { 456 drm_magic_t magic; 457 }; 458 459 /** 460 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 461 * 462 * \sa drmGetInterruptFromBusID(). 463 */ 464 struct drm_irq_busid { 465 int irq; /**< IRQ number */ 466 int busnum; /**< bus number */ 467 int devnum; /**< device number */ 468 int funcnum; /**< function number */ 469 }; 470 471 enum drm_vblank_seq_type { 472 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 473 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 474 /* bits 1-6 are reserved for high crtcs */ 475 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 476 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 477 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 478 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 479 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 480 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 481 }; 482 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 483 484 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 485 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 486 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 487 488 struct drm_wait_vblank_request { 489 enum drm_vblank_seq_type type; 490 unsigned int sequence; 491 unsigned long signal; 492 }; 493 494 struct drm_wait_vblank_reply { 495 enum drm_vblank_seq_type type; 496 unsigned int sequence; 497 long tval_sec; 498 long tval_usec; 499 }; 500 501 /** 502 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 503 * 504 * \sa drmWaitVBlank(). 505 */ 506 union drm_wait_vblank { 507 struct drm_wait_vblank_request request; 508 struct drm_wait_vblank_reply reply; 509 }; 510 511 #define _DRM_PRE_MODESET 1 512 #define _DRM_POST_MODESET 2 513 514 /** 515 * DRM_IOCTL_MODESET_CTL ioctl argument type 516 * 517 * \sa drmModesetCtl(). 518 */ 519 struct drm_modeset_ctl { 520 __u32 crtc; 521 __u32 cmd; 522 }; 523 524 /** 525 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 526 * 527 * \sa drmAgpEnable(). 528 */ 529 struct drm_agp_mode { 530 unsigned long mode; /**< AGP mode */ 531 }; 532 533 /** 534 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 535 * 536 * \sa drmAgpAlloc() and drmAgpFree(). 537 */ 538 struct drm_agp_buffer { 539 unsigned long size; /**< In bytes -- will round to page boundary */ 540 unsigned long handle; /**< Used for binding / unbinding */ 541 unsigned long type; /**< Type of memory to allocate */ 542 unsigned long physical; /**< Physical used by i810 */ 543 }; 544 545 /** 546 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 547 * 548 * \sa drmAgpBind() and drmAgpUnbind(). 549 */ 550 struct drm_agp_binding { 551 unsigned long handle; /**< From drm_agp_buffer */ 552 unsigned long offset; /**< In bytes -- will round to page boundary */ 553 }; 554 555 /** 556 * DRM_IOCTL_AGP_INFO ioctl argument type. 557 * 558 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 559 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 560 * drmAgpVendorId() and drmAgpDeviceId(). 561 */ 562 struct drm_agp_info { 563 int agp_version_major; 564 int agp_version_minor; 565 unsigned long mode; 566 unsigned long aperture_base; /* physical address */ 567 unsigned long aperture_size; /* bytes */ 568 unsigned long memory_allowed; /* bytes */ 569 unsigned long memory_used; 570 571 /* PCI information */ 572 unsigned short id_vendor; 573 unsigned short id_device; 574 }; 575 576 /** 577 * DRM_IOCTL_SG_ALLOC ioctl argument type. 578 */ 579 struct drm_scatter_gather { 580 unsigned long size; /**< In bytes -- will round to page boundary */ 581 unsigned long handle; /**< Used for mapping / unmapping */ 582 }; 583 584 /** 585 * DRM_IOCTL_SET_VERSION ioctl argument type. 586 */ 587 struct drm_set_version { 588 int drm_di_major; 589 int drm_di_minor; 590 int drm_dd_major; 591 int drm_dd_minor; 592 }; 593 594 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 595 struct drm_gem_close { 596 /** Handle of the object to be closed. */ 597 __u32 handle; 598 __u32 pad; 599 }; 600 601 /** DRM_IOCTL_GEM_FLINK ioctl argument type */ 602 struct drm_gem_flink { 603 /** Handle for the object being named */ 604 __u32 handle; 605 606 /** Returned global name */ 607 __u32 name; 608 }; 609 610 /** DRM_IOCTL_GEM_OPEN ioctl argument type */ 611 struct drm_gem_open { 612 /** Name of object being opened */ 613 __u32 name; 614 615 /** Returned handle for the object */ 616 __u32 handle; 617 618 /** Returned size of the object */ 619 __u64 size; 620 }; 621 622 #define DRM_CAP_DUMB_BUFFER 0x1 623 #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 624 #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 625 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 626 #define DRM_CAP_PRIME 0x5 627 #define DRM_PRIME_CAP_IMPORT 0x1 628 #define DRM_PRIME_CAP_EXPORT 0x2 629 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 630 #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 631 /* 632 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 633 * combination for the hardware cursor. The intention is that a hardware 634 * agnostic userspace can query a cursor plane size to use. 635 * 636 * Note that the cross-driver contract is to merely return a valid size; 637 * drivers are free to attach another meaning on top, eg. i915 returns the 638 * maximum plane size. 639 */ 640 #define DRM_CAP_CURSOR_WIDTH 0x8 641 #define DRM_CAP_CURSOR_HEIGHT 0x9 642 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 643 #define DRM_CAP_PAGE_FLIP_TARGET 0x11 644 #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 645 #define DRM_CAP_SYNCOBJ 0x13 646 647 /** DRM_IOCTL_GET_CAP ioctl argument type */ 648 struct drm_get_cap { 649 __u64 capability; 650 __u64 value; 651 }; 652 653 /** 654 * DRM_CLIENT_CAP_STEREO_3D 655 * 656 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 657 * monitor by advertising the supported 3D layouts in the flags of struct 658 * drm_mode_modeinfo. 659 */ 660 #define DRM_CLIENT_CAP_STEREO_3D 1 661 662 /** 663 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 664 * 665 * If set to 1, the DRM core will expose all planes (overlay, primary, and 666 * cursor) to userspace. 667 */ 668 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 669 670 /** 671 * DRM_CLIENT_CAP_ATOMIC 672 * 673 * If set to 1, the DRM core will expose atomic properties to userspace 674 */ 675 #define DRM_CLIENT_CAP_ATOMIC 3 676 677 /** 678 * DRM_CLIENT_CAP_ASPECT_RATIO 679 * 680 * If set to 1, the DRM core will provide aspect ratio information in modes. 681 */ 682 #define DRM_CLIENT_CAP_ASPECT_RATIO 4 683 684 /** 685 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 686 * 687 * If set to 1, the DRM core will expose special connectors to be used for 688 * writing back to memory the scene setup in the commit. Depends on client 689 * also supporting DRM_CLIENT_CAP_ATOMIC 690 */ 691 #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 692 693 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 694 struct drm_set_client_cap { 695 __u64 capability; 696 __u64 value; 697 }; 698 699 #define DRM_RDWR O_RDWR 700 #define DRM_CLOEXEC O_CLOEXEC 701 struct drm_prime_handle { 702 __u32 handle; 703 704 /** Flags.. only applicable for handle->fd */ 705 __u32 flags; 706 707 /** Returned dmabuf file descriptor */ 708 __s32 fd; 709 }; 710 711 #if defined(__OpenBSD__) || defined(__DragonFly__) 712 struct drm_pciinfo { 713 uint16_t domain; 714 uint8_t bus; 715 uint8_t dev; 716 uint8_t func; 717 uint16_t vendor_id; 718 uint16_t device_id; 719 uint16_t subvendor_id; 720 uint16_t subdevice_id; 721 uint8_t revision_id; 722 }; 723 #endif 724 725 struct drm_syncobj_create { 726 __u32 handle; 727 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) 728 __u32 flags; 729 }; 730 731 struct drm_syncobj_destroy { 732 __u32 handle; 733 __u32 pad; 734 }; 735 736 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) 737 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) 738 struct drm_syncobj_handle { 739 __u32 handle; 740 __u32 flags; 741 742 __s32 fd; 743 __u32 pad; 744 }; 745 746 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) 747 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) 748 struct drm_syncobj_wait { 749 __u64 handles; 750 /* absolute timeout */ 751 __s64 timeout_nsec; 752 __u32 count_handles; 753 __u32 flags; 754 __u32 first_signaled; /* only valid when not waiting all */ 755 __u32 pad; 756 }; 757 758 struct drm_syncobj_array { 759 __u64 handles; 760 __u32 count_handles; 761 __u32 pad; 762 }; 763 764 /* Query current scanout sequence number */ 765 struct drm_crtc_get_sequence { 766 __u32 crtc_id; /* requested crtc_id */ 767 __u32 active; /* return: crtc output is active */ 768 __u64 sequence; /* return: most recent vblank sequence */ 769 __s64 sequence_ns; /* return: most recent time of first pixel out */ 770 }; 771 772 /* Queue event to be delivered at specified sequence. Time stamp marks 773 * when the first pixel of the refresh cycle leaves the display engine 774 * for the display 775 */ 776 #define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ 777 #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ 778 779 struct drm_crtc_queue_sequence { 780 __u32 crtc_id; 781 __u32 flags; 782 __u64 sequence; /* on input, target sequence. on output, actual sequence */ 783 __u64 user_data; /* user data passed to event */ 784 }; 785 786 #if defined(__cplusplus) 787 } 788 #endif 789 790 #include "drm_mode.h" 791 792 #if defined(__cplusplus) 793 extern "C" { 794 #endif 795 796 #define DRM_IOCTL_BASE 'd' 797 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 798 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 799 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 800 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 801 802 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 803 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 804 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 805 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 806 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 807 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 808 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 809 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 810 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 811 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 812 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 813 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 814 #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 815 #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 816 817 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 818 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 819 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 820 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 821 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 822 #if defined(__OpenBSD__) || defined(__DragonFly__) 823 #define DRM_IOCTL_GET_PCIINFO DRM_IOR( 0x15, struct drm_pciinfo) 824 #else 825 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 826 #endif 827 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 828 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 829 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 830 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 831 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 832 833 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 834 835 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 836 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 837 838 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 839 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 840 841 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 842 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 843 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 844 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 845 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 846 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 847 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 848 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 849 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 850 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 851 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 852 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 853 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 854 855 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 856 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 857 858 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 859 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 860 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 861 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 862 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 863 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 864 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 865 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 866 867 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 868 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 869 870 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 871 872 #define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) 873 #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) 874 875 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 876 877 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 878 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 879 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 880 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 881 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 882 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 883 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 884 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 885 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 886 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 887 888 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 889 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 890 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 891 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 892 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 893 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 894 #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 895 #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 896 897 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 898 #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 899 #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 900 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 901 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 902 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 903 #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 904 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 905 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 906 #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 907 #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 908 #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 909 #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 910 911 #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) 912 #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) 913 #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) 914 #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) 915 #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) 916 #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) 917 #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) 918 919 #define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) 920 #define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) 921 #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) 922 #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) 923 924 /** 925 * Device specific ioctls should only be in their respective headers 926 * The device specific ioctl range is from 0x40 to 0x9f. 927 * Generic IOCTLS restart at 0xA0. 928 * 929 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 930 * drmCommandReadWrite(). 931 */ 932 #define DRM_COMMAND_BASE 0x40 933 #define DRM_COMMAND_END 0xA0 934 935 /** 936 * Header for events written back to userspace on the drm fd. The 937 * type defines the type of event, the length specifies the total 938 * length of the event (including the header), and user_data is 939 * typically a 64 bit value passed with the ioctl that triggered the 940 * event. A read on the drm fd will always only return complete 941 * events, that is, if for example the read buffer is 100 bytes, and 942 * there are two 64 byte events pending, only one will be returned. 943 * 944 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 945 * up are chipset specific. 946 */ 947 struct drm_event { 948 __u32 type; 949 __u32 length; 950 }; 951 952 #define DRM_EVENT_VBLANK 0x01 953 #define DRM_EVENT_FLIP_COMPLETE 0x02 954 #define DRM_EVENT_CRTC_SEQUENCE 0x03 955 956 struct drm_event_vblank { 957 struct drm_event base; 958 __u64 user_data; 959 __u32 tv_sec; 960 __u32 tv_usec; 961 __u32 sequence; 962 __u32 crtc_id; /* 0 on older kernels that do not support this */ 963 }; 964 965 /* Event delivered at sequence. Time stamp marks when the first pixel 966 * of the refresh cycle leaves the display engine for the display 967 */ 968 struct drm_event_crtc_sequence { 969 struct drm_event base; 970 __u64 user_data; 971 __s64 time_ns; 972 __u64 sequence; 973 }; 974 975 /* typedef area */ 976 #ifndef __KERNEL__ 977 typedef struct drm_clip_rect drm_clip_rect_t; 978 typedef struct drm_drawable_info drm_drawable_info_t; 979 typedef struct drm_tex_region drm_tex_region_t; 980 typedef struct drm_hw_lock drm_hw_lock_t; 981 typedef struct drm_version drm_version_t; 982 typedef struct drm_unique drm_unique_t; 983 typedef struct drm_list drm_list_t; 984 typedef struct drm_block drm_block_t; 985 typedef struct drm_control drm_control_t; 986 typedef enum drm_map_type drm_map_type_t; 987 typedef enum drm_map_flags drm_map_flags_t; 988 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 989 typedef struct drm_map drm_map_t; 990 typedef struct drm_client drm_client_t; 991 typedef enum drm_stat_type drm_stat_type_t; 992 typedef struct drm_stats drm_stats_t; 993 typedef enum drm_lock_flags drm_lock_flags_t; 994 typedef struct drm_lock drm_lock_t; 995 typedef enum drm_dma_flags drm_dma_flags_t; 996 typedef struct drm_buf_desc drm_buf_desc_t; 997 typedef struct drm_buf_info drm_buf_info_t; 998 typedef struct drm_buf_free drm_buf_free_t; 999 typedef struct drm_buf_pub drm_buf_pub_t; 1000 typedef struct drm_buf_map drm_buf_map_t; 1001 typedef struct drm_dma drm_dma_t; 1002 typedef union drm_wait_vblank drm_wait_vblank_t; 1003 typedef struct drm_agp_mode drm_agp_mode_t; 1004 typedef enum drm_ctx_flags drm_ctx_flags_t; 1005 typedef struct drm_ctx drm_ctx_t; 1006 typedef struct drm_ctx_res drm_ctx_res_t; 1007 typedef struct drm_draw drm_draw_t; 1008 typedef struct drm_update_draw drm_update_draw_t; 1009 typedef struct drm_auth drm_auth_t; 1010 typedef struct drm_irq_busid drm_irq_busid_t; 1011 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 1012 1013 typedef struct drm_agp_buffer drm_agp_buffer_t; 1014 typedef struct drm_agp_binding drm_agp_binding_t; 1015 typedef struct drm_agp_info drm_agp_info_t; 1016 typedef struct drm_scatter_gather drm_scatter_gather_t; 1017 typedef struct drm_set_version drm_set_version_t; 1018 #endif 1019 1020 #if defined(__cplusplus) 1021 } 1022 #endif 1023 1024 #endif 1025