1 /* $OpenBSD: aic79xx_reg.h,v 1.4 2006/12/23 21:15:58 krw Exp $ */ 2 /* 3 * DO NOT EDIT - This file is automatically generated 4 * from the following source files: 5 * 6 * Id: aic79xx.seq,v 1.6 2005/03/23 23:47:22 deraadt Exp 7 * Id: aic79xx.reg,v 1.5 2006/02/06 17:29:11 jmc Exp 8 */ 9 typedef int (ahd_reg_print_t)(u_int, u_int *, u_int); 10 typedef struct ahd_reg_parse_entry { 11 char *name; 12 uint8_t value; 13 uint8_t mask; 14 } ahd_reg_parse_entry_t; 15 16 #if AIC_DEBUG_REGISTERS 17 ahd_reg_print_t ahd_mode_ptr_print; 18 #else 19 #define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ 20 ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap) 21 #endif 22 23 #if AIC_DEBUG_REGISTERS 24 ahd_reg_print_t ahd_intstat_print; 25 #else 26 #define ahd_intstat_print(regvalue, cur_col, wrap) \ 27 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap) 28 #endif 29 30 #if AIC_DEBUG_REGISTERS 31 ahd_reg_print_t ahd_seqintcode_print; 32 #else 33 #define ahd_seqintcode_print(regvalue, cur_col, wrap) \ 34 ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap) 35 #endif 36 37 #if AIC_DEBUG_REGISTERS 38 ahd_reg_print_t ahd_clrint_print; 39 #else 40 #define ahd_clrint_print(regvalue, cur_col, wrap) \ 41 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap) 42 #endif 43 44 #if AIC_DEBUG_REGISTERS 45 ahd_reg_print_t ahd_error_print; 46 #else 47 #define ahd_error_print(regvalue, cur_col, wrap) \ 48 ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap) 49 #endif 50 51 #if AIC_DEBUG_REGISTERS 52 ahd_reg_print_t ahd_clrerr_print; 53 #else 54 #define ahd_clrerr_print(regvalue, cur_col, wrap) \ 55 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap) 56 #endif 57 58 #if AIC_DEBUG_REGISTERS 59 ahd_reg_print_t ahd_hcntrl_print; 60 #else 61 #define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 62 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap) 63 #endif 64 65 #if AIC_DEBUG_REGISTERS 66 ahd_reg_print_t ahd_hnscb_qoff_print; 67 #else 68 #define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \ 69 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap) 70 #endif 71 72 #if AIC_DEBUG_REGISTERS 73 ahd_reg_print_t ahd_hescb_qoff_print; 74 #else 75 #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 76 ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap) 77 #endif 78 79 #if AIC_DEBUG_REGISTERS 80 ahd_reg_print_t ahd_hs_mailbox_print; 81 #else 82 #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \ 83 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap) 84 #endif 85 86 #if AIC_DEBUG_REGISTERS 87 ahd_reg_print_t ahd_seqintstat_print; 88 #else 89 #define ahd_seqintstat_print(regvalue, cur_col, wrap) \ 90 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 91 #endif 92 93 #if AIC_DEBUG_REGISTERS 94 ahd_reg_print_t ahd_clrseqintstat_print; 95 #else 96 #define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \ 97 ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 98 #endif 99 100 #if AIC_DEBUG_REGISTERS 101 ahd_reg_print_t ahd_swtimer_print; 102 #else 103 #define ahd_swtimer_print(regvalue, cur_col, wrap) \ 104 ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap) 105 #endif 106 107 #if AIC_DEBUG_REGISTERS 108 ahd_reg_print_t ahd_snscb_qoff_print; 109 #else 110 #define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \ 111 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap) 112 #endif 113 114 #if AIC_DEBUG_REGISTERS 115 ahd_reg_print_t ahd_sescb_qoff_print; 116 #else 117 #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 118 ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap) 119 #endif 120 121 #if AIC_DEBUG_REGISTERS 122 ahd_reg_print_t ahd_sdscb_qoff_print; 123 #else 124 #define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \ 125 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap) 126 #endif 127 128 #if AIC_DEBUG_REGISTERS 129 ahd_reg_print_t ahd_qoff_ctlsta_print; 130 #else 131 #define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 132 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap) 133 #endif 134 135 #if AIC_DEBUG_REGISTERS 136 ahd_reg_print_t ahd_intctl_print; 137 #else 138 #define ahd_intctl_print(regvalue, cur_col, wrap) \ 139 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap) 140 #endif 141 142 #if AIC_DEBUG_REGISTERS 143 ahd_reg_print_t ahd_dfcntrl_print; 144 #else 145 #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \ 146 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap) 147 #endif 148 149 #if AIC_DEBUG_REGISTERS 150 ahd_reg_print_t ahd_dscommand0_print; 151 #else 152 #define ahd_dscommand0_print(regvalue, cur_col, wrap) \ 153 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap) 154 #endif 155 156 #if AIC_DEBUG_REGISTERS 157 ahd_reg_print_t ahd_dfstatus_print; 158 #else 159 #define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 160 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap) 161 #endif 162 163 #if AIC_DEBUG_REGISTERS 164 ahd_reg_print_t ahd_sg_cache_shadow_print; 165 #else 166 #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 167 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap) 168 #endif 169 170 #if AIC_DEBUG_REGISTERS 171 ahd_reg_print_t ahd_sg_cache_pre_print; 172 #else 173 #define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 174 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap) 175 #endif 176 177 #if AIC_DEBUG_REGISTERS 178 ahd_reg_print_t ahd_arbctl_print; 179 #else 180 #define ahd_arbctl_print(regvalue, cur_col, wrap) \ 181 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap) 182 #endif 183 184 #if AIC_DEBUG_REGISTERS 185 ahd_reg_print_t ahd_lqin_print; 186 #else 187 #define ahd_lqin_print(regvalue, cur_col, wrap) \ 188 ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap) 189 #endif 190 191 #if AIC_DEBUG_REGISTERS 192 ahd_reg_print_t ahd_typeptr_print; 193 #else 194 #define ahd_typeptr_print(regvalue, cur_col, wrap) \ 195 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap) 196 #endif 197 198 #if AIC_DEBUG_REGISTERS 199 ahd_reg_print_t ahd_tagptr_print; 200 #else 201 #define ahd_tagptr_print(regvalue, cur_col, wrap) \ 202 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap) 203 #endif 204 205 #if AIC_DEBUG_REGISTERS 206 ahd_reg_print_t ahd_lunptr_print; 207 #else 208 #define ahd_lunptr_print(regvalue, cur_col, wrap) \ 209 ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap) 210 #endif 211 212 #if AIC_DEBUG_REGISTERS 213 ahd_reg_print_t ahd_datalenptr_print; 214 #else 215 #define ahd_datalenptr_print(regvalue, cur_col, wrap) \ 216 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap) 217 #endif 218 219 #if AIC_DEBUG_REGISTERS 220 ahd_reg_print_t ahd_statlenptr_print; 221 #else 222 #define ahd_statlenptr_print(regvalue, cur_col, wrap) \ 223 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap) 224 #endif 225 226 #if AIC_DEBUG_REGISTERS 227 ahd_reg_print_t ahd_cmdlenptr_print; 228 #else 229 #define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 230 ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap) 231 #endif 232 233 #if AIC_DEBUG_REGISTERS 234 ahd_reg_print_t ahd_attrptr_print; 235 #else 236 #define ahd_attrptr_print(regvalue, cur_col, wrap) \ 237 ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap) 238 #endif 239 240 #if AIC_DEBUG_REGISTERS 241 ahd_reg_print_t ahd_flagptr_print; 242 #else 243 #define ahd_flagptr_print(regvalue, cur_col, wrap) \ 244 ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap) 245 #endif 246 247 #if AIC_DEBUG_REGISTERS 248 ahd_reg_print_t ahd_cmdptr_print; 249 #else 250 #define ahd_cmdptr_print(regvalue, cur_col, wrap) \ 251 ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap) 252 #endif 253 254 #if AIC_DEBUG_REGISTERS 255 ahd_reg_print_t ahd_qnextptr_print; 256 #else 257 #define ahd_qnextptr_print(regvalue, cur_col, wrap) \ 258 ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap) 259 #endif 260 261 #if AIC_DEBUG_REGISTERS 262 ahd_reg_print_t ahd_idptr_print; 263 #else 264 #define ahd_idptr_print(regvalue, cur_col, wrap) \ 265 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap) 266 #endif 267 268 #if AIC_DEBUG_REGISTERS 269 ahd_reg_print_t ahd_abrtbyteptr_print; 270 #else 271 #define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 272 ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap) 273 #endif 274 275 #if AIC_DEBUG_REGISTERS 276 ahd_reg_print_t ahd_abrtbitptr_print; 277 #else 278 #define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \ 279 ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap) 280 #endif 281 282 #if AIC_DEBUG_REGISTERS 283 ahd_reg_print_t ahd_maxcmdbytes_print; 284 #else 285 #define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \ 286 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap) 287 #endif 288 289 #if AIC_DEBUG_REGISTERS 290 ahd_reg_print_t ahd_maxcmd2rcv_print; 291 #else 292 #define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \ 293 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap) 294 #endif 295 296 #if AIC_DEBUG_REGISTERS 297 ahd_reg_print_t ahd_shortthresh_print; 298 #else 299 #define ahd_shortthresh_print(regvalue, cur_col, wrap) \ 300 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap) 301 #endif 302 303 #if AIC_DEBUG_REGISTERS 304 ahd_reg_print_t ahd_lunlen_print; 305 #else 306 #define ahd_lunlen_print(regvalue, cur_col, wrap) \ 307 ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap) 308 #endif 309 310 #if AIC_DEBUG_REGISTERS 311 ahd_reg_print_t ahd_cdblimit_print; 312 #else 313 #define ahd_cdblimit_print(regvalue, cur_col, wrap) \ 314 ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap) 315 #endif 316 317 #if AIC_DEBUG_REGISTERS 318 ahd_reg_print_t ahd_maxcmd_print; 319 #else 320 #define ahd_maxcmd_print(regvalue, cur_col, wrap) \ 321 ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap) 322 #endif 323 324 #if AIC_DEBUG_REGISTERS 325 ahd_reg_print_t ahd_maxcmdcnt_print; 326 #else 327 #define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \ 328 ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap) 329 #endif 330 331 #if AIC_DEBUG_REGISTERS 332 ahd_reg_print_t ahd_lqrsvd01_print; 333 #else 334 #define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \ 335 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap) 336 #endif 337 338 #if AIC_DEBUG_REGISTERS 339 ahd_reg_print_t ahd_lqrsvd16_print; 340 #else 341 #define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \ 342 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap) 343 #endif 344 345 #if AIC_DEBUG_REGISTERS 346 ahd_reg_print_t ahd_lqrsvd17_print; 347 #else 348 #define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \ 349 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap) 350 #endif 351 352 #if AIC_DEBUG_REGISTERS 353 ahd_reg_print_t ahd_cmdrsvd0_print; 354 #else 355 #define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \ 356 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap) 357 #endif 358 359 #if AIC_DEBUG_REGISTERS 360 ahd_reg_print_t ahd_lqctl0_print; 361 #else 362 #define ahd_lqctl0_print(regvalue, cur_col, wrap) \ 363 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap) 364 #endif 365 366 #if AIC_DEBUG_REGISTERS 367 ahd_reg_print_t ahd_lqctl1_print; 368 #else 369 #define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 370 ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap) 371 #endif 372 373 #if AIC_DEBUG_REGISTERS 374 ahd_reg_print_t ahd_lqctl2_print; 375 #else 376 #define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 377 ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap) 378 #endif 379 380 #if AIC_DEBUG_REGISTERS 381 ahd_reg_print_t ahd_scsbist0_print; 382 #else 383 #define ahd_scsbist0_print(regvalue, cur_col, wrap) \ 384 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap) 385 #endif 386 387 #if AIC_DEBUG_REGISTERS 388 ahd_reg_print_t ahd_scsiseq0_print; 389 #else 390 #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 391 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap) 392 #endif 393 394 #if AIC_DEBUG_REGISTERS 395 ahd_reg_print_t ahd_scsbist1_print; 396 #else 397 #define ahd_scsbist1_print(regvalue, cur_col, wrap) \ 398 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap) 399 #endif 400 401 #if AIC_DEBUG_REGISTERS 402 ahd_reg_print_t ahd_scsiseq1_print; 403 #else 404 #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \ 405 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap) 406 #endif 407 408 #if AIC_DEBUG_REGISTERS 409 ahd_reg_print_t ahd_businitid_print; 410 #else 411 #define ahd_businitid_print(regvalue, cur_col, wrap) \ 412 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap) 413 #endif 414 415 #if AIC_DEBUG_REGISTERS 416 ahd_reg_print_t ahd_sxfrctl0_print; 417 #else 418 #define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \ 419 ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap) 420 #endif 421 422 #if AIC_DEBUG_REGISTERS 423 ahd_reg_print_t ahd_dlcount_print; 424 #else 425 #define ahd_dlcount_print(regvalue, cur_col, wrap) \ 426 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap) 427 #endif 428 429 #if AIC_DEBUG_REGISTERS 430 ahd_reg_print_t ahd_sxfrctl1_print; 431 #else 432 #define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 433 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap) 434 #endif 435 436 #if AIC_DEBUG_REGISTERS 437 ahd_reg_print_t ahd_bustargid_print; 438 #else 439 #define ahd_bustargid_print(regvalue, cur_col, wrap) \ 440 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap) 441 #endif 442 443 #if AIC_DEBUG_REGISTERS 444 ahd_reg_print_t ahd_sxfrctl2_print; 445 #else 446 #define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \ 447 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap) 448 #endif 449 450 #if AIC_DEBUG_REGISTERS 451 ahd_reg_print_t ahd_dffstat_print; 452 #else 453 #define ahd_dffstat_print(regvalue, cur_col, wrap) \ 454 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap) 455 #endif 456 457 #if AIC_DEBUG_REGISTERS 458 ahd_reg_print_t ahd_scsisigo_print; 459 #else 460 #define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 461 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 462 #endif 463 464 #if AIC_DEBUG_REGISTERS 465 ahd_reg_print_t ahd_multargid_print; 466 #else 467 #define ahd_multargid_print(regvalue, cur_col, wrap) \ 468 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 469 #endif 470 471 #if AIC_DEBUG_REGISTERS 472 ahd_reg_print_t ahd_scsisigi_print; 473 #else 474 #define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 475 ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap) 476 #endif 477 478 #if AIC_DEBUG_REGISTERS 479 ahd_reg_print_t ahd_scsiphase_print; 480 #else 481 #define ahd_scsiphase_print(regvalue, cur_col, wrap) \ 482 ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap) 483 #endif 484 485 #if AIC_DEBUG_REGISTERS 486 ahd_reg_print_t ahd_scsidat0_img_print; 487 #else 488 #define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \ 489 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap) 490 #endif 491 492 #if AIC_DEBUG_REGISTERS 493 ahd_reg_print_t ahd_scsidat_print; 494 #else 495 #define ahd_scsidat_print(regvalue, cur_col, wrap) \ 496 ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap) 497 #endif 498 499 #if AIC_DEBUG_REGISTERS 500 ahd_reg_print_t ahd_scsibus_print; 501 #else 502 #define ahd_scsibus_print(regvalue, cur_col, wrap) \ 503 ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap) 504 #endif 505 506 #if AIC_DEBUG_REGISTERS 507 ahd_reg_print_t ahd_targidin_print; 508 #else 509 #define ahd_targidin_print(regvalue, cur_col, wrap) \ 510 ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap) 511 #endif 512 513 #if AIC_DEBUG_REGISTERS 514 ahd_reg_print_t ahd_selid_print; 515 #else 516 #define ahd_selid_print(regvalue, cur_col, wrap) \ 517 ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap) 518 #endif 519 520 #if AIC_DEBUG_REGISTERS 521 ahd_reg_print_t ahd_optionmode_print; 522 #else 523 #define ahd_optionmode_print(regvalue, cur_col, wrap) \ 524 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap) 525 #endif 526 527 #if AIC_DEBUG_REGISTERS 528 ahd_reg_print_t ahd_sblkctl_print; 529 #else 530 #define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 531 ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap) 532 #endif 533 534 #if AIC_DEBUG_REGISTERS 535 ahd_reg_print_t ahd_simode0_print; 536 #else 537 #define ahd_simode0_print(regvalue, cur_col, wrap) \ 538 ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap) 539 #endif 540 541 #if AIC_DEBUG_REGISTERS 542 ahd_reg_print_t ahd_sstat0_print; 543 #else 544 #define ahd_sstat0_print(regvalue, cur_col, wrap) \ 545 ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap) 546 #endif 547 548 #if AIC_DEBUG_REGISTERS 549 ahd_reg_print_t ahd_clrsint0_print; 550 #else 551 #define ahd_clrsint0_print(regvalue, cur_col, wrap) \ 552 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap) 553 #endif 554 555 #if AIC_DEBUG_REGISTERS 556 ahd_reg_print_t ahd_sstat1_print; 557 #else 558 #define ahd_sstat1_print(regvalue, cur_col, wrap) \ 559 ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap) 560 #endif 561 562 #if AIC_DEBUG_REGISTERS 563 ahd_reg_print_t ahd_clrsint1_print; 564 #else 565 #define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 566 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 567 #endif 568 569 #if AIC_DEBUG_REGISTERS 570 ahd_reg_print_t ahd_sstat2_print; 571 #else 572 #define ahd_sstat2_print(regvalue, cur_col, wrap) \ 573 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 574 #endif 575 576 #if AIC_DEBUG_REGISTERS 577 ahd_reg_print_t ahd_clrsint2_print; 578 #else 579 #define ahd_clrsint2_print(regvalue, cur_col, wrap) \ 580 ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap) 581 #endif 582 583 #if AIC_DEBUG_REGISTERS 584 ahd_reg_print_t ahd_simode2_print; 585 #else 586 #define ahd_simode2_print(regvalue, cur_col, wrap) \ 587 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap) 588 #endif 589 590 #if AIC_DEBUG_REGISTERS 591 ahd_reg_print_t ahd_perrdiag_print; 592 #else 593 #define ahd_perrdiag_print(regvalue, cur_col, wrap) \ 594 ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap) 595 #endif 596 597 #if AIC_DEBUG_REGISTERS 598 ahd_reg_print_t ahd_lqistate_print; 599 #else 600 #define ahd_lqistate_print(regvalue, cur_col, wrap) \ 601 ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap) 602 #endif 603 604 #if AIC_DEBUG_REGISTERS 605 ahd_reg_print_t ahd_soffcnt_print; 606 #else 607 #define ahd_soffcnt_print(regvalue, cur_col, wrap) \ 608 ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap) 609 #endif 610 611 #if AIC_DEBUG_REGISTERS 612 ahd_reg_print_t ahd_lqostate_print; 613 #else 614 #define ahd_lqostate_print(regvalue, cur_col, wrap) \ 615 ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap) 616 #endif 617 618 #if AIC_DEBUG_REGISTERS 619 ahd_reg_print_t ahd_lqistat0_print; 620 #else 621 #define ahd_lqistat0_print(regvalue, cur_col, wrap) \ 622 ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap) 623 #endif 624 625 #if AIC_DEBUG_REGISTERS 626 ahd_reg_print_t ahd_clrlqiint0_print; 627 #else 628 #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 629 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 630 #endif 631 632 #if AIC_DEBUG_REGISTERS 633 ahd_reg_print_t ahd_lqimode0_print; 634 #else 635 #define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 636 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 637 #endif 638 639 #if AIC_DEBUG_REGISTERS 640 ahd_reg_print_t ahd_lqistat1_print; 641 #else 642 #define ahd_lqistat1_print(regvalue, cur_col, wrap) \ 643 ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap) 644 #endif 645 646 #if AIC_DEBUG_REGISTERS 647 ahd_reg_print_t ahd_clrlqiint1_print; 648 #else 649 #define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \ 650 ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap) 651 #endif 652 653 #if AIC_DEBUG_REGISTERS 654 ahd_reg_print_t ahd_lqimode1_print; 655 #else 656 #define ahd_lqimode1_print(regvalue, cur_col, wrap) \ 657 ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap) 658 #endif 659 660 #if AIC_DEBUG_REGISTERS 661 ahd_reg_print_t ahd_lqistat2_print; 662 #else 663 #define ahd_lqistat2_print(regvalue, cur_col, wrap) \ 664 ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap) 665 #endif 666 667 #if AIC_DEBUG_REGISTERS 668 ahd_reg_print_t ahd_sstat3_print; 669 #else 670 #define ahd_sstat3_print(regvalue, cur_col, wrap) \ 671 ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap) 672 #endif 673 674 #if AIC_DEBUG_REGISTERS 675 ahd_reg_print_t ahd_clrsint3_print; 676 #else 677 #define ahd_clrsint3_print(regvalue, cur_col, wrap) \ 678 ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap) 679 #endif 680 681 #if AIC_DEBUG_REGISTERS 682 ahd_reg_print_t ahd_simode3_print; 683 #else 684 #define ahd_simode3_print(regvalue, cur_col, wrap) \ 685 ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap) 686 #endif 687 688 #if AIC_DEBUG_REGISTERS 689 ahd_reg_print_t ahd_lqomode0_print; 690 #else 691 #define ahd_lqomode0_print(regvalue, cur_col, wrap) \ 692 ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap) 693 #endif 694 695 #if AIC_DEBUG_REGISTERS 696 ahd_reg_print_t ahd_lqostat0_print; 697 #else 698 #define ahd_lqostat0_print(regvalue, cur_col, wrap) \ 699 ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap) 700 #endif 701 702 #if AIC_DEBUG_REGISTERS 703 ahd_reg_print_t ahd_clrlqoint0_print; 704 #else 705 #define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \ 706 ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap) 707 #endif 708 709 #if AIC_DEBUG_REGISTERS 710 ahd_reg_print_t ahd_lqomode1_print; 711 #else 712 #define ahd_lqomode1_print(regvalue, cur_col, wrap) \ 713 ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap) 714 #endif 715 716 #if AIC_DEBUG_REGISTERS 717 ahd_reg_print_t ahd_lqostat1_print; 718 #else 719 #define ahd_lqostat1_print(regvalue, cur_col, wrap) \ 720 ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap) 721 #endif 722 723 #if AIC_DEBUG_REGISTERS 724 ahd_reg_print_t ahd_clrlqoint1_print; 725 #else 726 #define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \ 727 ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap) 728 #endif 729 730 #if AIC_DEBUG_REGISTERS 731 ahd_reg_print_t ahd_os_space_cnt_print; 732 #else 733 #define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \ 734 ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap) 735 #endif 736 737 #if AIC_DEBUG_REGISTERS 738 ahd_reg_print_t ahd_lqostat2_print; 739 #else 740 #define ahd_lqostat2_print(regvalue, cur_col, wrap) \ 741 ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap) 742 #endif 743 744 #if AIC_DEBUG_REGISTERS 745 ahd_reg_print_t ahd_simode1_print; 746 #else 747 #define ahd_simode1_print(regvalue, cur_col, wrap) \ 748 ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap) 749 #endif 750 751 #if AIC_DEBUG_REGISTERS 752 ahd_reg_print_t ahd_gsfifo_print; 753 #else 754 #define ahd_gsfifo_print(regvalue, cur_col, wrap) \ 755 ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap) 756 #endif 757 758 #if AIC_DEBUG_REGISTERS 759 ahd_reg_print_t ahd_dffsxfrctl_print; 760 #else 761 #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \ 762 ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap) 763 #endif 764 765 #if AIC_DEBUG_REGISTERS 766 ahd_reg_print_t ahd_nextscb_print; 767 #else 768 #define ahd_nextscb_print(regvalue, cur_col, wrap) \ 769 ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap) 770 #endif 771 772 #if AIC_DEBUG_REGISTERS 773 ahd_reg_print_t ahd_lqoscsctl_print; 774 #else 775 #define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \ 776 ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap) 777 #endif 778 779 #if AIC_DEBUG_REGISTERS 780 ahd_reg_print_t ahd_seqintsrc_print; 781 #else 782 #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \ 783 ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap) 784 #endif 785 786 #if AIC_DEBUG_REGISTERS 787 ahd_reg_print_t ahd_clrseqintsrc_print; 788 #else 789 #define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \ 790 ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap) 791 #endif 792 793 #if AIC_DEBUG_REGISTERS 794 ahd_reg_print_t ahd_currscb_print; 795 #else 796 #define ahd_currscb_print(regvalue, cur_col, wrap) \ 797 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 798 #endif 799 800 #if AIC_DEBUG_REGISTERS 801 ahd_reg_print_t ahd_seqimode_print; 802 #else 803 #define ahd_seqimode_print(regvalue, cur_col, wrap) \ 804 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 805 #endif 806 807 #if AIC_DEBUG_REGISTERS 808 ahd_reg_print_t ahd_mdffstat_print; 809 #else 810 #define ahd_mdffstat_print(regvalue, cur_col, wrap) \ 811 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap) 812 #endif 813 814 #if AIC_DEBUG_REGISTERS 815 ahd_reg_print_t ahd_crccontrol_print; 816 #else 817 #define ahd_crccontrol_print(regvalue, cur_col, wrap) \ 818 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap) 819 #endif 820 821 #if AIC_DEBUG_REGISTERS 822 ahd_reg_print_t ahd_scsitest_print; 823 #else 824 #define ahd_scsitest_print(regvalue, cur_col, wrap) \ 825 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap) 826 #endif 827 828 #if AIC_DEBUG_REGISTERS 829 ahd_reg_print_t ahd_dfftag_print; 830 #else 831 #define ahd_dfftag_print(regvalue, cur_col, wrap) \ 832 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap) 833 #endif 834 835 #if AIC_DEBUG_REGISTERS 836 ahd_reg_print_t ahd_lastscb_print; 837 #else 838 #define ahd_lastscb_print(regvalue, cur_col, wrap) \ 839 ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap) 840 #endif 841 842 #if AIC_DEBUG_REGISTERS 843 ahd_reg_print_t ahd_iopdnctl_print; 844 #else 845 #define ahd_iopdnctl_print(regvalue, cur_col, wrap) \ 846 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap) 847 #endif 848 849 #if AIC_DEBUG_REGISTERS 850 ahd_reg_print_t ahd_negoaddr_print; 851 #else 852 #define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 853 ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap) 854 #endif 855 856 #if AIC_DEBUG_REGISTERS 857 ahd_reg_print_t ahd_shaddr_print; 858 #else 859 #define ahd_shaddr_print(regvalue, cur_col, wrap) \ 860 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap) 861 #endif 862 863 #if AIC_DEBUG_REGISTERS 864 ahd_reg_print_t ahd_dgrpcrci_print; 865 #else 866 #define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \ 867 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap) 868 #endif 869 870 #if AIC_DEBUG_REGISTERS 871 ahd_reg_print_t ahd_negperiod_print; 872 #else 873 #define ahd_negperiod_print(regvalue, cur_col, wrap) \ 874 ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap) 875 #endif 876 877 #if AIC_DEBUG_REGISTERS 878 ahd_reg_print_t ahd_packcrci_print; 879 #else 880 #define ahd_packcrci_print(regvalue, cur_col, wrap) \ 881 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap) 882 #endif 883 884 #if AIC_DEBUG_REGISTERS 885 ahd_reg_print_t ahd_negoffset_print; 886 #else 887 #define ahd_negoffset_print(regvalue, cur_col, wrap) \ 888 ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap) 889 #endif 890 891 #if AIC_DEBUG_REGISTERS 892 ahd_reg_print_t ahd_negppropts_print; 893 #else 894 #define ahd_negppropts_print(regvalue, cur_col, wrap) \ 895 ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap) 896 #endif 897 898 #if AIC_DEBUG_REGISTERS 899 ahd_reg_print_t ahd_negconopts_print; 900 #else 901 #define ahd_negconopts_print(regvalue, cur_col, wrap) \ 902 ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap) 903 #endif 904 905 #if AIC_DEBUG_REGISTERS 906 ahd_reg_print_t ahd_annexcol_print; 907 #else 908 #define ahd_annexcol_print(regvalue, cur_col, wrap) \ 909 ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap) 910 #endif 911 912 #if AIC_DEBUG_REGISTERS 913 ahd_reg_print_t ahd_annexdat_print; 914 #else 915 #define ahd_annexdat_print(regvalue, cur_col, wrap) \ 916 ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap) 917 #endif 918 919 #if AIC_DEBUG_REGISTERS 920 ahd_reg_print_t ahd_scschkn_print; 921 #else 922 #define ahd_scschkn_print(regvalue, cur_col, wrap) \ 923 ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap) 924 #endif 925 926 #if AIC_DEBUG_REGISTERS 927 ahd_reg_print_t ahd_iownid_print; 928 #else 929 #define ahd_iownid_print(regvalue, cur_col, wrap) \ 930 ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap) 931 #endif 932 933 #if AIC_DEBUG_REGISTERS 934 ahd_reg_print_t ahd_shcnt_print; 935 #else 936 #define ahd_shcnt_print(regvalue, cur_col, wrap) \ 937 ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap) 938 #endif 939 940 #if AIC_DEBUG_REGISTERS 941 ahd_reg_print_t ahd_pll960ctl0_print; 942 #else 943 #define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \ 944 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap) 945 #endif 946 947 #if AIC_DEBUG_REGISTERS 948 ahd_reg_print_t ahd_pll960ctl1_print; 949 #else 950 #define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \ 951 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap) 952 #endif 953 954 #if AIC_DEBUG_REGISTERS 955 ahd_reg_print_t ahd_townid_print; 956 #else 957 #define ahd_townid_print(regvalue, cur_col, wrap) \ 958 ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap) 959 #endif 960 961 #if AIC_DEBUG_REGISTERS 962 ahd_reg_print_t ahd_xsig_print; 963 #else 964 #define ahd_xsig_print(regvalue, cur_col, wrap) \ 965 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap) 966 #endif 967 968 #if AIC_DEBUG_REGISTERS 969 ahd_reg_print_t ahd_pll960cnt0_print; 970 #else 971 #define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \ 972 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap) 973 #endif 974 975 #if AIC_DEBUG_REGISTERS 976 ahd_reg_print_t ahd_seloid_print; 977 #else 978 #define ahd_seloid_print(regvalue, cur_col, wrap) \ 979 ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap) 980 #endif 981 982 #if AIC_DEBUG_REGISTERS 983 ahd_reg_print_t ahd_fairness_print; 984 #else 985 #define ahd_fairness_print(regvalue, cur_col, wrap) \ 986 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap) 987 #endif 988 989 #if AIC_DEBUG_REGISTERS 990 ahd_reg_print_t ahd_pll400ctl0_print; 991 #else 992 #define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \ 993 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap) 994 #endif 995 996 #if AIC_DEBUG_REGISTERS 997 ahd_reg_print_t ahd_pll400ctl1_print; 998 #else 999 #define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \ 1000 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap) 1001 #endif 1002 1003 #if AIC_DEBUG_REGISTERS 1004 ahd_reg_print_t ahd_pll400cnt0_print; 1005 #else 1006 #define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \ 1007 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap) 1008 #endif 1009 1010 #if AIC_DEBUG_REGISTERS 1011 ahd_reg_print_t ahd_unfairness_print; 1012 #else 1013 #define ahd_unfairness_print(regvalue, cur_col, wrap) \ 1014 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap) 1015 #endif 1016 1017 #if AIC_DEBUG_REGISTERS 1018 ahd_reg_print_t ahd_hodmaadr_print; 1019 #else 1020 #define ahd_hodmaadr_print(regvalue, cur_col, wrap) \ 1021 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap) 1022 #endif 1023 1024 #if AIC_DEBUG_REGISTERS 1025 ahd_reg_print_t ahd_haddr_print; 1026 #else 1027 #define ahd_haddr_print(regvalue, cur_col, wrap) \ 1028 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap) 1029 #endif 1030 1031 #if AIC_DEBUG_REGISTERS 1032 ahd_reg_print_t ahd_plldelay_print; 1033 #else 1034 #define ahd_plldelay_print(regvalue, cur_col, wrap) \ 1035 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap) 1036 #endif 1037 1038 #if AIC_DEBUG_REGISTERS 1039 ahd_reg_print_t ahd_hcnt_print; 1040 #else 1041 #define ahd_hcnt_print(regvalue, cur_col, wrap) \ 1042 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap) 1043 #endif 1044 1045 #if AIC_DEBUG_REGISTERS 1046 ahd_reg_print_t ahd_hodmacnt_print; 1047 #else 1048 #define ahd_hodmacnt_print(regvalue, cur_col, wrap) \ 1049 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap) 1050 #endif 1051 1052 #if AIC_DEBUG_REGISTERS 1053 ahd_reg_print_t ahd_hodmaen_print; 1054 #else 1055 #define ahd_hodmaen_print(regvalue, cur_col, wrap) \ 1056 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap) 1057 #endif 1058 1059 #if AIC_DEBUG_REGISTERS 1060 ahd_reg_print_t ahd_scbhaddr_print; 1061 #else 1062 #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 1063 ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap) 1064 #endif 1065 1066 #if AIC_DEBUG_REGISTERS 1067 ahd_reg_print_t ahd_sghaddr_print; 1068 #else 1069 #define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 1070 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 1071 #endif 1072 1073 #if AIC_DEBUG_REGISTERS 1074 ahd_reg_print_t ahd_scbhcnt_print; 1075 #else 1076 #define ahd_scbhcnt_print(regvalue, cur_col, wrap) \ 1077 ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap) 1078 #endif 1079 1080 #if AIC_DEBUG_REGISTERS 1081 ahd_reg_print_t ahd_sghcnt_print; 1082 #else 1083 #define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 1084 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 1085 #endif 1086 1087 #if AIC_DEBUG_REGISTERS 1088 ahd_reg_print_t ahd_dff_thrsh_print; 1089 #else 1090 #define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 1091 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 1092 #endif 1093 1094 #if AIC_DEBUG_REGISTERS 1095 ahd_reg_print_t ahd_romaddr_print; 1096 #else 1097 #define ahd_romaddr_print(regvalue, cur_col, wrap) \ 1098 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap) 1099 #endif 1100 1101 #if AIC_DEBUG_REGISTERS 1102 ahd_reg_print_t ahd_romcntrl_print; 1103 #else 1104 #define ahd_romcntrl_print(regvalue, cur_col, wrap) \ 1105 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap) 1106 #endif 1107 1108 #if AIC_DEBUG_REGISTERS 1109 ahd_reg_print_t ahd_romdata_print; 1110 #else 1111 #define ahd_romdata_print(regvalue, cur_col, wrap) \ 1112 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap) 1113 #endif 1114 1115 #if AIC_DEBUG_REGISTERS 1116 ahd_reg_print_t ahd_dchrxmsg0_print; 1117 #else 1118 #define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \ 1119 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap) 1120 #endif 1121 1122 #if AIC_DEBUG_REGISTERS 1123 ahd_reg_print_t ahd_ovlyrxmsg0_print; 1124 #else 1125 #define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \ 1126 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap) 1127 #endif 1128 1129 #if AIC_DEBUG_REGISTERS 1130 ahd_reg_print_t ahd_cmcrxmsg0_print; 1131 #else 1132 #define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \ 1133 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap) 1134 #endif 1135 1136 #if AIC_DEBUG_REGISTERS 1137 ahd_reg_print_t ahd_roenable_print; 1138 #else 1139 #define ahd_roenable_print(regvalue, cur_col, wrap) \ 1140 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap) 1141 #endif 1142 1143 #if AIC_DEBUG_REGISTERS 1144 ahd_reg_print_t ahd_dchrxmsg1_print; 1145 #else 1146 #define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \ 1147 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap) 1148 #endif 1149 1150 #if AIC_DEBUG_REGISTERS 1151 ahd_reg_print_t ahd_ovlyrxmsg1_print; 1152 #else 1153 #define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \ 1154 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap) 1155 #endif 1156 1157 #if AIC_DEBUG_REGISTERS 1158 ahd_reg_print_t ahd_cmcrxmsg1_print; 1159 #else 1160 #define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \ 1161 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap) 1162 #endif 1163 1164 #if AIC_DEBUG_REGISTERS 1165 ahd_reg_print_t ahd_nsenable_print; 1166 #else 1167 #define ahd_nsenable_print(regvalue, cur_col, wrap) \ 1168 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap) 1169 #endif 1170 1171 #if AIC_DEBUG_REGISTERS 1172 ahd_reg_print_t ahd_dchrxmsg2_print; 1173 #else 1174 #define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \ 1175 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap) 1176 #endif 1177 1178 #if AIC_DEBUG_REGISTERS 1179 ahd_reg_print_t ahd_ovlyrxmsg2_print; 1180 #else 1181 #define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \ 1182 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap) 1183 #endif 1184 1185 #if AIC_DEBUG_REGISTERS 1186 ahd_reg_print_t ahd_cmcrxmsg2_print; 1187 #else 1188 #define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \ 1189 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap) 1190 #endif 1191 1192 #if AIC_DEBUG_REGISTERS 1193 ahd_reg_print_t ahd_ost_print; 1194 #else 1195 #define ahd_ost_print(regvalue, cur_col, wrap) \ 1196 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap) 1197 #endif 1198 1199 #if AIC_DEBUG_REGISTERS 1200 ahd_reg_print_t ahd_dchrxmsg3_print; 1201 #else 1202 #define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \ 1203 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap) 1204 #endif 1205 1206 #if AIC_DEBUG_REGISTERS 1207 ahd_reg_print_t ahd_ovlyrxmsg3_print; 1208 #else 1209 #define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \ 1210 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap) 1211 #endif 1212 1213 #if AIC_DEBUG_REGISTERS 1214 ahd_reg_print_t ahd_cmcrxmsg3_print; 1215 #else 1216 #define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \ 1217 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap) 1218 #endif 1219 1220 #if AIC_DEBUG_REGISTERS 1221 ahd_reg_print_t ahd_pcixctl_print; 1222 #else 1223 #define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 1224 ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap) 1225 #endif 1226 1227 #if AIC_DEBUG_REGISTERS 1228 ahd_reg_print_t ahd_ovlyseqbcnt_print; 1229 #else 1230 #define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \ 1231 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap) 1232 #endif 1233 1234 #if AIC_DEBUG_REGISTERS 1235 ahd_reg_print_t ahd_cmcseqbcnt_print; 1236 #else 1237 #define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \ 1238 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap) 1239 #endif 1240 1241 #if AIC_DEBUG_REGISTERS 1242 ahd_reg_print_t ahd_dchseqbcnt_print; 1243 #else 1244 #define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \ 1245 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap) 1246 #endif 1247 1248 #if AIC_DEBUG_REGISTERS 1249 ahd_reg_print_t ahd_cmcspltstat0_print; 1250 #else 1251 #define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \ 1252 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1253 #endif 1254 1255 #if AIC_DEBUG_REGISTERS 1256 ahd_reg_print_t ahd_dchspltstat0_print; 1257 #else 1258 #define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 1259 ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1260 #endif 1261 1262 #if AIC_DEBUG_REGISTERS 1263 ahd_reg_print_t ahd_ovlyspltstat0_print; 1264 #else 1265 #define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \ 1266 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 1267 #endif 1268 1269 #if AIC_DEBUG_REGISTERS 1270 ahd_reg_print_t ahd_ovlyspltstat1_print; 1271 #else 1272 #define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \ 1273 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1274 #endif 1275 1276 #if AIC_DEBUG_REGISTERS 1277 ahd_reg_print_t ahd_cmcspltstat1_print; 1278 #else 1279 #define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \ 1280 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1281 #endif 1282 1283 #if AIC_DEBUG_REGISTERS 1284 ahd_reg_print_t ahd_dchspltstat1_print; 1285 #else 1286 #define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 1287 ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 1288 #endif 1289 1290 #if AIC_DEBUG_REGISTERS 1291 ahd_reg_print_t ahd_sgrxmsg0_print; 1292 #else 1293 #define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \ 1294 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap) 1295 #endif 1296 1297 #if AIC_DEBUG_REGISTERS 1298 ahd_reg_print_t ahd_slvspltoutadr0_print; 1299 #else 1300 #define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \ 1301 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap) 1302 #endif 1303 1304 #if AIC_DEBUG_REGISTERS 1305 ahd_reg_print_t ahd_sgrxmsg1_print; 1306 #else 1307 #define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \ 1308 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap) 1309 #endif 1310 1311 #if AIC_DEBUG_REGISTERS 1312 ahd_reg_print_t ahd_slvspltoutadr1_print; 1313 #else 1314 #define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \ 1315 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap) 1316 #endif 1317 1318 #if AIC_DEBUG_REGISTERS 1319 ahd_reg_print_t ahd_sgrxmsg2_print; 1320 #else 1321 #define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \ 1322 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap) 1323 #endif 1324 1325 #if AIC_DEBUG_REGISTERS 1326 ahd_reg_print_t ahd_slvspltoutadr2_print; 1327 #else 1328 #define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \ 1329 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap) 1330 #endif 1331 1332 #if AIC_DEBUG_REGISTERS 1333 ahd_reg_print_t ahd_slvspltoutadr3_print; 1334 #else 1335 #define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \ 1336 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap) 1337 #endif 1338 1339 #if AIC_DEBUG_REGISTERS 1340 ahd_reg_print_t ahd_sgrxmsg3_print; 1341 #else 1342 #define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \ 1343 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap) 1344 #endif 1345 1346 #if AIC_DEBUG_REGISTERS 1347 ahd_reg_print_t ahd_sgseqbcnt_print; 1348 #else 1349 #define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \ 1350 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap) 1351 #endif 1352 1353 #if AIC_DEBUG_REGISTERS 1354 ahd_reg_print_t ahd_slvspltoutattr0_print; 1355 #else 1356 #define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \ 1357 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap) 1358 #endif 1359 1360 #if AIC_DEBUG_REGISTERS 1361 ahd_reg_print_t ahd_slvspltoutattr1_print; 1362 #else 1363 #define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \ 1364 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap) 1365 #endif 1366 1367 #if AIC_DEBUG_REGISTERS 1368 ahd_reg_print_t ahd_slvspltoutattr2_print; 1369 #else 1370 #define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \ 1371 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap) 1372 #endif 1373 1374 #if AIC_DEBUG_REGISTERS 1375 ahd_reg_print_t ahd_sgspltstat0_print; 1376 #else 1377 #define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 1378 ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap) 1379 #endif 1380 1381 #if AIC_DEBUG_REGISTERS 1382 ahd_reg_print_t ahd_sgspltstat1_print; 1383 #else 1384 #define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \ 1385 ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap) 1386 #endif 1387 1388 #if AIC_DEBUG_REGISTERS 1389 ahd_reg_print_t ahd_sfunct_print; 1390 #else 1391 #define ahd_sfunct_print(regvalue, cur_col, wrap) \ 1392 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 1393 #endif 1394 1395 #if AIC_DEBUG_REGISTERS 1396 ahd_reg_print_t ahd_df0pcistat_print; 1397 #else 1398 #define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 1399 ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap) 1400 #endif 1401 1402 #if AIC_DEBUG_REGISTERS 1403 ahd_reg_print_t ahd_reg0_print; 1404 #else 1405 #define ahd_reg0_print(regvalue, cur_col, wrap) \ 1406 ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap) 1407 #endif 1408 1409 #if AIC_DEBUG_REGISTERS 1410 ahd_reg_print_t ahd_df1pcistat_print; 1411 #else 1412 #define ahd_df1pcistat_print(regvalue, cur_col, wrap) \ 1413 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap) 1414 #endif 1415 1416 #if AIC_DEBUG_REGISTERS 1417 ahd_reg_print_t ahd_sgpcistat_print; 1418 #else 1419 #define ahd_sgpcistat_print(regvalue, cur_col, wrap) \ 1420 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap) 1421 #endif 1422 1423 #if AIC_DEBUG_REGISTERS 1424 ahd_reg_print_t ahd_reg1_print; 1425 #else 1426 #define ahd_reg1_print(regvalue, cur_col, wrap) \ 1427 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap) 1428 #endif 1429 1430 #if AIC_DEBUG_REGISTERS 1431 ahd_reg_print_t ahd_cmcpcistat_print; 1432 #else 1433 #define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \ 1434 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap) 1435 #endif 1436 1437 #if AIC_DEBUG_REGISTERS 1438 ahd_reg_print_t ahd_ovlypcistat_print; 1439 #else 1440 #define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \ 1441 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap) 1442 #endif 1443 1444 #if AIC_DEBUG_REGISTERS 1445 ahd_reg_print_t ahd_reg_isr_print; 1446 #else 1447 #define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 1448 ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap) 1449 #endif 1450 1451 #if AIC_DEBUG_REGISTERS 1452 ahd_reg_print_t ahd_msipcistat_print; 1453 #else 1454 #define ahd_msipcistat_print(regvalue, cur_col, wrap) \ 1455 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap) 1456 #endif 1457 1458 #if AIC_DEBUG_REGISTERS 1459 ahd_reg_print_t ahd_sg_state_print; 1460 #else 1461 #define ahd_sg_state_print(regvalue, cur_col, wrap) \ 1462 ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap) 1463 #endif 1464 1465 #if AIC_DEBUG_REGISTERS 1466 ahd_reg_print_t ahd_targpcistat_print; 1467 #else 1468 #define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 1469 ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap) 1470 #endif 1471 1472 #if AIC_DEBUG_REGISTERS 1473 ahd_reg_print_t ahd_data_count_odd_print; 1474 #else 1475 #define ahd_data_count_odd_print(regvalue, cur_col, wrap) \ 1476 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap) 1477 #endif 1478 1479 #if AIC_DEBUG_REGISTERS 1480 ahd_reg_print_t ahd_scbptr_print; 1481 #else 1482 #define ahd_scbptr_print(regvalue, cur_col, wrap) \ 1483 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap) 1484 #endif 1485 1486 #if AIC_DEBUG_REGISTERS 1487 ahd_reg_print_t ahd_ccscbacnt_print; 1488 #else 1489 #define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \ 1490 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap) 1491 #endif 1492 1493 #if AIC_DEBUG_REGISTERS 1494 ahd_reg_print_t ahd_scbautoptr_print; 1495 #else 1496 #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 1497 ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap) 1498 #endif 1499 1500 #if AIC_DEBUG_REGISTERS 1501 ahd_reg_print_t ahd_ccscbadr_bk_print; 1502 #else 1503 #define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \ 1504 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap) 1505 #endif 1506 1507 #if AIC_DEBUG_REGISTERS 1508 ahd_reg_print_t ahd_ccsgaddr_print; 1509 #else 1510 #define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \ 1511 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap) 1512 #endif 1513 1514 #if AIC_DEBUG_REGISTERS 1515 ahd_reg_print_t ahd_ccscbaddr_print; 1516 #else 1517 #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 1518 ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap) 1519 #endif 1520 1521 #if AIC_DEBUG_REGISTERS 1522 ahd_reg_print_t ahd_ccscbctl_print; 1523 #else 1524 #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 1525 ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap) 1526 #endif 1527 1528 #if AIC_DEBUG_REGISTERS 1529 ahd_reg_print_t ahd_ccsgctl_print; 1530 #else 1531 #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \ 1532 ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap) 1533 #endif 1534 1535 #if AIC_DEBUG_REGISTERS 1536 ahd_reg_print_t ahd_cmc_rambist_print; 1537 #else 1538 #define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \ 1539 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap) 1540 #endif 1541 1542 #if AIC_DEBUG_REGISTERS 1543 ahd_reg_print_t ahd_ccsgram_print; 1544 #else 1545 #define ahd_ccsgram_print(regvalue, cur_col, wrap) \ 1546 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap) 1547 #endif 1548 1549 #if AIC_DEBUG_REGISTERS 1550 ahd_reg_print_t ahd_ccscbram_print; 1551 #else 1552 #define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 1553 ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap) 1554 #endif 1555 1556 #if AIC_DEBUG_REGISTERS 1557 ahd_reg_print_t ahd_flexadr_print; 1558 #else 1559 #define ahd_flexadr_print(regvalue, cur_col, wrap) \ 1560 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap) 1561 #endif 1562 1563 #if AIC_DEBUG_REGISTERS 1564 ahd_reg_print_t ahd_flexcnt_print; 1565 #else 1566 #define ahd_flexcnt_print(regvalue, cur_col, wrap) \ 1567 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap) 1568 #endif 1569 1570 #if AIC_DEBUG_REGISTERS 1571 ahd_reg_print_t ahd_flexdmastat_print; 1572 #else 1573 #define ahd_flexdmastat_print(regvalue, cur_col, wrap) \ 1574 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap) 1575 #endif 1576 1577 #if AIC_DEBUG_REGISTERS 1578 ahd_reg_print_t ahd_flexdata_print; 1579 #else 1580 #define ahd_flexdata_print(regvalue, cur_col, wrap) \ 1581 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap) 1582 #endif 1583 1584 #if AIC_DEBUG_REGISTERS 1585 ahd_reg_print_t ahd_brddat_print; 1586 #else 1587 #define ahd_brddat_print(regvalue, cur_col, wrap) \ 1588 ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap) 1589 #endif 1590 1591 #if AIC_DEBUG_REGISTERS 1592 ahd_reg_print_t ahd_brdctl_print; 1593 #else 1594 #define ahd_brdctl_print(regvalue, cur_col, wrap) \ 1595 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap) 1596 #endif 1597 1598 #if AIC_DEBUG_REGISTERS 1599 ahd_reg_print_t ahd_seeadr_print; 1600 #else 1601 #define ahd_seeadr_print(regvalue, cur_col, wrap) \ 1602 ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap) 1603 #endif 1604 1605 #if AIC_DEBUG_REGISTERS 1606 ahd_reg_print_t ahd_seedat_print; 1607 #else 1608 #define ahd_seedat_print(regvalue, cur_col, wrap) \ 1609 ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap) 1610 #endif 1611 1612 #if AIC_DEBUG_REGISTERS 1613 ahd_reg_print_t ahd_seectl_print; 1614 #else 1615 #define ahd_seectl_print(regvalue, cur_col, wrap) \ 1616 ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap) 1617 #endif 1618 1619 #if AIC_DEBUG_REGISTERS 1620 ahd_reg_print_t ahd_seestat_print; 1621 #else 1622 #define ahd_seestat_print(regvalue, cur_col, wrap) \ 1623 ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap) 1624 #endif 1625 1626 #if AIC_DEBUG_REGISTERS 1627 ahd_reg_print_t ahd_scbcnt_print; 1628 #else 1629 #define ahd_scbcnt_print(regvalue, cur_col, wrap) \ 1630 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap) 1631 #endif 1632 1633 #if AIC_DEBUG_REGISTERS 1634 ahd_reg_print_t ahd_dspfltrctl_print; 1635 #else 1636 #define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \ 1637 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap) 1638 #endif 1639 1640 #if AIC_DEBUG_REGISTERS 1641 ahd_reg_print_t ahd_dfwaddr_print; 1642 #else 1643 #define ahd_dfwaddr_print(regvalue, cur_col, wrap) \ 1644 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap) 1645 #endif 1646 1647 #if AIC_DEBUG_REGISTERS 1648 ahd_reg_print_t ahd_dspdatactl_print; 1649 #else 1650 #define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 1651 ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap) 1652 #endif 1653 1654 #if AIC_DEBUG_REGISTERS 1655 ahd_reg_print_t ahd_dspreqctl_print; 1656 #else 1657 #define ahd_dspreqctl_print(regvalue, cur_col, wrap) \ 1658 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap) 1659 #endif 1660 1661 #if AIC_DEBUG_REGISTERS 1662 ahd_reg_print_t ahd_dfraddr_print; 1663 #else 1664 #define ahd_dfraddr_print(regvalue, cur_col, wrap) \ 1665 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap) 1666 #endif 1667 1668 #if AIC_DEBUG_REGISTERS 1669 ahd_reg_print_t ahd_dspackctl_print; 1670 #else 1671 #define ahd_dspackctl_print(regvalue, cur_col, wrap) \ 1672 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap) 1673 #endif 1674 1675 #if AIC_DEBUG_REGISTERS 1676 ahd_reg_print_t ahd_dfdat_print; 1677 #else 1678 #define ahd_dfdat_print(regvalue, cur_col, wrap) \ 1679 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap) 1680 #endif 1681 1682 #if AIC_DEBUG_REGISTERS 1683 ahd_reg_print_t ahd_dspselect_print; 1684 #else 1685 #define ahd_dspselect_print(regvalue, cur_col, wrap) \ 1686 ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap) 1687 #endif 1688 1689 #if AIC_DEBUG_REGISTERS 1690 ahd_reg_print_t ahd_wrtbiasctl_print; 1691 #else 1692 #define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \ 1693 ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap) 1694 #endif 1695 1696 #if AIC_DEBUG_REGISTERS 1697 ahd_reg_print_t ahd_rcvrbiosctl_print; 1698 #else 1699 #define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \ 1700 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap) 1701 #endif 1702 1703 #if AIC_DEBUG_REGISTERS 1704 ahd_reg_print_t ahd_wrtbiascalc_print; 1705 #else 1706 #define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \ 1707 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap) 1708 #endif 1709 1710 #if AIC_DEBUG_REGISTERS 1711 ahd_reg_print_t ahd_dfptrs_print; 1712 #else 1713 #define ahd_dfptrs_print(regvalue, cur_col, wrap) \ 1714 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap) 1715 #endif 1716 1717 #if AIC_DEBUG_REGISTERS 1718 ahd_reg_print_t ahd_rcvrbiascalc_print; 1719 #else 1720 #define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \ 1721 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap) 1722 #endif 1723 1724 #if AIC_DEBUG_REGISTERS 1725 ahd_reg_print_t ahd_dfbkptr_print; 1726 #else 1727 #define ahd_dfbkptr_print(regvalue, cur_col, wrap) \ 1728 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap) 1729 #endif 1730 1731 #if AIC_DEBUG_REGISTERS 1732 ahd_reg_print_t ahd_skewcalc_print; 1733 #else 1734 #define ahd_skewcalc_print(regvalue, cur_col, wrap) \ 1735 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap) 1736 #endif 1737 1738 #if AIC_DEBUG_REGISTERS 1739 ahd_reg_print_t ahd_dfdbctl_print; 1740 #else 1741 #define ahd_dfdbctl_print(regvalue, cur_col, wrap) \ 1742 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap) 1743 #endif 1744 1745 #if AIC_DEBUG_REGISTERS 1746 ahd_reg_print_t ahd_dfscnt_print; 1747 #else 1748 #define ahd_dfscnt_print(regvalue, cur_col, wrap) \ 1749 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap) 1750 #endif 1751 1752 #if AIC_DEBUG_REGISTERS 1753 ahd_reg_print_t ahd_dfbcnt_print; 1754 #else 1755 #define ahd_dfbcnt_print(regvalue, cur_col, wrap) \ 1756 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap) 1757 #endif 1758 1759 #if AIC_DEBUG_REGISTERS 1760 ahd_reg_print_t ahd_ovlyaddr_print; 1761 #else 1762 #define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \ 1763 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap) 1764 #endif 1765 1766 #if AIC_DEBUG_REGISTERS 1767 ahd_reg_print_t ahd_seqctl0_print; 1768 #else 1769 #define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 1770 ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap) 1771 #endif 1772 1773 #if AIC_DEBUG_REGISTERS 1774 ahd_reg_print_t ahd_seqctl1_print; 1775 #else 1776 #define ahd_seqctl1_print(regvalue, cur_col, wrap) \ 1777 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap) 1778 #endif 1779 1780 #if AIC_DEBUG_REGISTERS 1781 ahd_reg_print_t ahd_flags_print; 1782 #else 1783 #define ahd_flags_print(regvalue, cur_col, wrap) \ 1784 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap) 1785 #endif 1786 1787 #if AIC_DEBUG_REGISTERS 1788 ahd_reg_print_t ahd_seqintctl_print; 1789 #else 1790 #define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 1791 ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap) 1792 #endif 1793 1794 #if AIC_DEBUG_REGISTERS 1795 ahd_reg_print_t ahd_seqram_print; 1796 #else 1797 #define ahd_seqram_print(regvalue, cur_col, wrap) \ 1798 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap) 1799 #endif 1800 1801 #if AIC_DEBUG_REGISTERS 1802 ahd_reg_print_t ahd_prgmcnt_print; 1803 #else 1804 #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 1805 ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap) 1806 #endif 1807 1808 #if AIC_DEBUG_REGISTERS 1809 ahd_reg_print_t ahd_accum_print; 1810 #else 1811 #define ahd_accum_print(regvalue, cur_col, wrap) \ 1812 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap) 1813 #endif 1814 1815 #if AIC_DEBUG_REGISTERS 1816 ahd_reg_print_t ahd_sindex_print; 1817 #else 1818 #define ahd_sindex_print(regvalue, cur_col, wrap) \ 1819 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap) 1820 #endif 1821 1822 #if AIC_DEBUG_REGISTERS 1823 ahd_reg_print_t ahd_dindex_print; 1824 #else 1825 #define ahd_dindex_print(regvalue, cur_col, wrap) \ 1826 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap) 1827 #endif 1828 1829 #if AIC_DEBUG_REGISTERS 1830 ahd_reg_print_t ahd_brkaddr0_print; 1831 #else 1832 #define ahd_brkaddr0_print(regvalue, cur_col, wrap) \ 1833 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap) 1834 #endif 1835 1836 #if AIC_DEBUG_REGISTERS 1837 ahd_reg_print_t ahd_brkaddr1_print; 1838 #else 1839 #define ahd_brkaddr1_print(regvalue, cur_col, wrap) \ 1840 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap) 1841 #endif 1842 1843 #if AIC_DEBUG_REGISTERS 1844 ahd_reg_print_t ahd_allones_print; 1845 #else 1846 #define ahd_allones_print(regvalue, cur_col, wrap) \ 1847 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap) 1848 #endif 1849 1850 #if AIC_DEBUG_REGISTERS 1851 ahd_reg_print_t ahd_none_print; 1852 #else 1853 #define ahd_none_print(regvalue, cur_col, wrap) \ 1854 ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap) 1855 #endif 1856 1857 #if AIC_DEBUG_REGISTERS 1858 ahd_reg_print_t ahd_allzeros_print; 1859 #else 1860 #define ahd_allzeros_print(regvalue, cur_col, wrap) \ 1861 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap) 1862 #endif 1863 1864 #if AIC_DEBUG_REGISTERS 1865 ahd_reg_print_t ahd_sindir_print; 1866 #else 1867 #define ahd_sindir_print(regvalue, cur_col, wrap) \ 1868 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap) 1869 #endif 1870 1871 #if AIC_DEBUG_REGISTERS 1872 ahd_reg_print_t ahd_dindir_print; 1873 #else 1874 #define ahd_dindir_print(regvalue, cur_col, wrap) \ 1875 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap) 1876 #endif 1877 1878 #if AIC_DEBUG_REGISTERS 1879 ahd_reg_print_t ahd_function1_print; 1880 #else 1881 #define ahd_function1_print(regvalue, cur_col, wrap) \ 1882 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap) 1883 #endif 1884 1885 #if AIC_DEBUG_REGISTERS 1886 ahd_reg_print_t ahd_stack_print; 1887 #else 1888 #define ahd_stack_print(regvalue, cur_col, wrap) \ 1889 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap) 1890 #endif 1891 1892 #if AIC_DEBUG_REGISTERS 1893 ahd_reg_print_t ahd_intvec1_addr_print; 1894 #else 1895 #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 1896 ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap) 1897 #endif 1898 1899 #if AIC_DEBUG_REGISTERS 1900 ahd_reg_print_t ahd_curaddr_print; 1901 #else 1902 #define ahd_curaddr_print(regvalue, cur_col, wrap) \ 1903 ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap) 1904 #endif 1905 1906 #if AIC_DEBUG_REGISTERS 1907 ahd_reg_print_t ahd_intvec2_addr_print; 1908 #else 1909 #define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1910 ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap) 1911 #endif 1912 1913 #if AIC_DEBUG_REGISTERS 1914 ahd_reg_print_t ahd_lastaddr_print; 1915 #else 1916 #define ahd_lastaddr_print(regvalue, cur_col, wrap) \ 1917 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap) 1918 #endif 1919 1920 #if AIC_DEBUG_REGISTERS 1921 ahd_reg_print_t ahd_longjmp_addr_print; 1922 #else 1923 #define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \ 1924 ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap) 1925 #endif 1926 1927 #if AIC_DEBUG_REGISTERS 1928 ahd_reg_print_t ahd_accum_save_print; 1929 #else 1930 #define ahd_accum_save_print(regvalue, cur_col, wrap) \ 1931 ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap) 1932 #endif 1933 1934 #if AIC_DEBUG_REGISTERS 1935 ahd_reg_print_t ahd_sram_base_print; 1936 #else 1937 #define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1938 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1939 #endif 1940 1941 #if AIC_DEBUG_REGISTERS 1942 ahd_reg_print_t ahd_waiting_scb_tails_print; 1943 #else 1944 #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 1945 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 1946 #endif 1947 1948 #if AIC_DEBUG_REGISTERS 1949 ahd_reg_print_t ahd_ahd_pci_config_base_print; 1950 #else 1951 #define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \ 1952 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap) 1953 #endif 1954 1955 #if AIC_DEBUG_REGISTERS 1956 ahd_reg_print_t ahd_waiting_tid_head_print; 1957 #else 1958 #define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \ 1959 ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap) 1960 #endif 1961 1962 #if AIC_DEBUG_REGISTERS 1963 ahd_reg_print_t ahd_waiting_tid_tail_print; 1964 #else 1965 #define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \ 1966 ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap) 1967 #endif 1968 1969 #if AIC_DEBUG_REGISTERS 1970 ahd_reg_print_t ahd_next_queued_scb_addr_print; 1971 #else 1972 #define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \ 1973 ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap) 1974 #endif 1975 1976 #if AIC_DEBUG_REGISTERS 1977 ahd_reg_print_t ahd_complete_scb_head_print; 1978 #else 1979 #define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \ 1980 ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap) 1981 #endif 1982 1983 #if AIC_DEBUG_REGISTERS 1984 ahd_reg_print_t ahd_complete_scb_dmainprog_head_print; 1985 #else 1986 #define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \ 1987 ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap) 1988 #endif 1989 1990 #if AIC_DEBUG_REGISTERS 1991 ahd_reg_print_t ahd_complete_dma_scb_head_print; 1992 #else 1993 #define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \ 1994 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap) 1995 #endif 1996 1997 #if AIC_DEBUG_REGISTERS 1998 ahd_reg_print_t ahd_complete_dma_scb_tail_print; 1999 #else 2000 #define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \ 2001 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap) 2002 #endif 2003 2004 #if AIC_DEBUG_REGISTERS 2005 ahd_reg_print_t ahd_complete_on_qfreeze_head_print; 2006 #else 2007 #define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \ 2008 ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap) 2009 #endif 2010 2011 #if AIC_DEBUG_REGISTERS 2012 ahd_reg_print_t ahd_qfreeze_count_print; 2013 #else 2014 #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \ 2015 ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap) 2016 #endif 2017 2018 #if AIC_DEBUG_REGISTERS 2019 ahd_reg_print_t ahd_kernel_qfreeze_count_print; 2020 #else 2021 #define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \ 2022 ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap) 2023 #endif 2024 2025 #if AIC_DEBUG_REGISTERS 2026 ahd_reg_print_t ahd_saved_mode_print; 2027 #else 2028 #define ahd_saved_mode_print(regvalue, cur_col, wrap) \ 2029 ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap) 2030 #endif 2031 2032 #if AIC_DEBUG_REGISTERS 2033 ahd_reg_print_t ahd_msg_out_print; 2034 #else 2035 #define ahd_msg_out_print(regvalue, cur_col, wrap) \ 2036 ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap) 2037 #endif 2038 2039 #if AIC_DEBUG_REGISTERS 2040 ahd_reg_print_t ahd_dmaparams_print; 2041 #else 2042 #define ahd_dmaparams_print(regvalue, cur_col, wrap) \ 2043 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap) 2044 #endif 2045 2046 #if AIC_DEBUG_REGISTERS 2047 ahd_reg_print_t ahd_seq_flags_print; 2048 #else 2049 #define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 2050 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap) 2051 #endif 2052 2053 #if AIC_DEBUG_REGISTERS 2054 ahd_reg_print_t ahd_saved_scsiid_print; 2055 #else 2056 #define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \ 2057 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap) 2058 #endif 2059 2060 #if AIC_DEBUG_REGISTERS 2061 ahd_reg_print_t ahd_saved_lun_print; 2062 #else 2063 #define ahd_saved_lun_print(regvalue, cur_col, wrap) \ 2064 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap) 2065 #endif 2066 2067 #if AIC_DEBUG_REGISTERS 2068 ahd_reg_print_t ahd_lastphase_print; 2069 #else 2070 #define ahd_lastphase_print(regvalue, cur_col, wrap) \ 2071 ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap) 2072 #endif 2073 2074 #if AIC_DEBUG_REGISTERS 2075 ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print; 2076 #else 2077 #define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \ 2078 ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap) 2079 #endif 2080 2081 #if AIC_DEBUG_REGISTERS 2082 ahd_reg_print_t ahd_kernel_tqinpos_print; 2083 #else 2084 #define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 2085 ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap) 2086 #endif 2087 2088 #if AIC_DEBUG_REGISTERS 2089 ahd_reg_print_t ahd_tqinpos_print; 2090 #else 2091 #define ahd_tqinpos_print(regvalue, cur_col, wrap) \ 2092 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap) 2093 #endif 2094 2095 #if AIC_DEBUG_REGISTERS 2096 ahd_reg_print_t ahd_shared_data_addr_print; 2097 #else 2098 #define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \ 2099 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap) 2100 #endif 2101 2102 #if AIC_DEBUG_REGISTERS 2103 ahd_reg_print_t ahd_qoutfifo_next_addr_print; 2104 #else 2105 #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 2106 ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap) 2107 #endif 2108 2109 #if AIC_DEBUG_REGISTERS 2110 ahd_reg_print_t ahd_arg_1_print; 2111 #else 2112 #define ahd_arg_1_print(regvalue, cur_col, wrap) \ 2113 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap) 2114 #endif 2115 2116 #if AIC_DEBUG_REGISTERS 2117 ahd_reg_print_t ahd_arg_2_print; 2118 #else 2119 #define ahd_arg_2_print(regvalue, cur_col, wrap) \ 2120 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap) 2121 #endif 2122 2123 #if AIC_DEBUG_REGISTERS 2124 ahd_reg_print_t ahd_last_msg_print; 2125 #else 2126 #define ahd_last_msg_print(regvalue, cur_col, wrap) \ 2127 ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap) 2128 #endif 2129 2130 #if AIC_DEBUG_REGISTERS 2131 ahd_reg_print_t ahd_scsiseq_template_print; 2132 #else 2133 #define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \ 2134 ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap) 2135 #endif 2136 2137 #if AIC_DEBUG_REGISTERS 2138 ahd_reg_print_t ahd_initiator_tag_print; 2139 #else 2140 #define ahd_initiator_tag_print(regvalue, cur_col, wrap) \ 2141 ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap) 2142 #endif 2143 2144 #if AIC_DEBUG_REGISTERS 2145 ahd_reg_print_t ahd_seq_flags2_print; 2146 #else 2147 #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \ 2148 ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap) 2149 #endif 2150 2151 #if AIC_DEBUG_REGISTERS 2152 ahd_reg_print_t ahd_allocfifo_scbptr_print; 2153 #else 2154 #define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \ 2155 ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap) 2156 #endif 2157 2158 #if AIC_DEBUG_REGISTERS 2159 ahd_reg_print_t ahd_int_coalescing_timer_print; 2160 #else 2161 #define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \ 2162 ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap) 2163 #endif 2164 2165 #if AIC_DEBUG_REGISTERS 2166 ahd_reg_print_t ahd_int_coalescing_maxcmds_print; 2167 #else 2168 #define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \ 2169 ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap) 2170 #endif 2171 2172 #if AIC_DEBUG_REGISTERS 2173 ahd_reg_print_t ahd_int_coalescing_mincmds_print; 2174 #else 2175 #define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \ 2176 ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap) 2177 #endif 2178 2179 #if AIC_DEBUG_REGISTERS 2180 ahd_reg_print_t ahd_cmds_pending_print; 2181 #else 2182 #define ahd_cmds_pending_print(regvalue, cur_col, wrap) \ 2183 ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap) 2184 #endif 2185 2186 #if AIC_DEBUG_REGISTERS 2187 ahd_reg_print_t ahd_int_coalescing_cmdcount_print; 2188 #else 2189 #define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \ 2190 ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap) 2191 #endif 2192 2193 #if AIC_DEBUG_REGISTERS 2194 ahd_reg_print_t ahd_local_hs_mailbox_print; 2195 #else 2196 #define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \ 2197 ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap) 2198 #endif 2199 2200 #if AIC_DEBUG_REGISTERS 2201 ahd_reg_print_t ahd_cmdsize_table_print; 2202 #else 2203 #define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \ 2204 ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap) 2205 #endif 2206 2207 #if AIC_DEBUG_REGISTERS 2208 ahd_reg_print_t ahd_mk_message_scb_print; 2209 #else 2210 #define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \ 2211 ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap) 2212 #endif 2213 2214 #if AIC_DEBUG_REGISTERS 2215 ahd_reg_print_t ahd_mk_message_scsiid_print; 2216 #else 2217 #define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \ 2218 ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap) 2219 #endif 2220 2221 #if AIC_DEBUG_REGISTERS 2222 ahd_reg_print_t ahd_scb_base_print; 2223 #else 2224 #define ahd_scb_base_print(regvalue, cur_col, wrap) \ 2225 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 2226 #endif 2227 2228 #if AIC_DEBUG_REGISTERS 2229 ahd_reg_print_t ahd_scb_residual_datacnt_print; 2230 #else 2231 #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 2232 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 2233 #endif 2234 2235 #if AIC_DEBUG_REGISTERS 2236 ahd_reg_print_t ahd_scb_residual_sgptr_print; 2237 #else 2238 #define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 2239 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap) 2240 #endif 2241 2242 #if AIC_DEBUG_REGISTERS 2243 ahd_reg_print_t ahd_scb_scsi_status_print; 2244 #else 2245 #define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 2246 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 2247 #endif 2248 2249 #if AIC_DEBUG_REGISTERS 2250 ahd_reg_print_t ahd_scb_target_phases_print; 2251 #else 2252 #define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \ 2253 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap) 2254 #endif 2255 2256 #if AIC_DEBUG_REGISTERS 2257 ahd_reg_print_t ahd_scb_target_data_dir_print; 2258 #else 2259 #define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 2260 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap) 2261 #endif 2262 2263 #if AIC_DEBUG_REGISTERS 2264 ahd_reg_print_t ahd_scb_target_itag_print; 2265 #else 2266 #define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \ 2267 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap) 2268 #endif 2269 2270 #if AIC_DEBUG_REGISTERS 2271 ahd_reg_print_t ahd_scb_sense_busaddr_print; 2272 #else 2273 #define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 2274 ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap) 2275 #endif 2276 2277 #if AIC_DEBUG_REGISTERS 2278 ahd_reg_print_t ahd_scb_tag_print; 2279 #else 2280 #define ahd_scb_tag_print(regvalue, cur_col, wrap) \ 2281 ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap) 2282 #endif 2283 2284 #if AIC_DEBUG_REGISTERS 2285 ahd_reg_print_t ahd_scb_control_print; 2286 #else 2287 #define ahd_scb_control_print(regvalue, cur_col, wrap) \ 2288 ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap) 2289 #endif 2290 2291 #if AIC_DEBUG_REGISTERS 2292 ahd_reg_print_t ahd_scb_scsiid_print; 2293 #else 2294 #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \ 2295 ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap) 2296 #endif 2297 2298 #if AIC_DEBUG_REGISTERS 2299 ahd_reg_print_t ahd_scb_lun_print; 2300 #else 2301 #define ahd_scb_lun_print(regvalue, cur_col, wrap) \ 2302 ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap) 2303 #endif 2304 2305 #if AIC_DEBUG_REGISTERS 2306 ahd_reg_print_t ahd_scb_task_attribute_print; 2307 #else 2308 #define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \ 2309 ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap) 2310 #endif 2311 2312 #if AIC_DEBUG_REGISTERS 2313 ahd_reg_print_t ahd_scb_cdb_len_print; 2314 #else 2315 #define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \ 2316 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap) 2317 #endif 2318 2319 #if AIC_DEBUG_REGISTERS 2320 ahd_reg_print_t ahd_scb_task_management_print; 2321 #else 2322 #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 2323 ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap) 2324 #endif 2325 2326 #if AIC_DEBUG_REGISTERS 2327 ahd_reg_print_t ahd_scb_dataptr_print; 2328 #else 2329 #define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \ 2330 ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap) 2331 #endif 2332 2333 #if AIC_DEBUG_REGISTERS 2334 ahd_reg_print_t ahd_scb_datacnt_print; 2335 #else 2336 #define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \ 2337 ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap) 2338 #endif 2339 2340 #if AIC_DEBUG_REGISTERS 2341 ahd_reg_print_t ahd_scb_sgptr_print; 2342 #else 2343 #define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \ 2344 ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap) 2345 #endif 2346 2347 #if AIC_DEBUG_REGISTERS 2348 ahd_reg_print_t ahd_scb_busaddr_print; 2349 #else 2350 #define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \ 2351 ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap) 2352 #endif 2353 2354 #if AIC_DEBUG_REGISTERS 2355 ahd_reg_print_t ahd_scb_next_print; 2356 #else 2357 #define ahd_scb_next_print(regvalue, cur_col, wrap) \ 2358 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap) 2359 #endif 2360 2361 #if AIC_DEBUG_REGISTERS 2362 ahd_reg_print_t ahd_scb_next2_print; 2363 #else 2364 #define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 2365 ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap) 2366 #endif 2367 2368 #if AIC_DEBUG_REGISTERS 2369 ahd_reg_print_t ahd_scb_spare_print; 2370 #else 2371 #define ahd_scb_spare_print(regvalue, cur_col, wrap) \ 2372 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap) 2373 #endif 2374 2375 #if AIC_DEBUG_REGISTERS 2376 ahd_reg_print_t ahd_scb_disconnected_lists_print; 2377 #else 2378 #define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 2379 ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap) 2380 #endif 2381 2382 2383 #define MODE_PTR 0x00 2384 #define DST_MODE 0x70 2385 #define SRC_MODE 0x07 2386 2387 #define INTSTAT 0x01 2388 #define INT_PEND 0xff 2389 #define HWERRINT 0x80 2390 #define BRKADRINT 0x40 2391 #define SWTMINT 0x20 2392 #define PCIINT 0x10 2393 #define SCSIINT 0x08 2394 #define SEQINT 0x04 2395 #define CMDCMPLT 0x02 2396 #define SPLTINT 0x01 2397 2398 #define SEQINTCODE 0x02 2399 #define BAD_SCB_STATUS 0x1a 2400 #define SAW_HWERR 0x19 2401 #define TRACEPOINT3 0x18 2402 #define TRACEPOINT2 0x17 2403 #define TRACEPOINT1 0x16 2404 #define TRACEPOINT0 0x15 2405 #define TASKMGMT_CMD_CMPLT_OKAY 0x14 2406 #define TASKMGMT_FUNC_COMPLETE 0x13 2407 #define ENTERING_NONPACK 0x12 2408 #define CFG4OVERRUN 0x11 2409 #define STATUS_OVERRUN 0x10 2410 #define CFG4ISTAT_INTR 0x0f 2411 #define INVALID_SEQINT 0x0e 2412 #define ILLEGAL_PHASE 0x0d 2413 #define DUMP_CARD_STATE 0x0c 2414 #define MISSED_BUSFREE 0x0b 2415 #define MKMSG_FAILED 0x0a 2416 #define DATA_OVERRUN 0x09 2417 #define BAD_STATUS 0x08 2418 #define HOST_MSG_LOOP 0x07 2419 #define PDATA_REINIT 0x06 2420 #define IGN_WIDE_RES 0x05 2421 #define NO_MATCH 0x04 2422 #define PROTO_VIOLATION 0x03 2423 #define SEND_REJECT 0x02 2424 #define BAD_PHASE 0x01 2425 #define NO_SEQINT 0x00 2426 2427 #define CLRINT 0x03 2428 #define CLRHWERRINT 0x80 2429 #define CLRBRKADRINT 0x40 2430 #define CLRSWTMINT 0x20 2431 #define CLRPCIINT 0x10 2432 #define CLRSCSIINT 0x08 2433 #define CLRSEQINT 0x04 2434 #define CLRCMDINT 0x02 2435 #define CLRSPLTINT 0x01 2436 2437 #define ERROR 0x04 2438 #define CIOPARERR 0x80 2439 #define CIOACCESFAIL 0x40 2440 #define MPARERR 0x20 2441 #define DPARERR 0x10 2442 #define SQPARERR 0x08 2443 #define ILLOPCODE 0x04 2444 #define DSCTMOUT 0x02 2445 2446 #define CLRERR 0x04 2447 #define CLRCIOPARERR 0x80 2448 #define CLRCIOACCESFAIL 0x40 2449 #define CLRMPARERR 0x20 2450 #define CLRDPARERR 0x10 2451 #define CLRSQPARERR 0x08 2452 #define CLRILLOPCODE 0x04 2453 #define CLRDSCTMOUT 0x02 2454 2455 #define HCNTRL 0x05 2456 #define SEQ_RESET 0x80 2457 #define POWRDN 0x40 2458 #define SWINT 0x10 2459 #define SWTIMER_START_B 0x08 2460 #define PAUSE 0x04 2461 #define INTEN 0x02 2462 #define CHIPRST 0x01 2463 #define CHIPRSTACK 0x01 2464 2465 #define HNSCB_QOFF 0x06 2466 2467 #define HESCB_QOFF 0x08 2468 2469 #define HS_MAILBOX 0x0b 2470 #define HOST_TQINPOS 0x80 2471 #define ENINT_COALESCE 0x40 2472 2473 #define SEQINTSTAT 0x0c 2474 #define SEQ_SWTMRTO 0x10 2475 #define SEQ_SEQINT 0x08 2476 #define SEQ_SCSIINT 0x04 2477 #define SEQ_PCIINT 0x02 2478 #define SEQ_SPLTINT 0x01 2479 2480 #define CLRSEQINTSTAT 0x0c 2481 #define CLRSEQ_SWTMRTO 0x10 2482 #define CLRSEQ_SEQINT 0x08 2483 #define CLRSEQ_SCSIINT 0x04 2484 #define CLRSEQ_PCIINT 0x02 2485 #define CLRSEQ_SPLTINT 0x01 2486 2487 #define SWTIMER 0x0e 2488 2489 #define SNSCB_QOFF 0x10 2490 2491 #define SESCB_QOFF 0x12 2492 2493 #define SDSCB_QOFF 0x14 2494 2495 #define QOFF_CTLSTA 0x16 2496 #define EMPTY_SCB_AVAIL 0x80 2497 #define NEW_SCB_AVAIL 0x40 2498 #define SDSCB_ROLLOVR 0x20 2499 #define HS_MAILBOX_ACT 0x10 2500 #define SCB_QSIZE 0x0f 2501 #define SCB_QSIZE_16384 0x0c 2502 #define SCB_QSIZE_8192 0x0b 2503 #define SCB_QSIZE_4096 0x0a 2504 #define SCB_QSIZE_2048 0x09 2505 #define SCB_QSIZE_1024 0x08 2506 #define SCB_QSIZE_512 0x07 2507 #define SCB_QSIZE_256 0x06 2508 #define SCB_QSIZE_128 0x05 2509 #define SCB_QSIZE_64 0x04 2510 #define SCB_QSIZE_32 0x03 2511 #define SCB_QSIZE_16 0x02 2512 #define SCB_QSIZE_8 0x01 2513 #define SCB_QSIZE_4 0x00 2514 2515 #define INTCTL 0x18 2516 #define SWTMINTMASK 0x80 2517 #define SWTMINTEN 0x40 2518 #define SWTIMER_START 0x20 2519 #define AUTOCLRCMDINT 0x10 2520 #define PCIINTEN 0x08 2521 #define SCSIINTEN 0x04 2522 #define SEQINTEN 0x02 2523 #define SPLTINTEN 0x01 2524 2525 #define DFCNTRL 0x19 2526 #define SCSIENWRDIS 0x40 2527 #define SCSIENACK 0x20 2528 #define DIRECTIONACK 0x04 2529 #define FIFOFLUSHACK 0x02 2530 #define DIRECTIONEN 0x01 2531 2532 #define DSCOMMAND0 0x19 2533 #define CACHETHEN 0x80 2534 #define DPARCKEN 0x40 2535 #define MPARCKEN 0x20 2536 #define EXTREQLCK 0x10 2537 #define DISABLE_TWATE 0x02 2538 #define CIOPARCKEN 0x01 2539 2540 #define DFSTATUS 0x1a 2541 #define PRELOAD_AVAIL 0x80 2542 #define PKT_PRELOAD_AVAIL 0x40 2543 #define MREQPEND 0x10 2544 #define HDONE 0x08 2545 #define DFTHRESH 0x04 2546 #define FIFOFULL 0x02 2547 #define FIFOEMP 0x01 2548 2549 #define SG_CACHE_SHADOW 0x1b 2550 #define ODD_SEG 0x04 2551 #define LAST_SEG 0x02 2552 #define LAST_SEG_DONE 0x01 2553 2554 #define SG_CACHE_PRE 0x1b 2555 2556 #define ARBCTL 0x1b 2557 #define RESET_HARB 0x80 2558 #define RETRY_SWEN 0x08 2559 #define USE_TIME 0x07 2560 2561 #define LQIN 0x20 2562 2563 #define TYPEPTR 0x20 2564 2565 #define TAGPTR 0x21 2566 2567 #define LUNPTR 0x22 2568 2569 #define DATALENPTR 0x23 2570 2571 #define STATLENPTR 0x24 2572 2573 #define CMDLENPTR 0x25 2574 2575 #define ATTRPTR 0x26 2576 2577 #define FLAGPTR 0x27 2578 2579 #define CMDPTR 0x28 2580 2581 #define QNEXTPTR 0x29 2582 2583 #define IDPTR 0x2a 2584 2585 #define ABRTBYTEPTR 0x2b 2586 2587 #define ABRTBITPTR 0x2c 2588 2589 #define MAXCMDBYTES 0x2d 2590 2591 #define MAXCMD2RCV 0x2e 2592 2593 #define SHORTTHRESH 0x2f 2594 2595 #define LUNLEN 0x30 2596 #define TLUNLEN 0xf0 2597 #define ILUNLEN 0x0f 2598 2599 #define CDBLIMIT 0x31 2600 2601 #define MAXCMD 0x32 2602 2603 #define MAXCMDCNT 0x33 2604 2605 #define LQRSVD01 0x34 2606 2607 #define LQRSVD16 0x35 2608 2609 #define LQRSVD17 0x36 2610 2611 #define CMDRSVD0 0x37 2612 2613 #define LQCTL0 0x38 2614 #define LQITARGCLT 0xc0 2615 #define LQIINITGCLT 0x30 2616 #define LQ0TARGCLT 0x0c 2617 #define LQ0INITGCLT 0x03 2618 2619 #define LQCTL1 0x38 2620 #define PCI2PCI 0x04 2621 #define SINGLECMD 0x02 2622 #define ABORTPENDING 0x01 2623 2624 #define LQCTL2 0x39 2625 #define LQIRETRY 0x80 2626 #define LQICONTINUE 0x40 2627 #define LQITOIDLE 0x20 2628 #define LQIPAUSE 0x10 2629 #define LQORETRY 0x08 2630 #define LQOCONTINUE 0x04 2631 #define LQOTOIDLE 0x02 2632 #define LQOPAUSE 0x01 2633 2634 #define SCSBIST0 0x39 2635 #define GSBISTERR 0x40 2636 #define GSBISTDONE 0x20 2637 #define GSBISTRUN 0x10 2638 #define OSBISTERR 0x04 2639 #define OSBISTDONE 0x02 2640 #define OSBISTRUN 0x01 2641 2642 #define SCSISEQ0 0x3a 2643 #define TEMODEO 0x80 2644 #define ENSELO 0x40 2645 #define ENARBO 0x20 2646 #define FORCEBUSFREE 0x10 2647 #define SCSIRSTO 0x01 2648 2649 #define SCSBIST1 0x3a 2650 #define NTBISTERR 0x04 2651 #define NTBISTDONE 0x02 2652 #define NTBISTRUN 0x01 2653 2654 #define SCSISEQ1 0x3b 2655 2656 #define BUSINITID 0x3c 2657 2658 #define SXFRCTL0 0x3c 2659 #define DFON 0x80 2660 #define DFPEXP 0x40 2661 #define BIOSCANCELEN 0x10 2662 #define SPIOEN 0x08 2663 2664 #define DLCOUNT 0x3c 2665 2666 #define SXFRCTL1 0x3d 2667 #define BITBUCKET 0x80 2668 #define ENSACHK 0x40 2669 #define ENSPCHK 0x20 2670 #define STIMESEL 0x18 2671 #define ENSTIMER 0x04 2672 #define ACTNEGEN 0x02 2673 #define STPWEN 0x01 2674 2675 #define BUSTARGID 0x3e 2676 2677 #define SXFRCTL2 0x3e 2678 #define AUTORSTDIS 0x10 2679 #define CMDDMAEN 0x08 2680 #define ASU 0x07 2681 2682 #define DFFSTAT 0x3f 2683 #define CURRFIFO 0x03 2684 #define FIFO1FREE 0x20 2685 #define FIFO0FREE 0x10 2686 #define CURRFIFO_NONE 0x03 2687 #define CURRFIFO_1 0x01 2688 #define CURRFIFO_0 0x00 2689 2690 #define SCSISIGO 0x40 2691 #define CDO 0x80 2692 #define IOO 0x40 2693 #define MSGO 0x20 2694 #define ATNO 0x10 2695 #define SELO 0x08 2696 #define BSYO 0x04 2697 #define REQO 0x02 2698 #define ACKO 0x01 2699 2700 #define MULTARGID 0x40 2701 2702 #define SCSISIGI 0x41 2703 #define ATNI 0x10 2704 #define SELI 0x08 2705 #define BSYI 0x04 2706 #define REQI 0x02 2707 #define ACKI 0x01 2708 2709 #define SCSIPHASE 0x42 2710 #define STATUS_PHASE 0x20 2711 #define COMMAND_PHASE 0x10 2712 #define MSG_IN_PHASE 0x08 2713 #define MSG_OUT_PHASE 0x04 2714 #define DATA_PHASE_MASK 0x03 2715 #define DATA_IN_PHASE 0x02 2716 #define DATA_OUT_PHASE 0x01 2717 2718 #define SCSIDAT0_IMG 0x43 2719 2720 #define SCSIDAT 0x44 2721 2722 #define SCSIBUS 0x46 2723 2724 #define TARGIDIN 0x48 2725 #define CLKOUT 0x80 2726 #define TARGID 0x0f 2727 2728 #define SELID 0x49 2729 #define SELID_MASK 0xf0 2730 #define ONEBIT 0x08 2731 2732 #define OPTIONMODE 0x4a 2733 #define OPTIONMODE_DEFAULTS 0x02 2734 #define BIOSCANCTL 0x80 2735 #define AUTOACKEN 0x40 2736 #define BIASCANCTL 0x20 2737 #define BUSFREEREV 0x10 2738 #define ENDGFORMCHK 0x04 2739 #define AUTO_MSGOUT_DE 0x02 2740 2741 #define SBLKCTL 0x4a 2742 #define DIAGLEDEN 0x80 2743 #define DIAGLEDON 0x40 2744 #define ENAB40 0x08 2745 #define ENAB20 0x04 2746 #define SELWIDE 0x02 2747 2748 #define SIMODE0 0x4b 2749 #define ENSELDO 0x40 2750 #define ENSELDI 0x20 2751 #define ENSELINGO 0x10 2752 #define ENIOERR 0x08 2753 #define ENOVERRUN 0x04 2754 #define ENSPIORDY 0x02 2755 #define ENARBDO 0x01 2756 2757 #define SSTAT0 0x4b 2758 #define TARGET 0x80 2759 #define SELDO 0x40 2760 #define SELDI 0x20 2761 #define SELINGO 0x10 2762 #define IOERR 0x08 2763 #define OVERRUN 0x04 2764 #define SPIORDY 0x02 2765 #define ARBDO 0x01 2766 2767 #define CLRSINT0 0x4b 2768 #define CLRSELDO 0x40 2769 #define CLRSELDI 0x20 2770 #define CLRSELINGO 0x10 2771 #define CLRIOERR 0x08 2772 #define CLROVERRUN 0x04 2773 #define CLRSPIORDY 0x02 2774 #define CLRARBDO 0x01 2775 2776 #define SSTAT1 0x4c 2777 #define SELTO 0x80 2778 #define ATNTARG 0x40 2779 #define SCSIRSTI 0x20 2780 #define PHASEMIS 0x10 2781 #define BUSFREE 0x08 2782 #define SCSIPERR 0x04 2783 #define STRB2FAST 0x02 2784 #define REQINIT 0x01 2785 2786 #define CLRSINT1 0x4c 2787 #define CLRSELTIMEO 0x80 2788 #define CLRATNO 0x40 2789 #define CLRSCSIRSTI 0x20 2790 #define CLRBUSFREE 0x08 2791 #define CLRSCSIPERR 0x04 2792 #define CLRSTRB2FAST 0x02 2793 #define CLRREQINIT 0x01 2794 2795 #define SSTAT2 0x4d 2796 #define BUSFREETIME 0xc0 2797 #define NONPACKREQ 0x20 2798 #define EXP_ACTIVE 0x10 2799 #define BSYX 0x08 2800 #define WIDE_RES 0x04 2801 #define SDONE 0x02 2802 #define DMADONE 0x01 2803 #define BUSFREE_DFF1 0xc0 2804 #define BUSFREE_DFF0 0x80 2805 #define BUSFREE_LQO 0x40 2806 2807 #define CLRSINT2 0x4d 2808 #define CLRNONPACKREQ 0x20 2809 #define CLRWIDE_RES 0x04 2810 #define CLRSDONE 0x02 2811 #define CLRDMADONE 0x01 2812 2813 #define SIMODE2 0x4d 2814 #define ENWIDE_RES 0x04 2815 #define ENSDONE 0x02 2816 #define ENDMADONE 0x01 2817 2818 #define PERRDIAG 0x4e 2819 #define HIZERO 0x80 2820 #define HIPERR 0x40 2821 #define PREVPHASE 0x20 2822 #define PARITYERR 0x10 2823 #define AIPERR 0x08 2824 #define CRCERR 0x04 2825 #define DGFORMERR 0x02 2826 #define DTERR 0x01 2827 2828 #define LQISTATE 0x4e 2829 2830 #define SOFFCNT 0x4f 2831 2832 #define LQOSTATE 0x4f 2833 2834 #define LQISTAT0 0x50 2835 #define LQIATNQAS 0x20 2836 #define LQICRCT1 0x10 2837 #define LQICRCT2 0x08 2838 #define LQIBADLQT 0x04 2839 #define LQIATNLQ 0x02 2840 #define LQIATNCMD 0x01 2841 2842 #define CLRLQIINT0 0x50 2843 #define CLRLQIATNQAS 0x20 2844 #define CLRLQICRCT1 0x10 2845 #define CLRLQICRCT2 0x08 2846 #define CLRLQIBADLQT 0x04 2847 #define CLRLQIATNLQ 0x02 2848 #define CLRLQIATNCMD 0x01 2849 2850 #define LQIMODE0 0x50 2851 #define ENLQIATNQASK 0x20 2852 #define ENLQICRCT1 0x10 2853 #define ENLQICRCT2 0x08 2854 #define ENLQIBADLQT 0x04 2855 #define ENLQIATNLQ 0x02 2856 #define ENLQIATNCMD 0x01 2857 2858 #define LQISTAT1 0x51 2859 #define LQIPHASE_LQ 0x80 2860 #define LQIPHASE_NLQ 0x40 2861 #define LQIABORT 0x20 2862 #define LQICRCI_LQ 0x10 2863 #define LQICRCI_NLQ 0x08 2864 #define LQIBADLQI 0x04 2865 #define LQIOVERI_LQ 0x02 2866 #define LQIOVERI_NLQ 0x01 2867 2868 #define CLRLQIINT1 0x51 2869 #define CLRLQIPHASE_LQ 0x80 2870 #define CLRLQIPHASE_NLQ 0x40 2871 #define CLRLIQABORT 0x20 2872 #define CLRLQICRCI_LQ 0x10 2873 #define CLRLQICRCI_NLQ 0x08 2874 #define CLRLQIBADLQI 0x04 2875 #define CLRLQIOVERI_LQ 0x02 2876 #define CLRLQIOVERI_NLQ 0x01 2877 2878 #define LQIMODE1 0x51 2879 #define ENLQIPHASE_LQ 0x80 2880 #define ENLQIPHASE_NLQ 0x40 2881 #define ENLIQABORT 0x20 2882 #define ENLQICRCI_LQ 0x10 2883 #define ENLQICRCI_NLQ 0x08 2884 #define ENLQIBADLQI 0x04 2885 #define ENLQIOVERI_LQ 0x02 2886 #define ENLQIOVERI_NLQ 0x01 2887 2888 #define LQISTAT2 0x52 2889 #define PACKETIZED 0x80 2890 #define LQIPHASE_OUTPKT 0x40 2891 #define LQIWORKONLQ 0x20 2892 #define LQIWAITFIFO 0x10 2893 #define LQISTOPPKT 0x08 2894 #define LQISTOPLQ 0x04 2895 #define LQISTOPCMD 0x02 2896 #define LQIGSAVAIL 0x01 2897 2898 #define SSTAT3 0x53 2899 #define NTRAMPERR 0x02 2900 #define OSRAMPERR 0x01 2901 2902 #define CLRSINT3 0x53 2903 #define CLRNTRAMPERR 0x02 2904 #define CLROSRAMPERR 0x01 2905 2906 #define SIMODE3 0x53 2907 #define ENNTRAMPERR 0x02 2908 #define ENOSRAMPERR 0x01 2909 2910 #define LQOMODE0 0x54 2911 #define ENLQOTARGSCBPERR 0x10 2912 #define ENLQOSTOPT2 0x08 2913 #define ENLQOATNLQ 0x04 2914 #define ENLQOATNPKT 0x02 2915 #define ENLQOTCRC 0x01 2916 2917 #define LQOSTAT0 0x54 2918 #define LQOTARGSCBPERR 0x10 2919 #define LQOSTOPT2 0x08 2920 #define LQOATNLQ 0x04 2921 #define LQOATNPKT 0x02 2922 #define LQOTCRC 0x01 2923 2924 #define CLRLQOINT0 0x54 2925 #define CLRLQOTARGSCBPERR 0x10 2926 #define CLRLQOSTOPT2 0x08 2927 #define CLRLQOATNLQ 0x04 2928 #define CLRLQOATNPKT 0x02 2929 #define CLRLQOTCRC 0x01 2930 2931 #define LQOMODE1 0x55 2932 #define ENLQOINITSCBPERR 0x10 2933 #define ENLQOSTOPI2 0x08 2934 #define ENLQOBADQAS 0x04 2935 #define ENLQOBUSFREE 0x02 2936 #define ENLQOPHACHGINPKT 0x01 2937 2938 #define LQOSTAT1 0x55 2939 #define LQOINITSCBPERR 0x10 2940 #define LQOSTOPI2 0x08 2941 #define LQOBADQAS 0x04 2942 #define LQOBUSFREE 0x02 2943 #define LQOPHACHGINPKT 0x01 2944 2945 #define CLRLQOINT1 0x55 2946 #define CLRLQOINITSCBPERR 0x10 2947 #define CLRLQOSTOPI2 0x08 2948 #define CLRLQOBADQAS 0x04 2949 #define CLRLQOBUSFREE 0x02 2950 #define CLRLQOPHACHGINPKT 0x01 2951 2952 #define OS_SPACE_CNT 0x56 2953 2954 #define LQOSTAT2 0x56 2955 #define LQOPKT 0xe0 2956 #define LQOWAITFIFO 0x10 2957 #define LQOPHACHGOUTPKT 0x02 2958 #define LQOSTOP0 0x01 2959 2960 #define SIMODE1 0x57 2961 #define ENSELTIMO 0x80 2962 #define ENATNTARG 0x40 2963 #define ENSCSIRST 0x20 2964 #define ENPHASEMIS 0x10 2965 #define ENBUSFREE 0x08 2966 #define ENSCSIPERR 0x04 2967 #define ENSTRB2FAST 0x02 2968 #define ENREQINIT 0x01 2969 2970 #define GSFIFO 0x58 2971 2972 #define DFFSXFRCTL 0x5a 2973 #define DFFBITBUCKET 0x08 2974 #define CLRSHCNT 0x04 2975 #define CLRCHN 0x02 2976 #define RSTCHN 0x01 2977 2978 #define NEXTSCB 0x5a 2979 2980 #define LQOSCSCTL 0x5a 2981 #define LQOH2A_VERSION 0x80 2982 #define LQONOCHKOVER 0x01 2983 2984 #define SEQINTSRC 0x5b 2985 #define CTXTDONE 0x40 2986 #define SAVEPTRS 0x20 2987 #define CFG4DATA 0x10 2988 #define CFG4ISTAT 0x08 2989 #define CFG4TSTAT 0x04 2990 #define CFG4ICMD 0x02 2991 #define CFG4TCMD 0x01 2992 2993 #define CLRSEQINTSRC 0x5b 2994 #define CLRCTXTDONE 0x40 2995 #define CLRSAVEPTRS 0x20 2996 #define CLRCFG4DATA 0x10 2997 #define CLRCFG4ISTAT 0x08 2998 #define CLRCFG4TSTAT 0x04 2999 #define CLRCFG4ICMD 0x02 3000 #define CLRCFG4TCMD 0x01 3001 3002 #define CURRSCB 0x5c 3003 3004 #define SEQIMODE 0x5c 3005 #define ENCTXTDONE 0x40 3006 #define ENSAVEPTRS 0x20 3007 #define ENCFG4DATA 0x10 3008 #define ENCFG4ISTAT 0x08 3009 #define ENCFG4TSTAT 0x04 3010 #define ENCFG4ICMD 0x02 3011 #define ENCFG4TCMD 0x01 3012 3013 #define MDFFSTAT 0x5d 3014 #define SHCNTNEGATIVE 0x40 3015 #define SHCNTMINUS1 0x20 3016 #define LASTSDONE 0x10 3017 #define SHVALID 0x08 3018 #define DLZERO 0x04 3019 #define DATAINFIFO 0x02 3020 #define FIFOFREE 0x01 3021 3022 #define CRCCONTROL 0x5d 3023 #define CRCVALCHKEN 0x40 3024 3025 #define SCSITEST 0x5e 3026 #define CNTRTEST 0x08 3027 #define SEL_TXPLL_DEBUG 0x04 3028 3029 #define DFFTAG 0x5e 3030 3031 #define LASTSCB 0x5e 3032 3033 #define IOPDNCTL 0x5f 3034 #define DISABLE_OE 0x80 3035 #define PDN_IDIST 0x04 3036 #define PDN_DIFFSENSE 0x01 3037 3038 #define NEGOADDR 0x60 3039 3040 #define SHADDR 0x60 3041 3042 #define DGRPCRCI 0x60 3043 3044 #define NEGPERIOD 0x61 3045 3046 #define PACKCRCI 0x62 3047 3048 #define NEGOFFSET 0x62 3049 3050 #define NEGPPROPTS 0x63 3051 #define PPROPT_PACE 0x08 3052 #define PPROPT_QAS 0x04 3053 #define PPROPT_DT 0x02 3054 #define PPROPT_IUT 0x01 3055 3056 #define NEGCONOPTS 0x64 3057 #define ENSNAPSHOT 0x40 3058 #define RTI_WRTDIS 0x20 3059 #define RTI_OVRDTRN 0x10 3060 #define ENSLOWCRC 0x08 3061 #define ENAUTOATNI 0x04 3062 #define ENAUTOATNO 0x02 3063 #define WIDEXFER 0x01 3064 3065 #define ANNEXCOL 0x65 3066 3067 #define ANNEXDAT 0x66 3068 3069 #define SCSCHKN 0x66 3070 #define STSELSKIDDIS 0x40 3071 #define CURRFIFODEF 0x20 3072 #define WIDERESEN 0x10 3073 #define SDONEMSKDIS 0x08 3074 #define DFFACTCLR 0x04 3075 #define SHVALIDSTDIS 0x02 3076 #define LSTSGCLRDIS 0x01 3077 3078 #define IOWNID 0x67 3079 3080 #define SHCNT 0x68 3081 3082 #define PLL960CTL0 0x68 3083 3084 #define PLL960CTL1 0x69 3085 3086 #define TOWNID 0x69 3087 3088 #define XSIG 0x6a 3089 3090 #define PLL960CNT0 0x6a 3091 3092 #define SELOID 0x6b 3093 3094 #define FAIRNESS 0x6c 3095 3096 #define PLL400CTL0 0x6c 3097 #define PLL_VCOSEL 0x80 3098 #define PLL_PWDN 0x40 3099 #define PLL_NS 0x30 3100 #define PLL_ENLUD 0x08 3101 #define PLL_ENLPF 0x04 3102 #define PLL_DLPF 0x02 3103 #define PLL_ENFBM 0x01 3104 3105 #define PLL400CTL1 0x6d 3106 #define PLL_CNTEN 0x80 3107 #define PLL_CNTCLR 0x40 3108 #define PLL_RST 0x01 3109 3110 #define PLL400CNT0 0x6e 3111 3112 #define UNFAIRNESS 0x6e 3113 3114 #define HODMAADR 0x70 3115 3116 #define HADDR 0x70 3117 3118 #define PLLDELAY 0x70 3119 #define SPLIT_DROP_REQ 0x80 3120 3121 #define HCNT 0x78 3122 3123 #define HODMACNT 0x78 3124 3125 #define HODMAEN 0x7a 3126 3127 #define SCBHADDR 0x7c 3128 3129 #define SGHADDR 0x7c 3130 3131 #define SCBHCNT 0x84 3132 3133 #define SGHCNT 0x84 3134 3135 #define DFF_THRSH 0x88 3136 #define WR_DFTHRSH 0x70 3137 #define RD_DFTHRSH 0x07 3138 #define WR_DFTHRSH_MAX 0x70 3139 #define WR_DFTHRSH_90 0x60 3140 #define WR_DFTHRSH_85 0x50 3141 #define WR_DFTHRSH_75 0x40 3142 #define WR_DFTHRSH_63 0x30 3143 #define WR_DFTHRSH_50 0x20 3144 #define WR_DFTHRSH_25 0x10 3145 #define RD_DFTHRSH_MAX 0x07 3146 #define RD_DFTHRSH_90 0x06 3147 #define RD_DFTHRSH_85 0x05 3148 #define RD_DFTHRSH_75 0x04 3149 #define RD_DFTHRSH_63 0x03 3150 #define RD_DFTHRSH_50 0x02 3151 #define RD_DFTHRSH_25 0x01 3152 #define WR_DFTHRSH_MIN 0x00 3153 #define RD_DFTHRSH_MIN 0x00 3154 3155 #define ROMADDR 0x8a 3156 3157 #define ROMCNTRL 0x8d 3158 #define ROMOP 0xe0 3159 #define ROMSPD 0x18 3160 #define REPEAT 0x02 3161 #define RDY 0x01 3162 3163 #define ROMDATA 0x8e 3164 3165 #define DCHRXMSG0 0x90 3166 3167 #define OVLYRXMSG0 0x90 3168 3169 #define CMCRXMSG0 0x90 3170 3171 #define ROENABLE 0x90 3172 #define MSIROEN 0x20 3173 #define OVLYROEN 0x10 3174 #define CMCROEN 0x08 3175 #define SGROEN 0x04 3176 #define DCH1ROEN 0x02 3177 #define DCH0ROEN 0x01 3178 3179 #define DCHRXMSG1 0x91 3180 3181 #define OVLYRXMSG1 0x91 3182 3183 #define CMCRXMSG1 0x91 3184 3185 #define NSENABLE 0x91 3186 #define MSINSEN 0x20 3187 #define OVLYNSEN 0x10 3188 #define CMCNSEN 0x08 3189 #define SGNSEN 0x04 3190 #define DCH1NSEN 0x02 3191 #define DCH0NSEN 0x01 3192 3193 #define DCHRXMSG2 0x92 3194 3195 #define OVLYRXMSG2 0x92 3196 3197 #define CMCRXMSG2 0x92 3198 3199 #define OST 0x92 3200 3201 #define DCHRXMSG3 0x93 3202 3203 #define OVLYRXMSG3 0x93 3204 3205 #define CMCRXMSG3 0x93 3206 3207 #define PCIXCTL 0x93 3208 #define SERRPULSE 0x80 3209 #define UNEXPSCIEN 0x20 3210 #define SPLTSMADIS 0x10 3211 #define SPLTSTADIS 0x08 3212 #define SRSPDPEEN 0x04 3213 #define TSCSERREN 0x02 3214 #define CMPABCDIS 0x01 3215 3216 #define OVLYSEQBCNT 0x94 3217 3218 #define CMCSEQBCNT 0x94 3219 3220 #define DCHSEQBCNT 0x94 3221 3222 #define CMCSPLTSTAT0 0x96 3223 3224 #define DCHSPLTSTAT0 0x96 3225 3226 #define OVLYSPLTSTAT0 0x96 3227 3228 #define OVLYSPLTSTAT1 0x97 3229 3230 #define CMCSPLTSTAT1 0x97 3231 3232 #define DCHSPLTSTAT1 0x97 3233 3234 #define SGRXMSG0 0x98 3235 #define CDNUM 0xf8 3236 #define CFNUM 0x07 3237 3238 #define SLVSPLTOUTADR0 0x98 3239 #define LOWER_ADDR 0x7f 3240 3241 #define SGRXMSG1 0x99 3242 #define CBNUM 0xff 3243 3244 #define SLVSPLTOUTADR1 0x99 3245 #define REQ_DNUM 0xf8 3246 #define REQ_FNUM 0x07 3247 3248 #define SGRXMSG2 0x9a 3249 #define MINDEX 0xff 3250 3251 #define SLVSPLTOUTADR2 0x9a 3252 #define REQ_BNUM 0xff 3253 3254 #define SLVSPLTOUTADR3 0x9b 3255 #define TAG_NUM 0x1f 3256 #define RLXORD 0x10 3257 3258 #define SGRXMSG3 0x9b 3259 #define MCLASS 0x0f 3260 3261 #define SGSEQBCNT 0x9c 3262 3263 #define SLVSPLTOUTATTR0 0x9c 3264 #define LOWER_BCNT 0xff 3265 3266 #define SLVSPLTOUTATTR1 0x9d 3267 #define CMPLT_DNUM 0xf8 3268 #define CMPLT_FNUM 0x07 3269 3270 #define SLVSPLTOUTATTR2 0x9e 3271 #define CMPLT_BNUM 0xff 3272 3273 #define SGSPLTSTAT0 0x9e 3274 #define STAETERM 0x80 3275 #define SCBCERR 0x40 3276 #define SCADERR 0x20 3277 #define SCDATBUCKET 0x10 3278 #define CNTNOTCMPLT 0x08 3279 #define RXOVRUN 0x04 3280 #define RXSCEMSG 0x02 3281 #define RXSPLTRSP 0x01 3282 3283 #define SGSPLTSTAT1 0x9f 3284 #define RXDATABUCKET 0x01 3285 3286 #define SFUNCT 0x9f 3287 #define TEST_GROUP 0xf0 3288 #define TEST_NUM 0x0f 3289 3290 #define DF0PCISTAT 0xa0 3291 3292 #define REG0 0xa0 3293 3294 #define DF1PCISTAT 0xa1 3295 3296 #define SGPCISTAT 0xa2 3297 3298 #define REG1 0xa2 3299 3300 #define CMCPCISTAT 0xa3 3301 3302 #define OVLYPCISTAT 0xa4 3303 #define SCAAPERR 0x08 3304 #define RDPERR 0x04 3305 3306 #define REG_ISR 0xa4 3307 3308 #define MSIPCISTAT 0xa6 3309 #define RMA 0x20 3310 #define RTA 0x10 3311 #define CLRPENDMSI 0x08 3312 #define DPR 0x01 3313 3314 #define SG_STATE 0xa6 3315 #define FETCH_INPROG 0x04 3316 #define LOADING_NEEDED 0x02 3317 #define SEGS_AVAIL 0x01 3318 3319 #define TARGPCISTAT 0xa7 3320 #define DPE 0x80 3321 #define SSE 0x40 3322 #define STA 0x08 3323 #define TWATERR 0x02 3324 3325 #define DATA_COUNT_ODD 0xa7 3326 3327 #define SCBPTR 0xa8 3328 3329 #define CCSCBACNT 0xab 3330 3331 #define SCBAUTOPTR 0xab 3332 #define AUSCBPTR_EN 0x80 3333 #define SCBPTR_ADDR 0x38 3334 #define SCBPTR_OFF 0x07 3335 3336 #define CCSCBADR_BK 0xac 3337 3338 #define CCSGADDR 0xac 3339 3340 #define CCSCBADDR 0xac 3341 3342 #define CCSCBCTL 0xad 3343 #define CCSCBDONE 0x80 3344 #define ARRDONE 0x40 3345 #define CCARREN 0x10 3346 #define CCSCBEN 0x08 3347 #define CCSCBDIR 0x04 3348 #define CCSCBRESET 0x01 3349 3350 #define CCSGCTL 0xad 3351 #define CCSGEN 0x0c 3352 #define CCSGDONE 0x80 3353 #define SG_CACHE_AVAIL 0x10 3354 #define CCSGENACK 0x08 3355 #define SG_FETCH_REQ 0x02 3356 #define CCSGRESET 0x01 3357 3358 #define CMC_RAMBIST 0xad 3359 #define SG_ELEMENT_SIZE 0x80 3360 #define SCBRAMBIST_FAIL 0x40 3361 #define SG_BIST_FAIL 0x20 3362 #define SG_BIST_EN 0x10 3363 #define CMC_BUFFER_BIST_FAIL 0x02 3364 #define CMC_BUFFER_BIST_EN 0x01 3365 3366 #define CCSGRAM 0xb0 3367 3368 #define CCSCBRAM 0xb0 3369 3370 #define FLEXADR 0xb0 3371 3372 #define FLEXCNT 0xb3 3373 3374 #define FLEXDMASTAT 0xb5 3375 #define FLEXDMAERR 0x02 3376 #define FLEXDMADONE 0x01 3377 3378 #define FLEXDATA 0xb6 3379 3380 #define BRDDAT 0xb8 3381 3382 #define BRDCTL 0xb9 3383 #define FLXARBACK 0x80 3384 #define FLXARBREQ 0x40 3385 #define BRDADDR 0x38 3386 #define BRDEN 0x04 3387 #define BRDRW 0x02 3388 #define BRDSTB 0x01 3389 3390 #define SEEADR 0xba 3391 3392 #define SEEDAT 0xbc 3393 3394 #define SEECTL 0xbe 3395 #define SEEOP_EWDS 0x40 3396 #define SEEOP_WALL 0x40 3397 #define SEEOP_EWEN 0x40 3398 #define SEEOPCODE 0x70 3399 #define SEERST 0x02 3400 #define SEESTART 0x01 3401 #define SEEOP_ERASE 0x70 3402 #define SEEOP_READ 0x60 3403 #define SEEOP_WRITE 0x50 3404 #define SEEOP_ERAL 0x40 3405 3406 #define SEESTAT 0xbe 3407 #define INIT_DONE 0x80 3408 #define LDALTID_L 0x08 3409 #define SEEARBACK 0x04 3410 #define SEEBUSY 0x02 3411 3412 #define SCBCNT 0xbf 3413 3414 #define DSPFLTRCTL 0xc0 3415 #define FLTRDISABLE 0x20 3416 #define EDGESENSE 0x10 3417 #define DSPFCNTSEL 0x0f 3418 3419 #define DFWADDR 0xc0 3420 3421 #define DSPDATACTL 0xc1 3422 #define BYPASSENAB 0x80 3423 #define DESQDIS 0x10 3424 #define RCVROFFSTDIS 0x04 3425 #define XMITOFFSTDIS 0x02 3426 3427 #define DSPREQCTL 0xc2 3428 #define MANREQCTL 0xc0 3429 #define MANREQDLY 0x3f 3430 3431 #define DFRADDR 0xc2 3432 3433 #define DSPACKCTL 0xc3 3434 #define MANACKCTL 0xc0 3435 #define MANACKDLY 0x3f 3436 3437 #define DFDAT 0xc4 3438 3439 #define DSPSELECT 0xc4 3440 #define AUTOINCEN 0x80 3441 #define DSPSEL 0x1f 3442 3443 #define WRTBIASCTL 0xc5 3444 #define AUTOXBCDIS 0x80 3445 #define XMITMANVAL 0x3f 3446 3447 #define RCVRBIOSCTL 0xc6 3448 #define AUTORBCDIS 0x80 3449 #define RCVRMANVAL 0x3f 3450 3451 #define WRTBIASCALC 0xc7 3452 3453 #define DFPTRS 0xc8 3454 3455 #define RCVRBIASCALC 0xc8 3456 3457 #define DFBKPTR 0xc9 3458 3459 #define SKEWCALC 0xc9 3460 3461 #define DFDBCTL 0xcb 3462 #define DFF_CIO_WR_RDY 0x20 3463 #define DFF_CIO_RD_RDY 0x10 3464 #define DFF_DIR_ERR 0x08 3465 #define DFF_RAMBIST_FAIL 0x04 3466 #define DFF_RAMBIST_DONE 0x02 3467 #define DFF_RAMBIST_EN 0x01 3468 3469 #define DFSCNT 0xcc 3470 3471 #define DFBCNT 0xce 3472 3473 #define OVLYADDR 0xd4 3474 3475 #define SEQCTL0 0xd6 3476 #define PERRORDIS 0x80 3477 #define PAUSEDIS 0x40 3478 #define FAILDIS 0x20 3479 #define FASTMODE 0x10 3480 #define BRKADRINTEN 0x08 3481 #define STEP 0x04 3482 #define SEQRESET 0x02 3483 #define LOADRAM 0x01 3484 3485 #define SEQCTL1 0xd7 3486 #define OVRLAY_DATA_CHK 0x08 3487 #define RAMBIST_DONE 0x04 3488 #define RAMBIST_FAIL 0x02 3489 #define RAMBIST_EN 0x01 3490 3491 #define FLAGS 0xd8 3492 #define ZERO 0x02 3493 #define CARRY 0x01 3494 3495 #define SEQINTCTL 0xd9 3496 #define INTVEC1DSL 0x80 3497 #define INT1_CONTEXT 0x20 3498 #define SCS_SEQ_INT1M1 0x10 3499 #define SCS_SEQ_INT1M0 0x08 3500 #define INTMASK2 0x04 3501 #define INTMASK1 0x02 3502 #define IRET 0x01 3503 3504 #define SEQRAM 0xda 3505 3506 #define PRGMCNT 0xde 3507 3508 #define ACCUM 0xe0 3509 3510 #define SINDEX 0xe2 3511 3512 #define DINDEX 0xe4 3513 3514 #define BRKADDR0 0xe6 3515 3516 #define BRKADDR1 0xe6 3517 #define BRKDIS 0x80 3518 3519 #define ALLONES 0xe8 3520 3521 #define NONE 0xea 3522 3523 #define ALLZEROS 0xea 3524 3525 #define SINDIR 0xec 3526 3527 #define DINDIR 0xed 3528 3529 #define FUNCTION1 0xf0 3530 3531 #define STACK 0xf2 3532 3533 #define INTVEC1_ADDR 0xf4 3534 3535 #define CURADDR 0xf4 3536 3537 #define INTVEC2_ADDR 0xf6 3538 3539 #define LASTADDR 0xf6 3540 3541 #define LONGJMP_ADDR 0xf8 3542 3543 #define ACCUM_SAVE 0xfa 3544 3545 #define SRAM_BASE 0x100 3546 3547 #define WAITING_SCB_TAILS 0x100 3548 3549 #define AHD_PCI_CONFIG_BASE 0x100 3550 3551 #define WAITING_TID_HEAD 0x120 3552 3553 #define WAITING_TID_TAIL 0x122 3554 3555 #define NEXT_QUEUED_SCB_ADDR 0x124 3556 3557 #define COMPLETE_SCB_HEAD 0x128 3558 3559 #define COMPLETE_SCB_DMAINPROG_HEAD 0x12a 3560 3561 #define COMPLETE_DMA_SCB_HEAD 0x12c 3562 3563 #define COMPLETE_DMA_SCB_TAIL 0x12e 3564 3565 #define COMPLETE_ON_QFREEZE_HEAD 0x130 3566 3567 #define QFREEZE_COUNT 0x132 3568 3569 #define KERNEL_QFREEZE_COUNT 0x134 3570 3571 #define SAVED_MODE 0x136 3572 3573 #define MSG_OUT 0x137 3574 3575 #define DMAPARAMS 0x138 3576 #define PRELOADEN 0x80 3577 #define WIDEODD 0x40 3578 #define SCSIEN 0x20 3579 #define SDMAEN 0x10 3580 #define SDMAENACK 0x10 3581 #define HDMAEN 0x08 3582 #define HDMAENACK 0x08 3583 #define DIRECTION 0x04 3584 #define FIFOFLUSH 0x02 3585 #define FIFORESET 0x01 3586 3587 #define SEQ_FLAGS 0x139 3588 #define NOT_IDENTIFIED 0x80 3589 #define NO_CDB_SENT 0x40 3590 #define TARGET_CMD_IS_TAGGED 0x40 3591 #define DPHASE 0x20 3592 #define TARG_CMD_PENDING 0x10 3593 #define CMDPHASE_PENDING 0x08 3594 #define DPHASE_PENDING 0x04 3595 #define SPHASE_PENDING 0x02 3596 #define NO_DISCONNECT 0x01 3597 3598 #define SAVED_SCSIID 0x13a 3599 3600 #define SAVED_LUN 0x13b 3601 3602 #define LASTPHASE 0x13c 3603 #define PHASE_MASK 0xe0 3604 #define CDI 0x80 3605 #define IOI 0x40 3606 #define MSGI 0x20 3607 #define P_BUSFREE 0x01 3608 #define P_MESGIN 0xe0 3609 #define P_STATUS 0xc0 3610 #define P_MESGOUT 0xa0 3611 #define P_COMMAND 0x80 3612 #define P_DATAIN_DT 0x60 3613 #define P_DATAIN 0x40 3614 #define P_DATAOUT_DT 0x20 3615 #define P_DATAOUT 0x00 3616 3617 #define QOUTFIFO_ENTRY_VALID_TAG 0x13d 3618 3619 #define KERNEL_TQINPOS 0x13e 3620 3621 #define TQINPOS 0x13f 3622 3623 #define SHARED_DATA_ADDR 0x140 3624 3625 #define QOUTFIFO_NEXT_ADDR 0x144 3626 3627 #define ARG_1 0x148 3628 #define RETURN_1 0x148 3629 #define SEND_MSG 0x80 3630 #define SEND_SENSE 0x40 3631 #define SEND_REJ 0x20 3632 #define MSGOUT_PHASEMIS 0x10 3633 #define EXIT_MSG_LOOP 0x08 3634 #define CONT_MSG_LOOP_WRITE 0x04 3635 #define CONT_MSG_LOOP_READ 0x03 3636 #define CONT_MSG_LOOP_TARG 0x02 3637 3638 #define ARG_2 0x149 3639 #define RETURN_2 0x149 3640 3641 #define LAST_MSG 0x14a 3642 3643 #define SCSISEQ_TEMPLATE 0x14b 3644 #define MANUALCTL 0x40 3645 #define ENSELI 0x20 3646 #define ENRSELI 0x10 3647 #define MANUALP 0x0c 3648 #define ENAUTOATNP 0x02 3649 #define ALTSTIM 0x01 3650 3651 #define INITIATOR_TAG 0x14c 3652 3653 #define SEQ_FLAGS2 0x14d 3654 #define SELECTOUT_QFROZEN 0x04 3655 #define TARGET_MSG_PENDING 0x02 3656 #define PENDING_MK_MESSAGE 0x01 3657 3658 #define ALLOCFIFO_SCBPTR 0x14e 3659 3660 #define INT_COALESCING_TIMER 0x150 3661 3662 #define INT_COALESCING_MAXCMDS 0x152 3663 3664 #define INT_COALESCING_MINCMDS 0x153 3665 3666 #define CMDS_PENDING 0x154 3667 3668 #define INT_COALESCING_CMDCOUNT 0x156 3669 3670 #define LOCAL_HS_MAILBOX 0x157 3671 3672 #define CMDSIZE_TABLE 0x158 3673 3674 #define MK_MESSAGE_SCB 0x160 3675 3676 #define MK_MESSAGE_SCSIID 0x162 3677 3678 #define SCB_BASE 0x180 3679 3680 #define SCB_RESIDUAL_DATACNT 0x180 3681 #define SCB_HOST_CDB_PTR 0x180 3682 #define SCB_CDB_STORE 0x180 3683 3684 #define SCB_RESIDUAL_SGPTR 0x184 3685 #define SG_ADDR_MASK 0xf8 3686 #define SG_OVERRUN_RESID 0x02 3687 3688 #define SCB_SCSI_STATUS 0x188 3689 #define SCB_HOST_CDB_LEN 0x188 3690 3691 #define SCB_TARGET_PHASES 0x189 3692 3693 #define SCB_TARGET_DATA_DIR 0x18a 3694 3695 #define SCB_TARGET_ITAG 0x18b 3696 3697 #define SCB_SENSE_BUSADDR 0x18c 3698 #define SCB_NEXT_COMPLETE 0x18c 3699 3700 #define SCB_TAG 0x190 3701 #define SCB_FIFO_USE_COUNT 0x190 3702 3703 #define SCB_CONTROL 0x192 3704 #define TARGET_SCB 0x80 3705 #define DISCENB 0x40 3706 #define TAG_ENB 0x20 3707 #define MK_MESSAGE 0x10 3708 #define STATUS_RCVD 0x08 3709 #define DISCONNECTED 0x04 3710 #define SCB_TAG_TYPE 0x03 3711 3712 #define SCB_SCSIID 0x193 3713 #define TID 0xf0 3714 #define OID 0x0f 3715 3716 #define SCB_LUN 0x194 3717 #define LID 0xff 3718 3719 #define SCB_TASK_ATTRIBUTE 0x195 3720 #define SCB_XFERLEN_ODD 0x01 3721 3722 #define SCB_CDB_LEN 0x196 3723 #define SCB_CDB_LEN_PTR 0x80 3724 3725 #define SCB_TASK_MANAGEMENT 0x197 3726 3727 #define SCB_DATAPTR 0x198 3728 3729 #define SCB_DATACNT 0x1a0 3730 #define SG_LAST_SEG 0x80 3731 #define SG_HIGH_ADDR_BITS 0x7f 3732 3733 #define SCB_SGPTR 0x1a4 3734 #define SG_STATUS_VALID 0x04 3735 #define SG_FULL_RESID 0x02 3736 #define SG_LIST_NULL 0x01 3737 3738 #define SCB_BUSADDR 0x1a8 3739 3740 #define SCB_NEXT 0x1ac 3741 #define SCB_NEXT_SCB_BUSADDR 0x1ac 3742 3743 #define SCB_NEXT2 0x1ae 3744 3745 #define SCB_SPARE 0x1b0 3746 #define SCB_PKT_LUN 0x1b0 3747 3748 #define SCB_DISCONNECTED_LISTS 0x1b8 3749 3750 3751 #define AHD_TIMER_MAX_US 0x18ffe7 3752 #define STIMESEL_MIN 0x18 3753 #define TARGET_CMD_CMPLT 0xfe 3754 #define SEEOP_ERAL_ADDR 0x80 3755 #define SRC_MODE_SHIFT 0x00 3756 #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 3757 #define MAX_OFFSET_PACED 0xfe 3758 #define SEEOP_EWDS_ADDR 0x00 3759 #define AHD_ANNEXCOL_AMPLITUDE 0x06 3760 #define AHD_PRECOMP_CUTBACK_29 0x06 3761 #define AHD_ANNEXCOL_PER_DEV0 0x04 3762 #define AHD_TIMER_MAX_TICKS 0xffff 3763 #define STATUS_PKT_SENSE 0xff 3764 #define CMD_GROUP_CODE_SHIFT 0x05 3765 #define BUS_8_BIT 0x00 3766 #define CCSGRAM_MAXSEGS 0x10 3767 #define AHD_AMPLITUDE_DEF 0x07 3768 #define AHD_SLEWRATE_DEF_REVB 0x08 3769 #define AHD_PRECOMP_CUTBACK_37 0x07 3770 #define AHD_PRECOMP_SHIFT 0x00 3771 #define PKT_OVERRUN_BUFSIZE 0x200 3772 #define SCB_TRANSFER_SIZE_FULL_LUN 0x38 3773 #define TARGET_DATA_IN 0x01 3774 #define STATUS_BUSY 0x08 3775 #define BUS_16_BIT 0x01 3776 #define CCSCBADDR_MAX 0x80 3777 #define TID_SHIFT 0x04 3778 #define AHD_AMPLITUDE_SHIFT 0x00 3779 #define AHD_SLEWRATE_DEF_REVA 0x08 3780 #define AHD_SLEWRATE_MASK 0x78 3781 #define MAX_OFFSET_PACED_BUG 0x7f 3782 #define AHD_PRECOMP_CUTBACK_17 0x04 3783 #define AHD_PRECOMP_MASK 0x07 3784 #define AHD_TIMER_US_PER_TICK 0x19 3785 #define HOST_MSG 0xff 3786 #define MAX_OFFSET 0xfe 3787 #define BUS_32_BIT 0x02 3788 #define SEEOP_EWEN_ADDR 0xc0 3789 #define AHD_AMPLITUDE_MASK 0x07 3790 #define LUNLEN_SINGLE_LEVEL_LUN 0x0f 3791 #define DST_MODE_SHIFT 0x04 3792 #define STIMESEL_SHIFT 0x03 3793 #define SEEOP_WRAL_ADDR 0x40 3794 #define AHD_ANNEXCOL_PRECOMP_SLEW 0x04 3795 #define STATUS_QUEUE_FULL 0x28 3796 #define MAX_OFFSET_NON_PACED 0x7f 3797 #define WRTBIASCTL_HP_DEFAULT 0x00 3798 #define NUMDSPS 0x14 3799 #define AHD_NUM_PER_DEV_ANNEXCOLS 0x04 3800 #define NVRAM_SCB_OFFSET 0x2c 3801 #define AHD_SENSE_BUFSIZE 0x100 3802 #define STIMESEL_BUG_ADJ 0x08 3803 #define INVALID_ADDR 0x80 3804 #define CCSGADDR_MAX 0x80 3805 #define MK_MESSAGE_BIT_OFFSET 0x04 3806 #define AHD_SLEWRATE_SHIFT 0x03 3807 #define B_CURRFIFO_0 0x02 3808 3809 3810 /* Downloaded Constant Definitions */ 3811 #define SG_SIZEOF 0x04 3812 #define CACHELINE_MASK 0x07 3813 #define SG_PREFETCH_ADDR_MASK 0x03 3814 #define SG_PREFETCH_ALIGN_MASK 0x02 3815 #define SCB_TRANSFER_SIZE 0x06 3816 #define SG_PREFETCH_CNT 0x00 3817 #define SG_PREFETCH_CNT_LIMIT 0x01 3818 #define PKT_OVERRUN_BUFOFFSET 0x05 3819 #define DOWNLOAD_CONST_COUNT 0x08 3820 3821 3822 /* Exported Labels */ 3823 #define LABEL_seq_isr 0x28f 3824 #define LABEL_timer_isr 0x28b 3825