1 /* $NetBSD: dwc2_hcd.h,v 1.15 2018/08/08 07:20:44 simonb Exp $ */
2
3 /*
4 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 *
6 * Copyright (C) 2004-2013 Synopsys, Inc.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The names of the above-listed copyright holders may not be used
18 * to endorse or promote products derived from this software without
19 * specific prior written permission.
20 *
21 * ALTERNATIVELY, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") as published by the Free Software
23 * Foundation; either version 2 of the License, or (at your option) any
24 * later version.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38 #ifndef __DWC2_HCD_H__
39 #define __DWC2_HCD_H__
40
41 /*
42 * This file contains the structures, constants, and interfaces for the
43 * Host Contoller Driver (HCD)
44 *
45 * The Host Controller Driver (HCD) is responsible for translating requests
46 * from the USB Driver into the appropriate actions on the DWC_otg controller.
47 * It isolates the USBD from the specifics of the controller by providing an
48 * API to the USBD.
49 */
50
51 struct dwc2_qh;
52
53 /**
54 * struct dwc2_host_chan - Software host channel descriptor
55 *
56 * @hc_num: Host channel number, used for register address lookup
57 * @dev_addr: Address of the device
58 * @ep_num: Endpoint of the device
59 * @ep_is_in: Endpoint direction
60 * @speed: Device speed. One of the following values:
61 * - USB_SPEED_LOW
62 * - USB_SPEED_FULL
63 * - USB_SPEED_HIGH
64 * @ep_type: Endpoint type. One of the following values:
65 * - USB_ENDPOINT_XFER_CONTROL: 0
66 * - USB_ENDPOINT_XFER_ISOC: 1
67 * - USB_ENDPOINT_XFER_BULK: 2
68 * - USB_ENDPOINT_XFER_INTR: 3
69 * @max_packet: Max packet size in bytes
70 * @data_pid_start: PID for initial transaction.
71 * 0: DATA0
72 * 1: DATA2
73 * 2: DATA1
74 * 3: MDATA (non-Control EP),
75 * SETUP (Control EP)
76 * @multi_count: Number of additional periodic transactions per
77 * (micro)frame
78 * @xfer_buf: Pointer to current transfer buffer position
79 * @xfer_dma: DMA address of xfer_buf
80 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not
81 * DWORD aligned
82 * @xfer_len: Total number of bytes to transfer
83 * @xfer_count: Number of bytes transferred so far
84 * @start_pkt_count: Packet count at start of transfer
85 * @xfer_started: True if the transfer has been started
86 * @ping: True if a PING request should be issued on this channel
87 * @error_state: True if the error count for this transaction is non-zero
88 * @halt_on_queue: True if this channel should be halted the next time a
89 * request is queued for the channel. This is necessary in
90 * slave mode if no request queue space is available when
91 * an attempt is made to halt the channel.
92 * @halt_pending: True if the host channel has been halted, but the core
93 * is not finished flushing queued requests
94 * @do_split: Enable split for the channel
95 * @complete_split: Enable complete split
96 * @hub_addr: Address of high speed hub for the split
97 * @hub_port: Port of the low/full speed device for the split
98 * @xact_pos: Split transaction position. One of the following values:
99 * - DWC2_HCSPLT_XACTPOS_MID
100 * - DWC2_HCSPLT_XACTPOS_BEGIN
101 * - DWC2_HCSPLT_XACTPOS_END
102 * - DWC2_HCSPLT_XACTPOS_ALL
103 * @requests: Number of requests issued for this channel since it was
104 * assigned to the current transfer (not counting PINGs)
105 * @schinfo: Scheduling micro-frame bitmap
106 * @ntd: Number of transfer descriptors for the transfer
107 * @halt_status: Reason for halting the host channel
108 * @hcint Contents of the HCINT register when the interrupt came
109 * @qh: QH for the transfer being processed by this channel
110 * @hc_list_entry: For linking to list of host channels
111 * @desc_list_addr: Current QH's descriptor list DMA address
112 * @desc_list_sz: Current QH's descriptor list size
113 *
114 * This structure represents the state of a single host channel when acting in
115 * host mode. It contains the data items needed to transfer packets to an
116 * endpoint via a host channel.
117 */
118 struct dwc2_host_chan {
119 u8 hc_num;
120
121 unsigned dev_addr:7;
122 unsigned ep_num:4;
123 unsigned ep_is_in:1;
124 unsigned speed:4;
125 unsigned ep_type:2;
126 unsigned max_packet:11;
127 unsigned data_pid_start:2;
128 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
129 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
130 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
131 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
132 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
133
134 unsigned multi_count:2;
135
136 usb_dma_t *xfer_usbdma;
137 u8 *xfer_buf;
138 dma_addr_t xfer_dma;
139 dma_addr_t align_buf;
140 u32 xfer_len;
141 u32 xfer_count;
142 u16 start_pkt_count;
143 u8 xfer_started;
144 u8 do_ping;
145 u8 error_state;
146 u8 halt_on_queue;
147 u8 halt_pending;
148 u8 do_split;
149 u8 complete_split;
150 u8 hub_addr;
151 u8 hub_port;
152 u8 xact_pos;
153 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
154 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
155 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
156 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
157
158 u8 requests;
159 u8 schinfo;
160 u16 ntd;
161 enum dwc2_halt_status halt_status;
162 u32 hcint;
163 struct dwc2_qh *qh;
164 struct list_head hc_list_entry;
165 usb_dma_t desc_list_usbdma;
166 dma_addr_t desc_list_addr;
167 u32 desc_list_sz;
168 };
169
170 struct dwc2_hcd_pipe_info {
171 u8 dev_addr;
172 u8 ep_num;
173 u8 pipe_type;
174 u8 pipe_dir;
175 u16 mps;
176 };
177
178 struct dwc2_hcd_iso_packet_desc {
179 u32 offset;
180 u32 length;
181 u32 actual_length;
182 u32 status;
183 };
184
185 struct dwc2_qtd;
186
187 struct dwc2_hcd_urb {
188 void *priv; /* the xfer handle */
189 struct dwc2_qtd *qtd;
190 usb_dma_t *usbdma;
191 u8 *buf;
192 dma_addr_t dma;
193 usb_dma_t *setup_usbdma;
194 void *setup_packet;
195 dma_addr_t setup_dma;
196 u32 length;
197 u32 actual_length;
198 u32 status;
199 u32 error_count;
200 u32 packet_count;
201 u32 flags;
202 u16 interval;
203 struct dwc2_hcd_pipe_info pipe_info;
204 struct dwc2_hcd_iso_packet_desc iso_descs[0];
205 };
206
207 /* Phases for control transfers */
208 enum dwc2_control_phase {
209 DWC2_CONTROL_SETUP,
210 DWC2_CONTROL_DATA,
211 DWC2_CONTROL_STATUS,
212 };
213
214 /* Transaction types */
215 enum dwc2_transaction_type {
216 DWC2_TRANSACTION_NONE,
217 DWC2_TRANSACTION_PERIODIC,
218 DWC2_TRANSACTION_NON_PERIODIC,
219 DWC2_TRANSACTION_ALL,
220 };
221
222 /**
223 * struct dwc2_qh - Software queue head structure
224 *
225 * @hsotg: The HCD state structure for the DWC OTG controller
226 * @ep_type: Endpoint type. One of the following values:
227 * - USB_ENDPOINT_XFER_CONTROL
228 * - USB_ENDPOINT_XFER_BULK
229 * - USB_ENDPOINT_XFER_INT
230 * - USB_ENDPOINT_XFER_ISOC
231 * @ep_is_in: Endpoint direction
232 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
233 * @dev_speed: Device speed. One of the following values:
234 * - USB_SPEED_LOW
235 * - USB_SPEED_FULL
236 * - USB_SPEED_HIGH
237 * @data_toggle: Determines the PID of the next data packet for
238 * non-controltransfers. Ignored for control transfers.
239 * One of the following values:
240 * - DWC2_HC_PID_DATA0
241 * - DWC2_HC_PID_DATA1
242 * @ping_state: Ping state
243 * @do_split: Full/low speed endpoint on high-speed hub requires split
244 * @td_first: Index of first activated isochronous transfer descriptor
245 * @td_last: Index of last activated isochronous transfer descriptor
246 * @usecs: Bandwidth in microseconds per (micro)frame
247 * @interval: Interval between transfers in (micro)frames
248 * @sched_frame: (Micro)frame to initialize a periodic transfer.
249 * The transfer executes in the following (micro)frame.
250 * @nak_frame: Internal variable used by the NAK holdoff code
251 * @frame_usecs: Internal variable used by the microframe scheduler
252 * @start_split_frame: (Micro)frame at which last start split was initialized
253 * @ntd: Actual number of transfer descriptors in a list
254 * @dw_align_buf: Used instead of original buffer if its physical address
255 * is not dword-aligned
256 * @dw_align_buf_size: Size of dw_align_buf
257 * @dw_align_buf_dma: DMA address for dw_align_buf
258 * @qtd_list: List of QTDs for this QH
259 * @channel: Host channel currently processing transfers for this QH
260 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
261 * schedule
262 * @desc_list: List of transfer descriptors
263 * @desc_list_dma: Physical address of desc_list
264 * @desc_list_sz: Size of descriptors list
265 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
266 * descriptor and indicates original XferSize value for the
267 * descriptor
268 * @wait_timer: Timer used to wait before re-queuing.
269 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
270 * @want_wait: We should wait before re-queuing; only matters for non-
271 * periodic transfers and is ignored for periodic ones.
272 * @wait_timer_cancel: Set to true to cancel the wait_timer.
273 *
274 * A Queue Head (QH) holds the static characteristics of an endpoint and
275 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
276 * be entered in either the non-periodic or periodic schedule.
277 */
278 struct dwc2_qh {
279 struct dwc2_hsotg *hsotg;
280 u8 ep_type;
281 u8 ep_is_in;
282 u16 maxp;
283 u8 dev_speed;
284 u8 data_toggle;
285 u8 ping_state;
286 u8 do_split;
287 u8 td_first;
288 u8 td_last;
289 u16 usecs;
290 u16 interval;
291 u16 sched_frame;
292 u16 nak_frame;
293 u16 frame_usecs[8];
294 u16 start_split_frame;
295 u16 ntd;
296 usb_dma_t dw_align_buf_usbdma;
297 u8 *dw_align_buf;
298 int dw_align_buf_size;
299 dma_addr_t dw_align_buf_dma;
300 struct list_head qtd_list;
301 struct dwc2_host_chan *channel;
302 struct list_head qh_list_entry;
303 usb_dma_t desc_list_usbdma;
304 struct dwc2_hcd_dma_desc *desc_list;
305 dma_addr_t desc_list_dma;
306 u32 desc_list_sz;
307 u32 *n_bytes;
308 /* XXX struct timer_list wait_timer; */
309 callout_t wait_timer;
310 unsigned tt_buffer_dirty:1;
311 unsigned want_wait:1;
312 unsigned wait_timer_cancel:1;
313 };
314
315 /**
316 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
317 *
318 * @control_phase: Current phase for control transfers (Setup, Data, or
319 * Status)
320 * @in_process: Indicates if this QTD is currently processed by HW
321 * @data_toggle: Determines the PID of the next data packet for the
322 * data phase of control transfers. Ignored for other
323 * transfer types. One of the following values:
324 * - DWC2_HC_PID_DATA0
325 * - DWC2_HC_PID_DATA1
326 * @complete_split: Keeps track of the current split type for FS/LS
327 * endpoints on a HS Hub
328 * @isoc_split_pos: Position of the ISOC split in full/low speed
329 * @isoc_frame_index: Index of the next frame descriptor for an isochronous
330 * transfer. A frame descriptor describes the buffer
331 * position and length of the data to be transferred in the
332 * next scheduled (micro)frame of an isochronous transfer.
333 * It also holds status for that transaction. The frame
334 * index starts at 0.
335 * @isoc_split_offset: Position of the ISOC split in the buffer for the
336 * current frame
337 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
338 * @error_count: Holds the number of bus errors that have occurred for
339 * a transaction within this transfer
340 * @n_desc: Number of DMA descriptors for this QTD
341 * @isoc_frame_index_last: Last activated frame (packet) index, used in
342 * descriptor DMA mode only
343 * @num_naks: Number of NAKs received on this QTD.
344 * @urb: URB for this transfer
345 * @qh: Queue head for this QTD
346 * @qtd_list_entry: For linking to the QH's list of QTDs
347 *
348 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
349 * interrupt, or isochronous transfer. A single QTD is created for each URB
350 * (of one of these types) submitted to the HCD. The transfer associated with
351 * a QTD may require one or multiple transactions.
352 *
353 * A QTD is linked to a Queue Head, which is entered in either the
354 * non-periodic or periodic schedule for execution. When a QTD is chosen for
355 * execution, some or all of its transactions may be executed. After
356 * execution, the state of the QTD is updated. The QTD may be retired if all
357 * its transactions are complete or if an error occurred. Otherwise, it
358 * remains in the schedule so more transactions can be executed later.
359 */
360 struct dwc2_qtd {
361 enum dwc2_control_phase control_phase;
362 u8 in_process;
363 u8 data_toggle;
364 u8 complete_split;
365 u8 isoc_split_pos;
366 u16 isoc_frame_index;
367 u16 isoc_split_offset;
368 u16 isoc_td_last;
369 u16 isoc_td_first;
370 u32 ssplit_out_xfer_count;
371 u8 error_count;
372 u8 n_desc;
373 u16 isoc_frame_index_last;
374 u16 num_naks;
375 struct dwc2_hcd_urb *urb;
376 struct dwc2_qh *qh;
377 struct list_head qtd_list_entry;
378 };
379
380 #ifdef DEBUG
381 struct hc_xfer_info {
382 struct dwc2_hsotg *hsotg;
383 struct dwc2_host_chan *chan;
384 };
385 #endif
386
387 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
dwc2_hsotg_to_hcd(struct dwc2_hsotg * hsotg)388 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
389 {
390 return (struct usb_hcd *)hsotg->priv;
391 }
392
393 /*
394 * Inline used to disable one channel interrupt. Channel interrupts are
395 * disabled when the channel is halted or released by the interrupt handler.
396 * There is no need to handle further interrupts of that type until the
397 * channel is re-assigned. In fact, subsequent handling may cause crashes
398 * because the channel structures are cleaned up when the channel is released.
399 */
disable_hc_int(struct dwc2_hsotg * hsotg,int chnum,u32 intr)400 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
401 {
402 u32 mask = DWC2_READ_4(hsotg, HCINTMSK(chnum));
403
404 mask &= ~intr;
405 DWC2_WRITE_4(hsotg, HCINTMSK(chnum), mask);
406 }
407
408 /*
409 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
410 * are read as 1, they won't clear when written back.
411 */
dwc2_read_hprt0(struct dwc2_hsotg * hsotg)412 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
413 {
414 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0);
415
416 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
417 return hprt0;
418 }
419
dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info * pipe)420 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
421 {
422 return pipe->ep_num;
423 }
424
dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info * pipe)425 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
426 {
427 return pipe->pipe_type;
428 }
429
dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info * pipe)430 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe)
431 {
432 return pipe->mps;
433 }
434
dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info * pipe)435 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
436 {
437 return pipe->dev_addr;
438 }
439
dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info * pipe)440 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
441 {
442 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
443 }
444
dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info * pipe)445 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
446 {
447 return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
448 }
449
dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info * pipe)450 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
451 {
452 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
453 }
454
dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info * pipe)455 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
456 {
457 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
458 }
459
dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info * pipe)460 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
461 {
462 return pipe->pipe_dir == USB_DIR_IN;
463 }
464
dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info * pipe)465 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
466 {
467 return !dwc2_hcd_is_pipe_in(pipe);
468 }
469
470 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
471 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
472
473 /* Transaction Execution Functions */
474 extern enum dwc2_transaction_type dwc2_hcd_select_transactions(
475 struct dwc2_hsotg *hsotg);
476 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
477 enum dwc2_transaction_type tr_type);
478
479 /* Schedule Queue Functions */
480 /* Implemented in hcd_queue.c */
481 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg);
482 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
483 struct dwc2_hcd_urb *urb,
484 gfp_t mem_flags);
485 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
486 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
487 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
488 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
489 int sched_csplit);
490
491 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
492 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
493 struct dwc2_qh *qh);
494
495 /* Removes and frees a QTD */
496 extern void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
497 struct dwc2_qtd *qtd,
498 struct dwc2_qh *qh);
499
500 /* Descriptor DMA support functions */
501 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
502 struct dwc2_qh *qh);
503 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
504 struct dwc2_host_chan *chan, int chnum,
505 enum dwc2_halt_status halt_status);
506
507 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
508 gfp_t mem_flags);
509 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
510
511 /* Check if QH is non-periodic */
512 #define dwc2_qh_is_non_per(_qh_ptr_) \
513 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
514 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
515
516 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
dbg_hc(struct dwc2_host_chan * hc)517 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
dbg_qh(struct dwc2_qh * qh)518 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
dbg_perio(void)519 static inline bool dbg_perio(void) { return true; }
520 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
dbg_hc(struct dwc2_host_chan * hc)521 static inline bool dbg_hc(struct dwc2_host_chan *hc)
522 {
523 return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
524 hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
525 }
526
dbg_qh(struct dwc2_qh * qh)527 static inline bool dbg_qh(struct dwc2_qh *qh)
528 {
529 return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
530 qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
531 }
532
533
dbg_perio(void)534 static inline bool dbg_perio(void) { return false; }
535 #endif
536
537 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */
538 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))
539
540 /* Packet size for any kind of endpoint descriptor */
541 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff)
542
543 /*
544 * Returns true if frame1 index is greater than frame2 index. The comparison
545 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
546 * frame number when the max index frame number is reached.
547 */
dwc2_frame_idx_num_gt(u16 fr_idx1,u16 fr_idx2)548 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
549 {
550 u16 diff = fr_idx1 - fr_idx2;
551 u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
552
553 return diff && !sign;
554 }
555
556 /*
557 * Returns true if frame1 is less than or equal to frame2. The comparison is
558 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
559 * frame number when the max frame number is reached.
560 */
dwc2_frame_num_le(u16 frame1,u16 frame2)561 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
562 {
563 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
564 }
565
566 /*
567 * Returns true if frame1 is greater than frame2. The comparison is done
568 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
569 * number when the max frame number is reached.
570 */
dwc2_frame_num_gt(u16 frame1,u16 frame2)571 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
572 {
573 return (frame1 != frame2) &&
574 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
575 }
576
577 /*
578 * Increments frame by the amount specified by inc. The addition is done
579 * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
580 */
dwc2_frame_num_inc(u16 frame,u16 inc)581 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
582 {
583 return (frame + inc) & HFNUM_MAX_FRNUM;
584 }
585
dwc2_full_frame_num(u16 frame)586 static inline u16 dwc2_full_frame_num(u16 frame)
587 {
588 return (frame & HFNUM_MAX_FRNUM) >> 3;
589 }
590
dwc2_micro_frame_num(u16 frame)591 static inline u16 dwc2_micro_frame_num(u16 frame)
592 {
593 return frame & 0x7;
594 }
595
596 /*
597 * Returns the Core Interrupt Status register contents, ANDed with the Core
598 * Interrupt Mask register contents
599 */
dwc2_read_core_intr(struct dwc2_hsotg * hsotg)600 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
601 {
602 return DWC2_READ_4(hsotg, GINTSTS) & DWC2_READ_4(hsotg, GINTMSK);
603 }
604
dwc2_hcd_urb_get_status(struct dwc2_hcd_urb * dwc2_urb)605 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
606 {
607 return dwc2_urb->status;
608 }
609
dwc2_hcd_urb_get_actual_length(struct dwc2_hcd_urb * dwc2_urb)610 static inline u32 dwc2_hcd_urb_get_actual_length(
611 struct dwc2_hcd_urb *dwc2_urb)
612 {
613 return dwc2_urb->actual_length;
614 }
615
dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb * dwc2_urb)616 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
617 {
618 return dwc2_urb->error_count;
619 }
620
dwc2_hcd_urb_set_iso_desc_params(struct dwc2_hcd_urb * dwc2_urb,int desc_num,u32 offset,u32 length)621 static inline void dwc2_hcd_urb_set_iso_desc_params(
622 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
623 u32 length)
624 {
625 dwc2_urb->iso_descs[desc_num].offset = offset;
626 dwc2_urb->iso_descs[desc_num].length = length;
627 }
628
dwc2_hcd_urb_get_iso_desc_status(struct dwc2_hcd_urb * dwc2_urb,int desc_num)629 static inline u32 dwc2_hcd_urb_get_iso_desc_status(
630 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
631 {
632 return dwc2_urb->iso_descs[desc_num].status;
633 }
634
dwc2_hcd_urb_get_iso_desc_actual_length(struct dwc2_hcd_urb * dwc2_urb,int desc_num)635 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
636 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
637 {
638 return dwc2_urb->iso_descs[desc_num].actual_length;
639 }
640
dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg * hsotg,struct usbd_xfer * xfer)641 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
642 struct usbd_xfer *xfer)
643 {
644 struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
645 struct dwc2_qh *qh = dpipe->priv;
646
647 if (qh && !list_empty(&qh->qh_list_entry))
648 return 1;
649
650 return 0;
651 }
652
dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg * hsotg,struct dwc2_pipe * dpipe)653 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
654 struct dwc2_pipe *dpipe)
655 {
656 struct dwc2_qh *qh = dpipe->priv;
657
658 if (!qh) {
659 WARN_ON(1);
660 return 0;
661 }
662
663 return qh->usecs;
664 }
665
666 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
667 struct dwc2_host_chan *chan, int chnum,
668 struct dwc2_qtd *qtd);
669
670 /* HCD Core API */
671
672 /**
673 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
674 *
675 * @hsotg: The DWC2 HCD
676 *
677 * Returns IRQ_HANDLED if interrupt is handled
678 * Return IRQ_NONE if interrupt is not handled
679 */
680 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
681
682 /**
683 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
684 *
685 * @hsotg: The DWC2 HCD
686 */
687 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
688
689 /**
690 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
691 * and 0 otherwise
692 *
693 * @hsotg: The DWC2 HCD
694 */
695 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
696
697 /**
698 * dwc2_hcd_dump_state() - Dumps hsotg state
699 *
700 * @hsotg: The DWC2 HCD
701 *
702 * NOTE: This function will be removed once the peripheral controller code
703 * is integrated and the driver is stable
704 */
705 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
706
707 /**
708 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
709 *
710 * @hsotg: The DWC2 HCD
711 *
712 * This can be used to determine average interrupt latency. Frame remaining is
713 * also shown for start transfer and two additional sample points.
714 *
715 * NOTE: This function will be removed once the peripheral controller code
716 * is integrated and the driver is stable
717 */
718 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
719
720 /* URB interface */
721
722 /* Transfer flags */
723 #define URB_GIVEBACK_ASAP 0x1
724 #define URB_SEND_ZERO_PACKET 0x2
725
726 /* Host driver callbacks */
727
728 extern void dwc2_host_start(struct dwc2_hsotg *hsotg);
729 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg);
730 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
731 int *hub_addr, int *hub_port);
732 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
733 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
734 int status);
735
736 #ifdef DEBUG
737 /*
738 * Macro to sample the remaining PHY clocks left in the current frame. This
739 * may be used during debugging to determine the average time it takes to
740 * execute sections of code. There are two possible sample points, "a" and
741 * "b", so the _letter_ argument must be one of these values.
742 *
743 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
744 * example, "cat /sys/devices/lm0/hcd_frrem".
745 */
746 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \
747 do { \
748 struct hfnum_data _hfnum_; \
749 struct dwc2_qtd *_qtd_; \
750 \
751 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \
752 qtd_list_entry); \
753 if (usb_pipeint(_qtd_->urb->pipe) && \
754 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
755 _hfnum_.d32 = DWC2_READ_4((_hcd_), HFNUM); \
756 switch (_hfnum_.b.frnum & 0x7) { \
757 case 7: \
758 (_hcd_)->hfnum_7_samples_##_letter_++; \
759 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \
760 _hfnum_.b.frrem; \
761 break; \
762 case 0: \
763 (_hcd_)->hfnum_0_samples_##_letter_++; \
764 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \
765 _hfnum_.b.frrem; \
766 break; \
767 default: \
768 (_hcd_)->hfnum_other_samples_##_letter_++; \
769 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \
770 _hfnum_.b.frrem; \
771 break; \
772 } \
773 } \
774 } while (0)
775 #else
776 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0)
777 #endif
778
779
780 void dwc2_wakeup_detected(void *);
781
782 int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *, struct dwc2_hcd_urb *);
783 void dwc2_hcd_reinit(struct dwc2_hsotg *);
784 int dwc2_hcd_hub_control(struct dwc2_hsotg *, u16, u16, u16, char *, u16);
785 struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *);
786 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
787 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
788 struct dwc2_qtd *qtd);
789 void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *, struct dwc2_hcd_urb *,
790 u8 ,u8, u8, u8, u16);
791
792 struct dwc2_hcd_urb * dwc2_hcd_urb_alloc(struct dwc2_hsotg *, int, gfp_t);
793 void dwc2_hcd_urb_free(struct dwc2_hsotg *, struct dwc2_hcd_urb *, int);
794
795 int _dwc2_hcd_start(struct dwc2_hsotg *);
796
797 int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *);
798
799 #endif /* __DWC2_HCD_H__ */
800