1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// FRAME_ALLOC_RECOVER - Represents the llvm.framerecover 76 /// intrinsic. Materializes the offset from the frame pointer of another 77 /// function to the result of llvm.frameallocate. 78 FRAME_ALLOC_RECOVER, 79 80 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 81 /// the DAG, which implements the named register global variables extension. 82 READ_REGISTER, 83 WRITE_REGISTER, 84 85 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 86 /// first (possible) on-stack argument. This is needed for correct stack 87 /// adjustment during unwind. 88 FRAME_TO_ARGS_OFFSET, 89 90 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 91 /// 'eh_return' gcc dwarf builtin, which is used to return from 92 /// exception. The general meaning is: adjust stack by OFFSET and pass 93 /// execution to HANDLER. Many platform-related details also :) 94 EH_RETURN, 95 96 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 97 /// This corresponds to the eh.sjlj.setjmp intrinsic. 98 /// It takes an input chain and a pointer to the jump buffer as inputs 99 /// and returns an outchain. 100 EH_SJLJ_SETJMP, 101 102 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 103 /// This corresponds to the eh.sjlj.longjmp intrinsic. 104 /// It takes an input chain and a pointer to the jump buffer as inputs 105 /// and returns an outchain. 106 EH_SJLJ_LONGJMP, 107 108 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 109 /// simplification, or lowering of the constant. They are used for constants 110 /// which are known to fit in the immediate fields of their users, or for 111 /// carrying magic numbers which are not values which need to be 112 /// materialized in registers. 113 TargetConstant, 114 TargetConstantFP, 115 116 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 117 /// anything else with this node, and this is valid in the target-specific 118 /// dag, turning into a GlobalAddress operand. 119 TargetGlobalAddress, 120 TargetGlobalTLSAddress, 121 TargetFrameIndex, 122 TargetJumpTable, 123 TargetConstantPool, 124 TargetExternalSymbol, 125 TargetBlockAddress, 126 127 /// TargetIndex - Like a constant pool entry, but with completely 128 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 129 /// 64-bit index. Targets can use this however they like. 130 TargetIndex, 131 132 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 133 /// This node represents a target intrinsic function with no side effects. 134 /// The first operand is the ID number of the intrinsic from the 135 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 136 /// node returns the result of the intrinsic. 137 INTRINSIC_WO_CHAIN, 138 139 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 140 /// This node represents a target intrinsic function with side effects that 141 /// returns a result. The first operand is a chain pointer. The second is 142 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 143 /// operands to the intrinsic follow. The node has two results, the result 144 /// of the intrinsic and an output chain. 145 INTRINSIC_W_CHAIN, 146 147 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 148 /// This node represents a target intrinsic function with side effects that 149 /// does not return a result. The first operand is a chain pointer. The 150 /// second is the ID number of the intrinsic from the llvm::Intrinsic 151 /// namespace. The operands to the intrinsic follow. 152 INTRINSIC_VOID, 153 154 /// CopyToReg - This node has three operands: a chain, a register number to 155 /// set to this value, and a value. 156 CopyToReg, 157 158 /// CopyFromReg - This node indicates that the input value is a virtual or 159 /// physical register that is defined outside of the scope of this 160 /// SelectionDAG. The register is available from the RegisterSDNode object. 161 CopyFromReg, 162 163 /// UNDEF - An undefined node. 164 UNDEF, 165 166 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 167 /// a Constant, which is required to be operand #1) half of the integer or 168 /// float value specified as operand #0. This is only for use before 169 /// legalization, for values that will be broken into multiple registers. 170 EXTRACT_ELEMENT, 171 172 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 173 /// Given two values of the same integer value type, this produces a value 174 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 175 /// legalization. 176 BUILD_PAIR, 177 178 /// MERGE_VALUES - This node takes multiple discrete operands and returns 179 /// them all as its individual results. This nodes has exactly the same 180 /// number of inputs and outputs. This node is useful for some pieces of the 181 /// code generator that want to think about a single node with multiple 182 /// results, not multiple nodes. 183 MERGE_VALUES, 184 185 /// Simple integer binary arithmetic operators. 186 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 187 188 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 189 /// a signed/unsigned value of type i[2*N], and return the full value as 190 /// two results, each of type iN. 191 SMUL_LOHI, UMUL_LOHI, 192 193 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 194 /// remainder result. 195 SDIVREM, UDIVREM, 196 197 /// CARRY_FALSE - This node is used when folding other nodes, 198 /// like ADDC/SUBC, which indicate the carry result is always false. 199 CARRY_FALSE, 200 201 /// Carry-setting nodes for multiple precision addition and subtraction. 202 /// These nodes take two operands of the same value type, and produce two 203 /// results. The first result is the normal add or sub result, the second 204 /// result is the carry flag result. 205 ADDC, SUBC, 206 207 /// Carry-using nodes for multiple precision addition and subtraction. These 208 /// nodes take three operands: The first two are the normal lhs and rhs to 209 /// the add or sub, and the third is the input carry flag. These nodes 210 /// produce two results; the normal result of the add or sub, and the output 211 /// carry flag. These nodes both read and write a carry flag to allow them 212 /// to them to be chained together for add and sub of arbitrarily large 213 /// values. 214 ADDE, SUBE, 215 216 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 217 /// These nodes take two operands: the normal LHS and RHS to the add. They 218 /// produce two results: the normal result of the add, and a boolean that 219 /// indicates if an overflow occurred (*not* a flag, because it may be store 220 /// to memory, etc.). If the type of the boolean is not i1 then the high 221 /// bits conform to getBooleanContents. 222 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 223 SADDO, UADDO, 224 225 /// Same for subtraction. 226 SSUBO, USUBO, 227 228 /// Same for multiplication. 229 SMULO, UMULO, 230 231 /// Simple binary floating point operators. 232 FADD, FSUB, FMUL, FMA, FDIV, FREM, 233 234 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 235 /// DAG node does not require that X and Y have the same type, just that the 236 /// are both floating point. X and the result must have the same type. 237 /// FCOPYSIGN(f32, f64) is allowed. 238 FCOPYSIGN, 239 240 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 241 /// value as an integer 0/1 value. 242 FGETSIGN, 243 244 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 245 /// specified, possibly variable, elements. The number of elements is 246 /// required to be a power of two. The types of the operands must all be 247 /// the same and must match the vector element type, except that integer 248 /// types are allowed to be larger than the element type, in which case 249 /// the operands are implicitly truncated. 250 BUILD_VECTOR, 251 252 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 253 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 254 /// element type then VAL is truncated before replacement. 255 INSERT_VECTOR_ELT, 256 257 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 258 /// identified by the (potentially variable) element number IDX. If the 259 /// return type is an integer type larger than the element type of the 260 /// vector, the result is extended to the width of the return type. 261 EXTRACT_VECTOR_ELT, 262 263 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 264 /// vector type with the same length and element type, this produces a 265 /// concatenated vector result value, with length equal to the sum of the 266 /// lengths of the input vectors. 267 CONCAT_VECTORS, 268 269 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 270 /// with VECTOR2 inserted into VECTOR1 at the (potentially 271 /// variable) element number IDX, which must be a multiple of the 272 /// VECTOR2 vector length. The elements of VECTOR1 starting at 273 /// IDX are overwritten with VECTOR2. Elements IDX through 274 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 275 INSERT_SUBVECTOR, 276 277 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 278 /// vector value) starting with the element number IDX, which must be a 279 /// constant multiple of the result vector length. 280 EXTRACT_SUBVECTOR, 281 282 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 283 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 284 /// values that indicate which value (or undef) each result element will 285 /// get. These constant ints are accessible through the 286 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 287 /// 'vperm' instruction, except that the indices must be constants and are 288 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 289 VECTOR_SHUFFLE, 290 291 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 292 /// scalar value into element 0 of the resultant vector type. The top 293 /// elements 1 to N-1 of the N-element vector are undefined. The type 294 /// of the operand must match the vector element type, except when they 295 /// are integer types. In this case the operand is allowed to be wider 296 /// than the vector element type, and is implicitly truncated to it. 297 SCALAR_TO_VECTOR, 298 299 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 300 /// producing an unsigned/signed value of type i[2*N], then return the top 301 /// part. 302 MULHU, MULHS, 303 304 /// Bitwise operators - logical and, logical or, logical xor. 305 AND, OR, XOR, 306 307 /// Shift and rotation operations. After legalization, the type of the 308 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 309 /// the shift amount can be any type, but care must be taken to ensure it is 310 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 311 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 312 /// to represent the shift amount. 313 /// When the 1st operand is a vector, the shift amount must be in the same 314 /// type. (TLI.getShiftAmountTy() will return the same type when the input 315 /// type is a vector.) 316 SHL, SRA, SRL, ROTL, ROTR, 317 318 /// Byte Swap and Counting operators. 319 BSWAP, CTTZ, CTLZ, CTPOP, 320 321 /// Bit counting operators with an undefined result for zero inputs. 322 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 323 324 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 325 /// i1 then the high bits must conform to getBooleanContents. 326 SELECT, 327 328 /// Select with a vector condition (op #0) and two vector operands (ops #1 329 /// and #2), returning a vector result. All vectors have the same length. 330 /// Much like the scalar select and setcc, each bit in the condition selects 331 /// whether the corresponding result element is taken from op #1 or op #2. 332 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 333 /// change the condition type in order to match the VSELECT node using a 334 /// pattern. The condition follows the BooleanContent format of the target. 335 VSELECT, 336 337 /// Select with condition operator - This selects between a true value and 338 /// a false value (ops #2 and #3) based on the boolean result of comparing 339 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 340 /// condition code in op #4, a CondCodeSDNode. 341 SELECT_CC, 342 343 /// SetCC operator - This evaluates to a true value iff the condition is 344 /// true. If the result value type is not i1 then the high bits conform 345 /// to getBooleanContents. The operands to this are the left and right 346 /// operands to compare (ops #0, and #1) and the condition code to compare 347 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 348 /// then the result type must also be a vector type. 349 SETCC, 350 351 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 352 /// integer shift operations, just like ADD/SUB_PARTS. The operation 353 /// ordering is: 354 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 355 SHL_PARTS, SRA_PARTS, SRL_PARTS, 356 357 /// Conversion operators. These are all single input single output 358 /// operations. For all of these, the result type must be strictly 359 /// wider or narrower (depending on the operation) than the source 360 /// type. 361 362 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 363 /// into new bits. 364 SIGN_EXTEND, 365 366 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 367 ZERO_EXTEND, 368 369 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 370 ANY_EXTEND, 371 372 /// TRUNCATE - Completely drop the high bits. 373 TRUNCATE, 374 375 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 376 /// depends on the first letter) to floating point. 377 SINT_TO_FP, 378 UINT_TO_FP, 379 380 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 381 /// sign extend a small value in a large integer register (e.g. sign 382 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 383 /// with the 7th bit). The size of the smaller type is indicated by the 1th 384 /// operand, a ValueType node. 385 SIGN_EXTEND_INREG, 386 387 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 388 /// in-register any-extension of the low lanes of an integer vector. The 389 /// result type must have fewer elements than the operand type, and those 390 /// elements must be larger integer types such that the total size of the 391 /// operand type and the result type match. Each of the low operand 392 /// elements is any-extended into the corresponding, wider result 393 /// elements with the high bits becoming undef. 394 ANY_EXTEND_VECTOR_INREG, 395 396 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 397 /// in-register sign-extension of the low lanes of an integer vector. The 398 /// result type must have fewer elements than the operand type, and those 399 /// elements must be larger integer types such that the total size of the 400 /// operand type and the result type match. Each of the low operand 401 /// elements is sign-extended into the corresponding, wider result 402 /// elements. 403 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 404 // scalars, but it also doesn't handle vectors well. Either it should be 405 // restricted to scalars or this node (and its handling) should be merged 406 // into it. 407 SIGN_EXTEND_VECTOR_INREG, 408 409 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 410 /// in-register zero-extension of the low lanes of an integer vector. The 411 /// result type must have fewer elements than the operand type, and those 412 /// elements must be larger integer types such that the total size of the 413 /// operand type and the result type match. Each of the low operand 414 /// elements is zero-extended into the corresponding, wider result 415 /// elements. 416 ZERO_EXTEND_VECTOR_INREG, 417 418 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 419 /// integer. 420 FP_TO_SINT, 421 FP_TO_UINT, 422 423 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 424 /// down to the precision of the destination VT. TRUNC is a flag, which is 425 /// always an integer that is zero or one. If TRUNC is 0, this is a 426 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 427 /// value of Y. 428 /// 429 /// The TRUNC = 1 case is used in cases where we know that the value will 430 /// not be modified by the node, because Y is not using any of the extra 431 /// precision of source type. This allows certain transformations like 432 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 433 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 434 FP_ROUND, 435 436 /// FLT_ROUNDS_ - Returns current rounding mode: 437 /// -1 Undefined 438 /// 0 Round to 0 439 /// 1 Round to nearest 440 /// 2 Round to +inf 441 /// 3 Round to -inf 442 FLT_ROUNDS_, 443 444 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 445 /// rounds it to a floating point value. It then promotes it and returns it 446 /// in a register of the same size. This operation effectively just 447 /// discards excess precision. The type to round down to is specified by 448 /// the VT operand, a VTSDNode. 449 FP_ROUND_INREG, 450 451 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 452 FP_EXTEND, 453 454 /// BITCAST - This operator converts between integer, vector and FP 455 /// values, as if the value was stored to memory with one type and loaded 456 /// from the same address with the other type (or equivalently for vector 457 /// format conversions, etc). The source and result are required to have 458 /// the same bit size (e.g. f32 <-> i32). This can also be used for 459 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 460 /// getNode(). 461 BITCAST, 462 463 /// ADDRSPACECAST - This operator converts between pointers of different 464 /// address spaces. 465 ADDRSPACECAST, 466 467 /// CONVERT_RNDSAT - This operator is used to support various conversions 468 /// between various types (float, signed, unsigned and vectors of those 469 /// types) with rounding and saturation. NOTE: Avoid using this operator as 470 /// most target don't support it and the operator might be removed in the 471 /// future. It takes the following arguments: 472 /// 0) value 473 /// 1) dest type (type to convert to) 474 /// 2) src type (type to convert from) 475 /// 3) rounding imm 476 /// 4) saturation imm 477 /// 5) ISD::CvtCode indicating the type of conversion to do 478 CONVERT_RNDSAT, 479 480 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 481 /// and truncation for half-precision (16 bit) floating numbers. These nodes 482 /// form a semi-softened interface for dealing with f16 (as an i16), which 483 /// is often a storage-only type but has native conversions. 484 FP16_TO_FP, FP_TO_FP16, 485 486 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 487 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 488 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 489 /// floating point operations. These are inspired by libm. 490 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 491 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 492 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 493 FMINNUM, FMAXNUM, 494 495 /// FSINCOS - Compute both fsin and fcos as a single operation. 496 FSINCOS, 497 498 /// LOAD and STORE have token chains as their first operand, then the same 499 /// operands as an LLVM load/store instruction, then an offset node that 500 /// is added / subtracted from the base pointer to form the address (for 501 /// indexed memory ops). 502 LOAD, STORE, 503 504 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 505 /// to a specified boundary. This node always has two return values: a new 506 /// stack pointer value and a chain. The first operand is the token chain, 507 /// the second is the number of bytes to allocate, and the third is the 508 /// alignment boundary. The size is guaranteed to be a multiple of the 509 /// stack alignment, and the alignment is guaranteed to be bigger than the 510 /// stack alignment (if required) or 0 to get standard stack alignment. 511 DYNAMIC_STACKALLOC, 512 513 /// Control flow instructions. These all have token chains. 514 515 /// BR - Unconditional branch. The first operand is the chain 516 /// operand, the second is the MBB to branch to. 517 BR, 518 519 /// BRIND - Indirect branch. The first operand is the chain, the second 520 /// is the value to branch to, which must be of the same type as the 521 /// target's pointer type. 522 BRIND, 523 524 /// BR_JT - Jumptable branch. The first operand is the chain, the second 525 /// is the jumptable index, the last one is the jumptable entry index. 526 BR_JT, 527 528 /// BRCOND - Conditional branch. The first operand is the chain, the 529 /// second is the condition, the third is the block to branch to if the 530 /// condition is true. If the type of the condition is not i1, then the 531 /// high bits must conform to getBooleanContents. 532 BRCOND, 533 534 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 535 /// that the condition is represented as condition code, and two nodes to 536 /// compare, rather than as a combined SetCC node. The operands in order 537 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 538 BR_CC, 539 540 /// INLINEASM - Represents an inline asm block. This node always has two 541 /// return values: a chain and a flag result. The inputs are as follows: 542 /// Operand #0 : Input chain. 543 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 544 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 545 /// Operand #3 : HasSideEffect, IsAlignStack bits. 546 /// After this, it is followed by a list of operands with this format: 547 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 548 /// of operands that follow, etc. See InlineAsm.h. 549 /// ... however many operands ... 550 /// Operand #last: Optional, an incoming flag. 551 /// 552 /// The variable width operands are required to represent target addressing 553 /// modes as a single "operand", even though they may have multiple 554 /// SDOperands. 555 INLINEASM, 556 557 /// EH_LABEL - Represents a label in mid basic block used to track 558 /// locations needed for debug and exception handling tables. These nodes 559 /// take a chain as input and return a chain. 560 EH_LABEL, 561 562 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 563 /// value, the same type as the pointer type for the system, and an output 564 /// chain. 565 STACKSAVE, 566 567 /// STACKRESTORE has two operands, an input chain and a pointer to restore 568 /// to it returns an output chain. 569 STACKRESTORE, 570 571 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 572 /// of a call sequence, and carry arbitrary information that target might 573 /// want to know. The first operand is a chain, the rest are specified by 574 /// the target and not touched by the DAG optimizers. 575 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 576 CALLSEQ_START, // Beginning of a call sequence 577 CALLSEQ_END, // End of a call sequence 578 579 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 580 /// and the alignment. It returns a pair of values: the vaarg value and a 581 /// new chain. 582 VAARG, 583 584 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 585 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 586 /// source. 587 VACOPY, 588 589 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 590 /// pointer, and a SRCVALUE. 591 VAEND, VASTART, 592 593 /// SRCVALUE - This is a node type that holds a Value* that is used to 594 /// make reference to a value in the LLVM IR. 595 SRCVALUE, 596 597 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 598 /// reference metadata in the IR. 599 MDNODE_SDNODE, 600 601 /// PCMARKER - This corresponds to the pcmarker intrinsic. 602 PCMARKER, 603 604 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 605 /// The only operand is a chain and a value and a chain are produced. The 606 /// value is the contents of the architecture specific cycle counter like 607 /// register (or other high accuracy low latency clock source) 608 READCYCLECOUNTER, 609 610 /// HANDLENODE node - Used as a handle for various purposes. 611 HANDLENODE, 612 613 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 614 /// takes as input a token chain, the pointer to the trampoline, the pointer 615 /// to the nested function, the pointer to pass for the 'nest' parameter, a 616 /// SRCVALUE for the trampoline and another for the nested function 617 /// (allowing targets to access the original Function*). 618 /// It produces a token chain as output. 619 INIT_TRAMPOLINE, 620 621 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 622 /// It takes a pointer to the trampoline and produces a (possibly) new 623 /// pointer to the same trampoline with platform-specific adjustments 624 /// applied. The pointer it returns points to an executable block of code. 625 ADJUST_TRAMPOLINE, 626 627 /// TRAP - Trapping instruction 628 TRAP, 629 630 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 631 DEBUGTRAP, 632 633 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 634 /// is the chain. The other operands are the address to prefetch, 635 /// read / write specifier, locality specifier and instruction / data cache 636 /// specifier. 637 PREFETCH, 638 639 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 640 /// This corresponds to the fence instruction. It takes an input chain, and 641 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 642 ATOMIC_FENCE, 643 644 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 645 /// This corresponds to "load atomic" instruction. 646 ATOMIC_LOAD, 647 648 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 649 /// This corresponds to "store atomic" instruction. 650 ATOMIC_STORE, 651 652 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 653 /// For double-word atomic operations: 654 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 655 /// swapLo, swapHi) 656 /// This corresponds to the cmpxchg instruction. 657 ATOMIC_CMP_SWAP, 658 659 /// Val, Success, OUTCHAIN 660 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 661 /// N.b. this is still a strong cmpxchg operation, so 662 /// Success == "Val == cmp". 663 ATOMIC_CMP_SWAP_WITH_SUCCESS, 664 665 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 666 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 667 /// For double-word atomic operations: 668 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 669 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 670 /// These correspond to the atomicrmw instruction. 671 ATOMIC_SWAP, 672 ATOMIC_LOAD_ADD, 673 ATOMIC_LOAD_SUB, 674 ATOMIC_LOAD_AND, 675 ATOMIC_LOAD_OR, 676 ATOMIC_LOAD_XOR, 677 ATOMIC_LOAD_NAND, 678 ATOMIC_LOAD_MIN, 679 ATOMIC_LOAD_MAX, 680 ATOMIC_LOAD_UMIN, 681 ATOMIC_LOAD_UMAX, 682 683 // Masked load and store 684 MLOAD, MSTORE, 685 686 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 687 /// is the chain and the second operand is the alloca pointer. 688 LIFETIME_START, LIFETIME_END, 689 690 /// BUILTIN_OP_END - This must be the last enum value in this list. 691 /// The target-specific pre-isel opcode values start here. 692 BUILTIN_OP_END 693 }; 694 695 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 696 /// which do not reference a specific memory location should be less than 697 /// this value. Those that do must not be less than this value, and can 698 /// be used with SelectionDAG::getMemIntrinsicNode. 699 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+180; 700 701 //===--------------------------------------------------------------------===// 702 /// MemIndexedMode enum - This enum defines the load / store indexed 703 /// addressing modes. 704 /// 705 /// UNINDEXED "Normal" load / store. The effective address is already 706 /// computed and is available in the base pointer. The offset 707 /// operand is always undefined. In addition to producing a 708 /// chain, an unindexed load produces one value (result of the 709 /// load); an unindexed store does not produce a value. 710 /// 711 /// PRE_INC Similar to the unindexed mode where the effective address is 712 /// PRE_DEC the value of the base pointer add / subtract the offset. 713 /// It considers the computation as being folded into the load / 714 /// store operation (i.e. the load / store does the address 715 /// computation as well as performing the memory transaction). 716 /// The base operand is always undefined. In addition to 717 /// producing a chain, pre-indexed load produces two values 718 /// (result of the load and the result of the address 719 /// computation); a pre-indexed store produces one value (result 720 /// of the address computation). 721 /// 722 /// POST_INC The effective address is the value of the base pointer. The 723 /// POST_DEC value of the offset operand is then added to / subtracted 724 /// from the base after memory transaction. In addition to 725 /// producing a chain, post-indexed load produces two values 726 /// (the result of the load and the result of the base +/- offset 727 /// computation); a post-indexed store produces one value (the 728 /// the result of the base +/- offset computation). 729 enum MemIndexedMode { 730 UNINDEXED = 0, 731 PRE_INC, 732 PRE_DEC, 733 POST_INC, 734 POST_DEC, 735 LAST_INDEXED_MODE 736 }; 737 738 //===--------------------------------------------------------------------===// 739 /// LoadExtType enum - This enum defines the three variants of LOADEXT 740 /// (load with extension). 741 /// 742 /// SEXTLOAD loads the integer operand and sign extends it to a larger 743 /// integer result type. 744 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 745 /// integer result type. 746 /// EXTLOAD is used for two things: floating point extending loads and 747 /// integer extending loads [the top bits are undefined]. 748 enum LoadExtType { 749 NON_EXTLOAD = 0, 750 EXTLOAD, 751 SEXTLOAD, 752 ZEXTLOAD, 753 LAST_LOADEXT_TYPE 754 }; 755 756 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 757 758 //===--------------------------------------------------------------------===// 759 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 760 /// below work out, when considering SETFALSE (something that never exists 761 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 762 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 763 /// to. If the "N" column is 1, the result of the comparison is undefined if 764 /// the input is a NAN. 765 /// 766 /// All of these (except for the 'always folded ops') should be handled for 767 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 768 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 769 /// 770 /// Note that these are laid out in a specific order to allow bit-twiddling 771 /// to transform conditions. 772 enum CondCode { 773 // Opcode N U L G E Intuitive operation 774 SETFALSE, // 0 0 0 0 Always false (always folded) 775 SETOEQ, // 0 0 0 1 True if ordered and equal 776 SETOGT, // 0 0 1 0 True if ordered and greater than 777 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 778 SETOLT, // 0 1 0 0 True if ordered and less than 779 SETOLE, // 0 1 0 1 True if ordered and less than or equal 780 SETONE, // 0 1 1 0 True if ordered and operands are unequal 781 SETO, // 0 1 1 1 True if ordered (no nans) 782 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 783 SETUEQ, // 1 0 0 1 True if unordered or equal 784 SETUGT, // 1 0 1 0 True if unordered or greater than 785 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 786 SETULT, // 1 1 0 0 True if unordered or less than 787 SETULE, // 1 1 0 1 True if unordered, less than, or equal 788 SETUNE, // 1 1 1 0 True if unordered or not equal 789 SETTRUE, // 1 1 1 1 Always true (always folded) 790 // Don't care operations: undefined if the input is a nan. 791 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 792 SETEQ, // 1 X 0 0 1 True if equal 793 SETGT, // 1 X 0 1 0 True if greater than 794 SETGE, // 1 X 0 1 1 True if greater than or equal 795 SETLT, // 1 X 1 0 0 True if less than 796 SETLE, // 1 X 1 0 1 True if less than or equal 797 SETNE, // 1 X 1 1 0 True if not equal 798 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 799 800 SETCC_INVALID // Marker value. 801 }; 802 803 /// isSignedIntSetCC - Return true if this is a setcc instruction that 804 /// performs a signed comparison when used with integer operands. isSignedIntSetCC(CondCode Code)805 inline bool isSignedIntSetCC(CondCode Code) { 806 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 807 } 808 809 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 810 /// performs an unsigned comparison when used with integer operands. isUnsignedIntSetCC(CondCode Code)811 inline bool isUnsignedIntSetCC(CondCode Code) { 812 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 813 } 814 815 /// isTrueWhenEqual - Return true if the specified condition returns true if 816 /// the two operands to the condition are equal. Note that if one of the two 817 /// operands is a NaN, this value is meaningless. isTrueWhenEqual(CondCode Cond)818 inline bool isTrueWhenEqual(CondCode Cond) { 819 return ((int)Cond & 1) != 0; 820 } 821 822 /// getUnorderedFlavor - This function returns 0 if the condition is always 823 /// false if an operand is a NaN, 1 if the condition is always true if the 824 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 825 /// NaN. getUnorderedFlavor(CondCode Cond)826 inline unsigned getUnorderedFlavor(CondCode Cond) { 827 return ((int)Cond >> 3) & 3; 828 } 829 830 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 831 /// 'op' is a valid SetCC operation. 832 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 833 834 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 835 /// when given the operation for (X op Y). 836 CondCode getSetCCSwappedOperands(CondCode Operation); 837 838 /// getSetCCOrOperation - Return the result of a logical OR between different 839 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 840 /// function returns SETCC_INVALID if it is not possible to represent the 841 /// resultant comparison. 842 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 843 844 /// getSetCCAndOperation - Return the result of a logical AND between 845 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 846 /// function returns SETCC_INVALID if it is not possible to represent the 847 /// resultant comparison. 848 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 849 850 //===--------------------------------------------------------------------===// 851 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 852 /// supports. 853 enum CvtCode { 854 CVT_FF, /// Float from Float 855 CVT_FS, /// Float from Signed 856 CVT_FU, /// Float from Unsigned 857 CVT_SF, /// Signed from Float 858 CVT_UF, /// Unsigned from Float 859 CVT_SS, /// Signed from Signed 860 CVT_SU, /// Signed from Unsigned 861 CVT_US, /// Unsigned from Signed 862 CVT_UU, /// Unsigned from Unsigned 863 CVT_INVALID /// Marker - Invalid opcode 864 }; 865 866 } // end llvm::ISD namespace 867 868 } // end llvm namespace 869 870 #endif 871