1 /* $OpenBSD: eapreg.h,v 1.4 2012/03/30 08:18:19 ratchov Exp $ */ 2 /* $NetBSD: eapreg.h,v 1.10 2005/02/13 23:58:38 fredb Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson <augustss@netbsd.org> and Charles M. Hannum. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * ES1370/ES1371/ES1373 registers 35 */ 36 37 #define EAP_ICSC 0x00 /* interrupt / chip select control */ 38 #define EAP_SERR_DISABLE 0x00000001 39 #define EAP_CDC_EN 0x00000002 40 #define EAP_JYSTK_EN 0x00000004 41 #define EAP_UART_EN 0x00000008 42 #define EAP_ADC_EN 0x00000010 43 #define EAP_DAC2_EN 0x00000020 44 #define EAP_DAC1_EN 0x00000040 45 #define EAP_BREQ 0x00000080 46 #define EAP_XTCL0 0x00000100 47 #define EAP_M_CB 0x00000200 48 #define EAP_CCB_INTRM 0x00000400 49 #define EAP_DAC_SYNC 0x00000800 50 #define EAP_WTSRSEL 0x00003000 51 #define EAP_WTSRSEL_5 0x00000000 52 #define EAP_WTSRSEL_11 0x00001000 53 #define EAP_WTSRSEL_22 0x00002000 54 #define EAP_WTSRSEL_44 0x00003000 55 #define EAP_M_SBB 0x00004000 56 #define E1371_SYNC_RES 0x00004000 57 #define EAP_MSFMTSEL 0x00008000 58 #define EAP_SET_PCLKDIV(n) (((n)&0x1fff)<<16) 59 #define EAP_GET_PCLKDIV(n) (((n)>>16)&0x1fff) 60 #define EAP_PCLKBITS 0x1fff0000 61 #define EAP_XTCL1 0x40000000 62 #define EAP_ADC_STOP 0x80000000 63 64 #define EAP_ICSS 0x04 /* interrupt / chip select status */ 65 /* on the 5880 control / status */ 66 #define EAP_I_ADC 0x00000001 67 #define EAP_I_DAC2 0x00000002 68 #define EAP_I_DAC1 0x00000004 69 #define EAP_I_UART 0x00000008 70 #define EAP_I_MCCB 0x00000010 71 #define EAP_VC 0x00000060 72 #define EAP_CWRIP 0x00000100 73 #define EAP_CBUSY 0x00000200 74 #define EAP_CSTAT 0x00000400 75 #define EAP_CT5880_AC97_RESET 0x20000000 76 #define EAP_INTR 0x80000000 77 78 #define EAP_UART_DATA 0x08 79 #define EAP_UART_STATUS 0x09 80 #define EAP_US_RXRDY 0x01 81 #define EAP_US_TXRDY 0x02 82 #define EAP_US_TXINT 0x04 83 #define EAP_US_RXINT 0x80 84 #define EAP_UART_CONTROL 0x09 85 #define EAP_UC_CNTRL 0x03 86 #define EAP_UC_TXINTEN 0x20 87 #define EAP_UC_RXINTEN 0x80 88 #define EAP_MEMPAGE 0x0c 89 #define EAP_CODEC 0x10 90 #define EAP_SET_CODEC(a,d) (((a)<<8) | (d)) 91 92 /* 93 * ES1371/ES1373 registers 94 */ 95 96 #define E1371_CODEC 0x14 97 #define E1371_CODEC_VALID 0x80000000 98 #define E1371_CODEC_WIP 0x40000000 99 #define E1371_CODEC_READ 0x00800000 100 #define E1371_SET_CODEC(a,d) (((a)<<16) | (d)) 101 102 #define E1371_SRC 0x10 103 #define E1371_SRC_RAMWE 0x01000000 104 #define E1371_SRC_RBUSY 0x00800000 105 #define E1371_SRC_DISABLE 0x00400000 106 #define E1371_SRC_DISP1 0x00200000 107 #define E1371_SRC_DISP2 0x00100000 108 #define E1371_SRC_DISREC 0x00080000 109 #define E1371_SRC_ADDR(a) ((a)<<25) 110 #define E1371_SRC_DATA(d) (d) 111 #define E1371_SRC_DATAMASK 0x0000ffff 112 #define E1371_SRC_CTLMASK (E1371_SRC_DISABLE | E1371_SRC_DISP1 | \ 113 E1371_SRC_DISP2 | E1371_SRC_DISREC) 114 #define E1371_SRC_STATE_MASK 0x00870000 115 #define E1371_SRC_STATE_OK 0x00010000 116 117 #define E1371_LEGACY 0x18 118 119 /* 120 * ES1371/ES1373 sample rate converter registers 121 */ 122 123 #define ESRC_ADC 0x78 124 #define ESRC_DAC1 0x74 125 #define ESRC_DAC2 0x70 126 #define ESRC_ADC_VOLL 0x6c 127 #define ESRC_ADC_VOLR 0x6d 128 #define ESRC_DAC1_VOLL 0x7c 129 #define ESRC_DAC1_VOLR 0x7d 130 #define ESRC_DAC2_VOLL 0x7e 131 #define ESRC_DAC2_VOLR 0x7f 132 #define ESRC_TRUNC_N 0x00 133 #define ESRC_IREGS 0x01 134 #define ESRC_ACF 0x02 135 #define ESRC_VFF 0x03 136 #define ESRC_SET_TRUNC(n) ((n)<<9) 137 #define ESRC_SET_N(n) ((n)<<4) 138 #define ESRC_SMF 0x8000 139 #define ESRC_SET_VFI(n) ((n)<<10) 140 #define ESRC_SET_ACI(n) (n) 141 #define ESRC_SET_ADC_VOL(n) ((n)<<8) 142 #define ESRC_SET_DAC_VOLI(n) ((n)<<12) 143 #define ESRC_SET_DAC_VOLF(n) (n) 144 #define SRC_MAGIC ((1<15)|(1<<13)|(1<<11)|(1<<9)) 145 146 #define EAP_SIC 0x20 147 #define EAP_P1_S_MB 0x00000001 148 #define EAP_P1_S_EB 0x00000002 149 #define EAP_P2_S_MB 0x00000004 150 #define EAP_P2_S_EB 0x00000008 151 #define EAP_R1_S_MB 0x00000010 152 #define EAP_R1_S_EB 0x00000020 153 #define EAP_P2_DAC_SEN 0x00000040 154 #define EAP_P1_SCT_RLD 0x00000080 155 #define EAP_P1_INTR_EN 0x00000100 156 #define EAP_P2_INTR_EN 0x00000200 157 #define EAP_R1_INTR_EN 0x00000400 158 #define EAP_P1_PAUSE 0x00000800 159 #define EAP_P2_PAUSE 0x00001000 160 #define EAP_P1_LOOP_SEL 0x00002000 161 #define EAP_P2_LOOP_SEL 0x00004000 162 #define EAP_R1_LOOP_SEL 0x00008000 163 #define EAP_SET_P2_ST_INC(i) ((i) << 16) 164 #define EAP_SET_P2_END_INC(i) ((i) << 19) 165 #define EAP_INC_BITS 0x003f0000 166 167 #define EAP_DAC1_CSR 0x24 168 #define EAP_DAC2_CSR 0x28 169 #define EAP_ADC_CSR 0x2c 170 #define EAP_GET_CURRSAMP(r) ((r) >> 16) 171 172 #define EAP_DAC_PAGE 0xc 173 #define EAP_ADC_PAGE 0xd 174 #define EAP_UART_PAGE1 0xe 175 #define EAP_UART_PAGE2 0xf 176 177 #define EAP_DAC1_ADDR 0x30 178 #define EAP_DAC1_SIZE 0x34 179 #define EAP_DAC2_ADDR 0x38 180 #define EAP_DAC2_SIZE 0x3c 181 #define EAP_ADC_ADDR 0x30 182 #define EAP_ADC_SIZE 0x34 183 #define EAP_SET_SIZE(c,s) (((c)<<16) | (s)) 184 185 #define EAP_READ_TIMEOUT 5000 186 #define EAP_WRITE_TIMEOUT 5000 187 188 189 #define EAP_XTAL_FREQ 1411200 /* 22.5792 / 16 MHz */ 190 191 /* AK4531 registers */ 192 #define AK_MASTER_L 0x00 193 #define AK_MASTER_R 0x01 194 #define AK_VOICE_L 0x02 195 #define AK_VOICE_R 0x03 196 #define AK_FM_L 0x04 197 #define AK_FM_R 0x05 198 #define AK_CD_L 0x06 199 #define AK_CD_R 0x07 200 #define AK_LINE_L 0x08 201 #define AK_LINE_R 0x09 202 #define AK_AUX_L 0x0a 203 #define AK_AUX_R 0x0b 204 #define AK_MONO1 0x0c 205 #define AK_MONO2 0x0d 206 #define AK_MIC 0x0e 207 #define AK_MONO 0x0f 208 #define AK_OUT_MIXER1 0x10 209 #define AK_M_FM_L 0x40 210 #define AK_M_FM_R 0x20 211 #define AK_M_LINE_L 0x10 212 #define AK_M_LINE_R 0x08 213 #define AK_M_CD_L 0x04 214 #define AK_M_CD_R 0x02 215 #define AK_M_MIC 0x01 216 #define AK_OUT_MIXER2 0x11 217 #define AK_M_AUX_L 0x20 218 #define AK_M_AUX_R 0x10 219 #define AK_M_VOICE_L 0x08 220 #define AK_M_VOICE_R 0x04 221 #define AK_M_MONO2 0x02 222 #define AK_M_MONO1 0x01 223 #define AK_IN_MIXER1_L 0x12 224 #define AK_IN_MIXER1_R 0x13 225 #define AK_IN_MIXER2_L 0x14 226 #define AK_IN_MIXER2_R 0x15 227 #define AK_M_TMIC 0x80 228 #define AK_M_TMONO1 0x40 229 #define AK_M_TMONO2 0x20 230 #define AK_M2_AUX_L 0x10 231 #define AK_M2_AUX_R 0x08 232 #define AK_M_VOICE 0x04 233 #define AK_M2_MONO2 0x02 234 #define AK_M2_MONO1 0x01 235 #define AK_RESET 0x16 236 #define AK_PD 0x02 237 #define AK_NRST 0x01 238 #define AK_CS 0x17 239 #define AK_ADSEL 0x18 240 #define AK_MGAIN 0x19 241 #define AK_NPORTS 0x20 242 243 /* Not sensical for AC97? */ 244 #define VOL_TO_ATT5(v) (0x1f - ((v) >> 3)) 245 #define VOL_TO_GAIN5(v) VOL_TO_ATT5(v) 246 #define ATT5_TO_VOL(v) ((0x1f - (v)) << 3) 247 #define GAIN5_TO_VOL(v) ATT5_TO_VOL(v) 248 #define VOL_0DB 200 249 250 /* Futzable parms */ 251 #define EAP_MASTER_VOL 0 252 #define EAP_VOICE_VOL 1 253 #define EAP_FM_VOL 2 254 #define EAP_VIDEO_VOL 2 /* ES1371 */ 255 #define EAP_CD_VOL 3 256 #define EAP_LINE_VOL 4 257 #define EAP_AUX_VOL 5 258 #define EAP_MIC_VOL 6 259 #define EAP_RECORD_SOURCE 7 260 #define EAP_INPUT_SOURCE 8 261 #define EAP_MIC_PREAMP 9 262 #define EAP_OUTPUT_CLASS 10 263 #define EAP_RECORD_CLASS 11 264 #define EAP_INPUT_CLASS 12 265 266 #define EAP_EV1938_A 0x00 267 #define EAP_ES1371_A 0x02 268 #define EAP_CT5880_C 0x02 269 #define EAP_CT5880_D 0x03 270 #define EAP_ES1373_A 0x04 271 #define EAP_ES1373_B 0x06 272 #define EAP_CT5880_A 0x07 273 #define EAP_ES1373_8 0x08 274 #define EAP_ES1371_B 0x09 275