1 /* $NetBSD: elroyreg.h,v 1.1 2014/02/24 07:23:42 skrll Exp $ */ 2 3 /* $OpenBSD: elroyreg.h,v 1.1 2007/05/21 22:43:38 kettenis Exp $ */ 4 5 /* 6 * Copyright (c) 2005 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 18 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 19 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 struct elroy_regs { 23 /* std PCI bridge header */ 24 uint32_t pci_id; /* 0x000 rw PCI_ID */ 25 uint32_t pci_cmdstat; /* 0x004 rw PCI_COMMAND_STATUS_REG */ 26 uint32_t pci_class; /* 0x008 ro PCI_CLASS_REG */ 27 uint32_t pci_bhlc; /* 0x00c rw PCI_BHLC_REG */ 28 uint32_t res0[0x30/4]; /* 0x010 */ 29 30 /* HW Bridge registers */ 31 uint32_t pci_conf_addr; /* 0x040 rw config space address */ 32 uint32_t pad040; 33 uint32_t pci_conf_data; /* 0x048 rw config space data */ 34 uint32_t pad048; 35 uint64_t elroy_mtlt; /* 0x050 */ 36 uint32_t busnum; /* 0x058 bus number/scratch */ 37 uint32_t par058; 38 uint64_t res1; /* 0x060 */ 39 uint64_t rope; /* 0x068 rope parity, loopback */ 40 uint64_t err_addr; /* 0x070 error log: address */ 41 uint64_t suspend; /* 0x078 rw suspend control */ 42 uint32_t arb_mask; /* 0x080 rw arbitration mask */ 43 uint32_t pad080; 44 #define ELROY_ARB_ENABLE 0x01 /* enable arbitration */ 45 #define ELROY_ARB_PCIDEVA 0x02 /* PCI device A allow */ 46 #define ELROY_ARB_PCIDEVB 0x04 /* PCI device A allow */ 47 #define ELROY_ARB_PCIDEVC 0x08 /* PCI device A allow */ 48 #define ELROY_ARB_PCIDEVD 0x10 /* PCI device A allow */ 49 #define ELROY_ARB_PCIDEVE 0x20 /* PCI device A allow */ 50 #define ELROY_ARB_PCIDEVF 0x40 /* PCI device A allow */ 51 #define ELROY_ARB_PCIDEVG 0x80 /* PCI device A allow */ 52 uint64_t arb_pri; /* 0x088 arbitration priority */ 53 uint64_t arb_mode; /* 0x090 arbitration mode */ 54 uint64_t mtlt; /* 0x098 */ 55 uint64_t res2[12]; /* 0x0a0 */ 56 uint64_t mod_info; /* 0x100 */ 57 uint32_t control; /* 0x108 */ 58 #define ELROY_CONTROL_RF 0x01 /* reset pci */ 59 #define ELROY_CONTROL_VE 0x08 /* VGA enable */ 60 #define ELROY_CONTROL_CL 0x10 /* clear error log */ 61 #define ELROY_CONTROL_CE 0x20 /* clear error log enable */ 62 #define ELROY_CONTROL_HF 0x40 /* hard fail enable */ 63 uint32_t status; /* 0x10c */ 64 #define ELROY_STATUS_RC 0x01 /* reset complete */ 65 #define ELROY_STATUS_BITS "\020\01RC" 66 uint64_t res3[30]; /* 0x110 */ 67 uint64_t lmmio_base; /* 0x200 */ 68 uint64_t lmmio_mask; /* 0x208 */ 69 uint64_t gmmio_base; /* 0x210 */ 70 uint64_t gmmio_mask; /* 0x218 */ 71 uint64_t wlmmio_base; /* 0x220 */ 72 uint64_t wlmmio_mask; /* 0x228 */ 73 uint64_t wgmmio_base; /* 0x230 */ 74 uint64_t wgmmio_mask; /* 0x238 */ 75 uint32_t io_base; /* 0x240 */ 76 uint32_t pad240; 77 uint32_t io_mask; /* 0x248 */ 78 uint32_t pad248; 79 uint32_t res4[4]; /* 0x250 */ 80 uint32_t eio_base; /* 0x260 */ 81 uint32_t pad260; 82 uint32_t eio_mask; /* 0x268 */ 83 uint32_t pad268; 84 #define ELROY_BASE_RE 0x01 /* range enable */ 85 uint64_t res5; /* 0x270 */ 86 uint64_t dmac_ctrl; /* 0x278 DMA connection control */ 87 uint64_t res6[16]; /* 0x280 */ 88 uint32_t ibase; /* 0x300 */ 89 uint32_t pad300; 90 uint32_t imask; /* 0x308 */ 91 uint32_t pad308; 92 uint64_t hint_cfg; /* 0x310 */ 93 uint64_t res7[13]; /* 0x318 */ 94 uint64_t hints[14]; /* 0x380 */ 95 uint64_t res8[2]; /* 0x3f0 */ 96 uint64_t res9[64]; /* 0x400 */ 97 uint64_t pad0; /* 0x600 */ 98 uint64_t pci_drive; /* 0x608 */ 99 uint64_t rope_cfg; /* 0x610 */ 100 uint64_t clk_ctl; /* 0x618 */ 101 uint32_t pad1; /* 0x620 */ 102 uint32_t res10[23]; /* 0x624 */ 103 uint32_t err_cfg; /* 0x680 error config */ 104 uint32_t pad680; 105 #define ELROY_ERRCFG_PW 0x01 /* PIO writes parity errors */ 106 #define ELROY_ERRCFG_PR 0x02 /* PIO reads parity errors */ 107 #define ELROY_ERRCFG_DW 0x04 /* DMA writes parity errors */ 108 #define ELROY_ERRCFG_DR 0x08 /* DMA reads parity errors */ 109 #define ELROY_ERRCFG_CM 0x10 /* no fatal on config space */ 110 #define ELROY_ERRCFG_SMART 0x20 /* smart bus mode */ 111 uint64_t err_stat; /* 0x688 error status */ 112 uint64_t err_mid; /* 0x690 error log: master id */ 113 uint64_t rope_estat; /* 0x698 rope error status */ 114 uint64_t rope_eclr; /* 0x6a0 rope error clear */ 115 uint64_t res11[42]; /* 0x6a8 */ 116 uint64_t regbus; /* 0x7f8 reads 0x3ff */ 117 uint32_t apic_addr; /* 0x800 APIC address register */ 118 uint32_t pad800; 119 uint64_t res12; 120 uint32_t apic_data; /* 0x810 APIC data register */ 121 uint32_t pad808; 122 uint64_t res13[5]; 123 uint32_t apic_eoi; /* 0x840 APIC interrupt ack */ 124 uint32_t pad840; 125 uint32_t apic_softint; /* 0x850 write generates softint */ 126 uint32_t pad850; 127 uint64_t res14[123]; /* 0x858 */ 128 /*0x1000 */ 129 }; 130 131 /* APIC registers */ 132 #define APIC_VERSION 0x01 133 #define APIC_VERSION_MASK 0xff 134 #define APIC_VERSION_NENT 0xff0000 135 #define APIC_VERSION_NENT_SHIFT 16 136 #define APIC_ENT0(i) (0x10 + (i)*2) 137 #define APIC_ENT0_VEC 0x000ff 138 #define APIC_ENT0_MOD 0x00700 /* delivery mode */ 139 #define APIC_ENT0_FXD 0x00000 140 #define APIC_ENT0_RDR 0x00100 141 #define APIC_ENT0_PMI 0x00200 142 #define APIC_ENT0_NMI 0x00400 143 #define APIC_ENT0_INI 0x00500 144 #define APIC_ENT0_EXT 0x00700 145 #define APIC_ENT0_PEND 0x01000 /* int is pending */ 146 #define APIC_ENT0_LOW 0x02000 /* polarity */ 147 #define APIC_ENT0_LEV 0x08000 /* edge/level */ 148 #define APIC_ENT0_MASK 0x10000 /* mask int */ 149 #define APIC_ENT1(i) (0x11 + (i)*2) 150