1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _ENA_ADMIN_H_
35 #define _ENA_ADMIN_H_
36
37 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
38 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
39
40 #define ENA_ADMIN_RSS_KEY_PARTS 10
41
42 #define ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK 0x3F
43 #define ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK 0x1F
44
45 /* customer metrics - in correlation with
46 * ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK
47 */
48 enum ena_admin_customer_metrics_id {
49 ENA_ADMIN_BW_IN_ALLOWANCE_EXCEEDED = 0,
50 ENA_ADMIN_BW_OUT_ALLOWANCE_EXCEEDED = 1,
51 ENA_ADMIN_PPS_ALLOWANCE_EXCEEDED = 2,
52 ENA_ADMIN_CONNTRACK_ALLOWANCE_EXCEEDED = 3,
53 ENA_ADMIN_LINKLOCAL_ALLOWANCE_EXCEEDED = 4,
54 ENA_ADMIN_CONNTRACK_ALLOWANCE_AVAILABLE = 5,
55 };
56
57 enum ena_admin_aq_opcode {
58 ENA_ADMIN_CREATE_SQ = 1,
59 ENA_ADMIN_DESTROY_SQ = 2,
60 ENA_ADMIN_CREATE_CQ = 3,
61 ENA_ADMIN_DESTROY_CQ = 4,
62 ENA_ADMIN_GET_FEATURE = 8,
63 ENA_ADMIN_SET_FEATURE = 9,
64 ENA_ADMIN_GET_STATS = 11,
65 };
66
67 enum ena_admin_aq_completion_status {
68 ENA_ADMIN_SUCCESS = 0,
69 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
70 ENA_ADMIN_BAD_OPCODE = 2,
71 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
72 ENA_ADMIN_MALFORMED_REQUEST = 4,
73 /* Additional status is provided in ACQ entry extended_status */
74 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
75 ENA_ADMIN_UNKNOWN_ERROR = 6,
76 ENA_ADMIN_RESOURCE_BUSY = 7,
77 };
78
79 /* subcommands for the set/get feature admin commands */
80 enum ena_admin_aq_feature_id {
81 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
82 ENA_ADMIN_MAX_QUEUES_NUM = 2,
83 ENA_ADMIN_HW_HINTS = 3,
84 ENA_ADMIN_LLQ = 4,
85 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
86 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
87 ENA_ADMIN_MAX_QUEUES_EXT = 7,
88 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
89 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
90 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
91 ENA_ADMIN_MTU = 14,
92 ENA_ADMIN_RSS_HASH_INPUT = 18,
93 ENA_ADMIN_INTERRUPT_MODERATION = 20,
94 ENA_ADMIN_AENQ_CONFIG = 26,
95 ENA_ADMIN_LINK_CONFIG = 27,
96 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
97 ENA_ADMIN_PHC_CONFIG = 29,
98 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
99 };
100
101 /* device capabilities */
102 enum ena_admin_aq_caps_id {
103 ENA_ADMIN_ENI_STATS = 0,
104 /* ENA SRD customer metrics */
105 ENA_ADMIN_ENA_SRD_INFO = 1,
106 ENA_ADMIN_CUSTOMER_METRICS = 2,
107 };
108
109 enum ena_admin_placement_policy_type {
110 /* descriptors and headers are in host memory */
111 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
112 /* descriptors and headers are in device memory (a.k.a Low Latency
113 * Queue)
114 */
115 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
116 };
117
118 enum ena_admin_link_types {
119 ENA_ADMIN_LINK_SPEED_1G = 0x1,
120 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
121 ENA_ADMIN_LINK_SPEED_5G = 0x4,
122 ENA_ADMIN_LINK_SPEED_10G = 0x8,
123 ENA_ADMIN_LINK_SPEED_25G = 0x10,
124 ENA_ADMIN_LINK_SPEED_40G = 0x20,
125 ENA_ADMIN_LINK_SPEED_50G = 0x40,
126 ENA_ADMIN_LINK_SPEED_100G = 0x80,
127 ENA_ADMIN_LINK_SPEED_200G = 0x100,
128 ENA_ADMIN_LINK_SPEED_400G = 0x200,
129 };
130
131 enum ena_admin_completion_policy_type {
132 /* completion queue entry for each sq descriptor */
133 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
134 /* completion queue entry upon request in sq descriptor */
135 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
136 /* current queue head pointer is updated in OS memory upon sq
137 * descriptor request
138 */
139 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
140 /* current queue head pointer is updated in OS memory for each sq
141 * descriptor
142 */
143 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
144 };
145
146 /* basic stats return ena_admin_basic_stats while extanded stats return a
147 * buffer (string format) with additional statistics per queue and per
148 * device id
149 */
150 enum ena_admin_get_stats_type {
151 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
152 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
153 /* extra HW stats for specific network interface */
154 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
155 /* extra HW stats for ENA SRD */
156 ENA_ADMIN_GET_STATS_TYPE_ENA_SRD = 3,
157 ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS = 4,
158
159 };
160
161 enum ena_admin_get_stats_scope {
162 ENA_ADMIN_SPECIFIC_QUEUE = 0,
163 ENA_ADMIN_ETH_TRAFFIC = 1,
164 };
165
166 enum ena_admin_get_phc_type {
167 ENA_ADMIN_PHC_TYPE_READLESS = 0,
168 };
169
170 /* ENA SRD configuration for ENI */
171 enum ena_admin_ena_srd_flags {
172 /* Feature enabled */
173 ENA_ADMIN_ENA_SRD_ENABLED = BIT(0),
174 /* UDP support enabled */
175 ENA_ADMIN_ENA_SRD_UDP_ENABLED = BIT(1),
176 /* Bypass Rx UDP ordering */
177 ENA_ADMIN_ENA_SRD_UDP_ORDERING_BYPASS_ENABLED = BIT(2),
178 };
179
180 struct ena_admin_aq_common_desc {
181 /* 11:0 : command_id
182 * 15:12 : reserved12
183 */
184 uint16_t command_id;
185
186 /* as appears in ena_admin_aq_opcode */
187 uint8_t opcode;
188
189 /* 0 : phase
190 * 1 : ctrl_data - control buffer address valid
191 * 2 : ctrl_data_indirect - control buffer address
192 * points to list of pages with addresses of control
193 * buffers
194 * 7:3 : reserved3
195 */
196 uint8_t flags;
197 };
198
199 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
200 * page list chunk. Used also at the end of indirect mode page list chunks,
201 * for chaining.
202 */
203 struct ena_admin_ctrl_buff_info {
204 uint32_t length;
205
206 struct ena_common_mem_addr address;
207 };
208
209 struct ena_admin_sq {
210 uint16_t sq_idx;
211
212 /* 4:0 : reserved
213 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
214 */
215 uint8_t sq_identity;
216
217 uint8_t reserved1;
218 };
219
220 struct ena_admin_aq_entry {
221 struct ena_admin_aq_common_desc aq_common_descriptor;
222
223 union {
224 uint32_t inline_data_w1[3];
225
226 struct ena_admin_ctrl_buff_info control_buffer;
227 } u;
228
229 uint32_t inline_data_w4[12];
230 };
231
232 struct ena_admin_acq_common_desc {
233 /* command identifier to associate it with the aq descriptor
234 * 11:0 : command_id
235 * 15:12 : reserved12
236 */
237 uint16_t command;
238
239 uint8_t status;
240
241 /* 0 : phase
242 * 7:1 : reserved1
243 */
244 uint8_t flags;
245
246 uint16_t extended_status;
247
248 /* indicates to the driver which AQ entry has been consumed by the
249 * device and could be reused
250 */
251 uint16_t sq_head_indx;
252 };
253
254 struct ena_admin_acq_entry {
255 struct ena_admin_acq_common_desc acq_common_descriptor;
256
257 uint32_t response_specific_data[14];
258 };
259
260 struct ena_admin_aq_create_sq_cmd {
261 struct ena_admin_aq_common_desc aq_common_descriptor;
262
263 /* 4:0 : reserved0_w1
264 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
265 */
266 uint8_t sq_identity;
267
268 uint8_t reserved8_w1;
269
270 /* 3:0 : placement_policy - Describing where the SQ
271 * descriptor ring and the SQ packet headers reside:
272 * 0x1 - descriptors and headers are in OS memory,
273 * 0x3 - descriptors and headers in device memory
274 * (a.k.a Low Latency Queue)
275 * 6:4 : completion_policy - Describing what policy
276 * to use for generation completion entry (cqe) in
277 * the CQ associated with this SQ: 0x0 - cqe for each
278 * sq descriptor, 0x1 - cqe upon request in sq
279 * descriptor, 0x2 - current queue head pointer is
280 * updated in OS memory upon sq descriptor request
281 * 0x3 - current queue head pointer is updated in OS
282 * memory for each sq descriptor
283 * 7 : reserved15_w1
284 */
285 uint8_t sq_caps_2;
286
287 /* 0 : is_physically_contiguous - Described if the
288 * queue ring memory is allocated in physical
289 * contiguous pages or split.
290 * 7:1 : reserved17_w1
291 */
292 uint8_t sq_caps_3;
293
294 /* associated completion queue id. This CQ must be created prior to SQ
295 * creation
296 */
297 uint16_t cq_idx;
298
299 /* submission queue depth in entries */
300 uint16_t sq_depth;
301
302 /* SQ physical base address in OS memory. This field should not be
303 * used for Low Latency queues. Has to be page aligned.
304 */
305 struct ena_common_mem_addr sq_ba;
306
307 /* specifies queue head writeback location in OS memory. Valid if
308 * completion_policy is set to completion_policy_head_on_demand or
309 * completion_policy_head. Has to be cache aligned
310 */
311 struct ena_common_mem_addr sq_head_writeback;
312
313 uint32_t reserved0_w7;
314
315 uint32_t reserved0_w8;
316 };
317
318 enum ena_admin_sq_direction {
319 ENA_ADMIN_SQ_DIRECTION_TX = 1,
320 ENA_ADMIN_SQ_DIRECTION_RX = 2,
321 };
322
323 struct ena_admin_acq_create_sq_resp_desc {
324 struct ena_admin_acq_common_desc acq_common_desc;
325
326 uint16_t sq_idx;
327
328 uint16_t reserved;
329
330 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
331 uint32_t sq_doorbell_offset;
332
333 /* low latency queue ring base address as an offset to PCIe MMIO
334 * LLQ_MEM BAR
335 */
336 uint32_t llq_descriptors_offset;
337
338 /* low latency queue headers' memory as an offset to PCIe MMIO
339 * LLQ_MEM BAR
340 */
341 uint32_t llq_headers_offset;
342 };
343
344 struct ena_admin_aq_destroy_sq_cmd {
345 struct ena_admin_aq_common_desc aq_common_descriptor;
346
347 struct ena_admin_sq sq;
348 };
349
350 struct ena_admin_acq_destroy_sq_resp_desc {
351 struct ena_admin_acq_common_desc acq_common_desc;
352 };
353
354 struct ena_admin_aq_create_cq_cmd {
355 struct ena_admin_aq_common_desc aq_common_descriptor;
356
357 /* 4:0 : reserved5
358 * 5 : interrupt_mode_enabled - if set, cq operates
359 * in interrupt mode, otherwise - polling
360 * 7:6 : reserved6
361 */
362 uint8_t cq_caps_1;
363
364 /* 4:0 : cq_entry_size_words - size of CQ entry in
365 * 32-bit words, valid values: 4, 8.
366 * 7:5 : reserved7
367 */
368 uint8_t cq_caps_2;
369
370 /* completion queue depth in # of entries. must be power of 2 */
371 uint16_t cq_depth;
372
373 /* msix vector assigned to this cq */
374 uint32_t msix_vector;
375
376 /* cq physical base address in OS memory. CQ must be physically
377 * contiguous
378 */
379 struct ena_common_mem_addr cq_ba;
380 };
381
382 struct ena_admin_acq_create_cq_resp_desc {
383 struct ena_admin_acq_common_desc acq_common_desc;
384
385 uint16_t cq_idx;
386
387 /* actual cq depth in number of entries */
388 uint16_t cq_actual_depth;
389
390 uint32_t numa_node_register_offset;
391
392 uint32_t cq_head_db_register_offset;
393
394 uint32_t cq_interrupt_unmask_register_offset;
395 };
396
397 struct ena_admin_aq_destroy_cq_cmd {
398 struct ena_admin_aq_common_desc aq_common_descriptor;
399
400 uint16_t cq_idx;
401
402 uint16_t reserved1;
403 };
404
405 struct ena_admin_acq_destroy_cq_resp_desc {
406 struct ena_admin_acq_common_desc acq_common_desc;
407 };
408
409 /* ENA AQ Get Statistics command. Extended statistics are placed in control
410 * buffer pointed by AQ entry
411 */
412 struct ena_admin_aq_get_stats_cmd {
413 struct ena_admin_aq_common_desc aq_common_descriptor;
414
415 union {
416 /* command specific inline data */
417 uint32_t inline_data_w1[3];
418
419 struct ena_admin_ctrl_buff_info control_buffer;
420 } u;
421
422 /* stats type as defined in enum ena_admin_get_stats_type */
423 uint8_t type;
424
425 /* stats scope defined in enum ena_admin_get_stats_scope */
426 uint8_t scope;
427
428 uint16_t reserved3;
429
430 /* queue id. used when scope is specific_queue */
431 uint16_t queue_idx;
432
433 /* device id, value 0xFFFF means mine. only privileged device can get
434 * stats of other device
435 */
436 uint16_t device_id;
437
438 /* a bitmap representing the requested metric values */
439 uint64_t requested_metrics;
440 };
441
442 /* Basic Statistics Command. */
443 struct ena_admin_basic_stats {
444 uint32_t tx_bytes_low;
445
446 uint32_t tx_bytes_high;
447
448 uint32_t tx_pkts_low;
449
450 uint32_t tx_pkts_high;
451
452 uint32_t rx_bytes_low;
453
454 uint32_t rx_bytes_high;
455
456 uint32_t rx_pkts_low;
457
458 uint32_t rx_pkts_high;
459
460 uint32_t rx_drops_low;
461
462 uint32_t rx_drops_high;
463
464 uint32_t tx_drops_low;
465
466 uint32_t tx_drops_high;
467 };
468
469 /* ENI Statistics Command. */
470 struct ena_admin_eni_stats {
471 /* The number of packets shaped due to inbound aggregate BW
472 * allowance being exceeded
473 */
474 uint64_t bw_in_allowance_exceeded;
475
476 /* The number of packets shaped due to outbound aggregate BW
477 * allowance being exceeded
478 */
479 uint64_t bw_out_allowance_exceeded;
480
481 /* The number of packets shaped due to PPS allowance being exceeded */
482 uint64_t pps_allowance_exceeded;
483
484 /* The number of packets shaped due to connection tracking
485 * allowance being exceeded and leading to failure in establishment
486 * of new connections
487 */
488 uint64_t conntrack_allowance_exceeded;
489
490 /* The number of packets shaped due to linklocal packet rate
491 * allowance being exceeded
492 */
493 uint64_t linklocal_allowance_exceeded;
494 };
495
496 struct ena_admin_ena_srd_stats {
497 /* Number of packets transmitted over ENA SRD */
498 uint64_t ena_srd_tx_pkts;
499
500 /* Number of packets transmitted or could have been
501 * transmitted over ENA SRD
502 */
503 uint64_t ena_srd_eligible_tx_pkts;
504
505 /* Number of packets received over ENA SRD */
506 uint64_t ena_srd_rx_pkts;
507
508 /* Percentage of the ENA SRD resources that is in use */
509 uint64_t ena_srd_resource_utilization;
510 };
511
512 /* ENA SRD Statistics Command */
513 struct ena_admin_ena_srd_info {
514 /* ENA SRD configuration bitmap. See ena_admin_ena_srd_flags for
515 * details
516 */
517 uint64_t flags;
518
519 struct ena_admin_ena_srd_stats ena_srd_stats;
520 };
521
522 /* Customer Metrics Command. */
523 struct ena_admin_customer_metrics {
524 /* A bitmap representing the reported customer metrics according to
525 * the order they are reported
526 */
527 uint64_t reported_metrics;
528 };
529
530 struct ena_admin_acq_get_stats_resp {
531 struct ena_admin_acq_common_desc acq_common_desc;
532
533 union {
534 uint64_t raw[7];
535
536 struct ena_admin_basic_stats basic_stats;
537
538 struct ena_admin_eni_stats eni_stats;
539
540 struct ena_admin_ena_srd_info ena_srd_info;
541
542 struct ena_admin_customer_metrics customer_metrics;
543 } u;
544 };
545
546 struct ena_admin_get_set_feature_common_desc {
547 /* 1:0 : select - 0x1 - current value; 0x3 - default
548 * value
549 * 7:3 : reserved3
550 */
551 uint8_t flags;
552
553 /* as appears in ena_admin_aq_feature_id */
554 uint8_t feature_id;
555
556 /* The driver specifies the max feature version it supports and the
557 * device responds with the currently supported feature version. The
558 * field is zero based
559 */
560 uint8_t feature_version;
561
562 uint8_t reserved8;
563 };
564
565 struct ena_admin_device_attr_feature_desc {
566 uint32_t impl_id;
567
568 uint32_t device_version;
569
570 /* bitmap of ena_admin_aq_feature_id, which represents supported
571 * subcommands for the set/get feature admin commands.
572 */
573 uint32_t supported_features;
574
575 /* bitmap of ena_admin_aq_caps_id, which represents device
576 * capabilities.
577 */
578 uint32_t capabilities;
579
580 /* Indicates how many bits are used physical address access. */
581 uint32_t phys_addr_width;
582
583 /* Indicates how many bits are used virtual address access. */
584 uint32_t virt_addr_width;
585
586 /* unicast MAC address (in Network byte order) */
587 uint8_t mac_addr[6];
588
589 uint8_t reserved7[2];
590
591 uint32_t max_mtu;
592 };
593
594 enum ena_admin_llq_header_location {
595 /* header is in descriptor list */
596 ENA_ADMIN_INLINE_HEADER = 1,
597 /* header in a separate ring, implies 16B descriptor list entry */
598 ENA_ADMIN_HEADER_RING = 2,
599 };
600
601 enum ena_admin_llq_ring_entry_size {
602 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
603 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
604 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
605 };
606
607 enum ena_admin_llq_num_descs_before_header {
608 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
609 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
610 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
611 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
612 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
613 };
614
615 /* packet descriptor list entry always starts with one or more descriptors,
616 * followed by a header. The rest of the descriptors are located in the
617 * beginning of the subsequent entry. Stride refers to how the rest of the
618 * descriptors are placed. This field is relevant only for inline header
619 * mode
620 */
621 enum ena_admin_llq_stride_ctrl {
622 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
623 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
624 };
625
626 enum ena_admin_accel_mode_feat {
627 ENA_ADMIN_DISABLE_META_CACHING = 0,
628 ENA_ADMIN_LIMIT_TX_BURST = 1,
629 };
630
631 struct ena_admin_accel_mode_get {
632 /* bit field of enum ena_admin_accel_mode_feat */
633 uint16_t supported_flags;
634
635 /* maximum burst size between two doorbells. The size is in bytes */
636 uint16_t max_tx_burst_size;
637 };
638
639 struct ena_admin_accel_mode_set {
640 /* bit field of enum ena_admin_accel_mode_feat */
641 uint16_t enabled_flags;
642
643 uint16_t reserved;
644 };
645
646 struct ena_admin_accel_mode_req {
647 union {
648 uint32_t raw[2];
649
650 struct ena_admin_accel_mode_get get;
651
652 struct ena_admin_accel_mode_set set;
653 } u;
654 };
655
656 struct ena_admin_feature_llq_desc {
657 uint32_t max_llq_num;
658
659 uint32_t max_llq_depth;
660
661 /* specify the header locations the device supports. bitfield of enum
662 * ena_admin_llq_header_location.
663 */
664 uint16_t header_location_ctrl_supported;
665
666 /* the header location the driver selected to use. */
667 uint16_t header_location_ctrl_enabled;
668
669 /* if inline header is specified - this is the size of descriptor list
670 * entry. If header in a separate ring is specified - this is the size
671 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
672 * specify the entry sizes the device supports
673 */
674 uint16_t entry_size_ctrl_supported;
675
676 /* the entry size the driver selected to use. */
677 uint16_t entry_size_ctrl_enabled;
678
679 /* valid only if inline header is specified. First entry associated with
680 * the packet includes descriptors and header. Rest of the entries
681 * occupied by descriptors. This parameter defines the max number of
682 * descriptors precedding the header in the first entry. The field is
683 * bitfield of enum ena_admin_llq_num_descs_before_header and specify
684 * the values the device supports
685 */
686 uint16_t desc_num_before_header_supported;
687
688 /* the desire field the driver selected to use */
689 uint16_t desc_num_before_header_enabled;
690
691 /* valid only if inline was chosen. bitfield of enum
692 * ena_admin_llq_stride_ctrl
693 */
694 uint16_t descriptors_stride_ctrl_supported;
695
696 /* the stride control the driver selected to use */
697 uint16_t descriptors_stride_ctrl_enabled;
698
699 /* reserved */
700 uint32_t reserved1;
701
702 /* accelerated low latency queues requirement. driver needs to
703 * support those requirements in order to use accelerated llq
704 */
705 struct ena_admin_accel_mode_req accel_mode;
706 };
707
708 struct ena_admin_queue_ext_feature_fields {
709 uint32_t max_tx_sq_num;
710
711 uint32_t max_tx_cq_num;
712
713 uint32_t max_rx_sq_num;
714
715 uint32_t max_rx_cq_num;
716
717 uint32_t max_tx_sq_depth;
718
719 uint32_t max_tx_cq_depth;
720
721 uint32_t max_rx_sq_depth;
722
723 uint32_t max_rx_cq_depth;
724
725 uint32_t max_tx_header_size;
726
727 /* Maximum Descriptors number, including meta descriptor, allowed for a
728 * single Tx packet
729 */
730 uint16_t max_per_packet_tx_descs;
731
732 /* Maximum Descriptors number allowed for a single Rx packet */
733 uint16_t max_per_packet_rx_descs;
734 };
735
736 struct ena_admin_queue_feature_desc {
737 uint32_t max_sq_num;
738
739 uint32_t max_sq_depth;
740
741 uint32_t max_cq_num;
742
743 uint32_t max_cq_depth;
744
745 uint32_t max_legacy_llq_num;
746
747 uint32_t max_legacy_llq_depth;
748
749 uint32_t max_header_size;
750
751 /* Maximum Descriptors number, including meta descriptor, allowed for a
752 * single Tx packet
753 */
754 uint16_t max_packet_tx_descs;
755
756 /* Maximum Descriptors number allowed for a single Rx packet */
757 uint16_t max_packet_rx_descs;
758 };
759
760 struct ena_admin_set_feature_mtu_desc {
761 /* exclude L2 */
762 uint32_t mtu;
763 };
764
765 struct ena_admin_get_extra_properties_strings_desc {
766 uint32_t count;
767 };
768
769 struct ena_admin_get_extra_properties_flags_desc {
770 uint32_t flags;
771 };
772
773 struct ena_admin_set_feature_host_attr_desc {
774 /* host OS info base address in OS memory. host info is 4KB of
775 * physically contiguous
776 */
777 struct ena_common_mem_addr os_info_ba;
778
779 /* host debug area base address in OS memory. debug area must be
780 * physically contiguous
781 */
782 struct ena_common_mem_addr debug_ba;
783
784 /* debug area size */
785 uint32_t debug_area_size;
786 };
787
788 struct ena_admin_feature_intr_moder_desc {
789 /* interrupt delay granularity in usec */
790 uint16_t intr_delay_resolution;
791
792 uint16_t reserved;
793 };
794
795 struct ena_admin_get_feature_link_desc {
796 /* Link speed in Mb */
797 uint32_t speed;
798
799 /* bit field of enum ena_admin_link types */
800 uint32_t supported;
801
802 /* 0 : autoneg
803 * 1 : duplex - Full Duplex
804 * 31:2 : reserved2
805 */
806 uint32_t flags;
807 };
808
809 struct ena_admin_feature_aenq_desc {
810 /* bitmask for AENQ groups the device can report */
811 uint32_t supported_groups;
812
813 /* bitmask for AENQ groups to report */
814 uint32_t enabled_groups;
815 };
816
817 struct ena_admin_feature_offload_desc {
818 /* 0 : TX_L3_csum_ipv4
819 * 1 : TX_L4_ipv4_csum_part - The checksum field
820 * should be initialized with pseudo header checksum
821 * 2 : TX_L4_ipv4_csum_full
822 * 3 : TX_L4_ipv6_csum_part - The checksum field
823 * should be initialized with pseudo header checksum
824 * 4 : TX_L4_ipv6_csum_full
825 * 5 : tso_ipv4
826 * 6 : tso_ipv6
827 * 7 : tso_ecn
828 */
829 uint32_t tx;
830
831 /* Receive side supported stateless offload
832 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
833 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
834 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
835 * 3 : RX_hash - Hash calculation
836 */
837 uint32_t rx_supported;
838
839 uint32_t rx_enabled;
840 };
841
842 enum ena_admin_hash_functions {
843 ENA_ADMIN_TOEPLITZ = 1,
844 ENA_ADMIN_CRC32 = 2,
845 };
846
847 struct ena_admin_feature_rss_flow_hash_control {
848 uint32_t key_parts;
849
850 uint32_t reserved;
851
852 uint32_t key[ENA_ADMIN_RSS_KEY_PARTS];
853 };
854
855 struct ena_admin_feature_rss_flow_hash_function {
856 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
857 uint32_t supported_func;
858
859 /* 7:0 : selected_func - bitmask of
860 * ena_admin_hash_functions
861 */
862 uint32_t selected_func;
863
864 /* initial value */
865 uint32_t init_val;
866 };
867
868 /* RSS flow hash protocols */
869 enum ena_admin_flow_hash_proto {
870 ENA_ADMIN_RSS_TCP4 = 0,
871 ENA_ADMIN_RSS_UDP4 = 1,
872 ENA_ADMIN_RSS_TCP6 = 2,
873 ENA_ADMIN_RSS_UDP6 = 3,
874 ENA_ADMIN_RSS_IP4 = 4,
875 ENA_ADMIN_RSS_IP6 = 5,
876 ENA_ADMIN_RSS_IP4_FRAG = 6,
877 ENA_ADMIN_RSS_NOT_IP = 7,
878 /* TCPv6 with extension header */
879 ENA_ADMIN_RSS_TCP6_EX = 8,
880 /* IPv6 with extension header */
881 ENA_ADMIN_RSS_IP6_EX = 9,
882 ENA_ADMIN_RSS_PROTO_NUM = 16,
883 };
884
885 /* RSS flow hash fields */
886 enum ena_admin_flow_hash_fields {
887 /* Ethernet Dest Addr */
888 ENA_ADMIN_RSS_L2_DA = BIT(0),
889 /* Ethernet Src Addr */
890 ENA_ADMIN_RSS_L2_SA = BIT(1),
891 /* ipv4/6 Dest Addr */
892 ENA_ADMIN_RSS_L3_DA = BIT(2),
893 /* ipv4/6 Src Addr */
894 ENA_ADMIN_RSS_L3_SA = BIT(3),
895 /* tcp/udp Dest Port */
896 ENA_ADMIN_RSS_L4_DP = BIT(4),
897 /* tcp/udp Src Port */
898 ENA_ADMIN_RSS_L4_SP = BIT(5),
899 };
900
901 struct ena_admin_proto_input {
902 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
903 uint16_t fields;
904
905 uint16_t reserved2;
906 };
907
908 struct ena_admin_feature_rss_hash_control {
909 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
910
911 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
912
913 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
914
915 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
916 };
917
918 struct ena_admin_feature_rss_flow_hash_input {
919 /* supported hash input sorting
920 * 1 : L3_sort - support swap L3 addresses if DA is
921 * smaller than SA
922 * 2 : L4_sort - support swap L4 ports if DP smaller
923 * SP
924 */
925 uint16_t supported_input_sort;
926
927 /* enabled hash input sorting
928 * 1 : enable_L3_sort - enable swap L3 addresses if
929 * DA smaller than SA
930 * 2 : enable_L4_sort - enable swap L4 ports if DP
931 * smaller than SP
932 */
933 uint16_t enabled_input_sort;
934 };
935
936 enum ena_admin_os_type {
937 ENA_ADMIN_OS_LINUX = 1,
938 ENA_ADMIN_OS_WIN = 2,
939 ENA_ADMIN_OS_DPDK = 3,
940 ENA_ADMIN_OS_FREEBSD = 4,
941 ENA_ADMIN_OS_IPXE = 5,
942 ENA_ADMIN_OS_ESXI = 6,
943 ENA_ADMIN_OS_MACOS = 7,
944 ENA_ADMIN_OS_GROUPS_NUM = 7,
945 };
946
947 struct ena_admin_host_info {
948 /* defined in enum ena_admin_os_type */
949 uint32_t os_type;
950
951 /* os distribution string format */
952 uint8_t os_dist_str[128];
953
954 /* OS distribution numeric format */
955 uint32_t os_dist;
956
957 /* kernel version string format */
958 uint8_t kernel_ver_str[32];
959
960 /* Kernel version numeric format */
961 uint32_t kernel_ver;
962
963 /* 7:0 : major
964 * 15:8 : minor
965 * 23:16 : sub_minor
966 * 31:24 : module_type
967 */
968 uint32_t driver_version;
969
970 /* features bitmap */
971 uint32_t supported_network_features[2];
972
973 /* ENA spec version of driver */
974 uint16_t ena_spec_version;
975
976 /* ENA device's Bus, Device and Function
977 * 2:0 : function
978 * 7:3 : device
979 * 15:8 : bus
980 */
981 uint16_t bdf;
982
983 /* Number of CPUs */
984 uint16_t num_cpus;
985
986 uint16_t reserved;
987
988 /* 0 : reserved
989 * 1 : rx_offset
990 * 2 : interrupt_moderation
991 * 3 : rx_buf_mirroring
992 * 4 : rss_configurable_function_key
993 * 5 : reserved
994 * 6 : rx_page_reuse
995 * 31:7 : reserved
996 */
997 uint32_t driver_supported_features;
998 };
999
1000 struct ena_admin_rss_ind_table_entry {
1001 uint16_t cq_idx;
1002
1003 uint16_t reserved;
1004 };
1005
1006 struct ena_admin_feature_rss_ind_table {
1007 /* min supported table size (2^min_size) */
1008 uint16_t min_size;
1009
1010 /* max supported table size (2^max_size) */
1011 uint16_t max_size;
1012
1013 /* table size (2^size) */
1014 uint16_t size;
1015
1016 /* 0 : one_entry_update - The ENA device supports
1017 * setting a single RSS table entry
1018 */
1019 uint8_t flags;
1020
1021 uint8_t reserved;
1022
1023 /* index of the inline entry. 0xFFFFFFFF means invalid */
1024 uint32_t inline_index;
1025
1026 /* used for updating single entry, ignored when setting the entire
1027 * table through the control buffer.
1028 */
1029 struct ena_admin_rss_ind_table_entry inline_entry;
1030 };
1031
1032 /* When hint value is 0, driver should use it's own predefined value */
1033 struct ena_admin_ena_hw_hints {
1034 /* value in ms */
1035 uint16_t mmio_read_timeout;
1036
1037 /* value in ms */
1038 uint16_t driver_watchdog_timeout;
1039
1040 /* Per packet tx completion timeout. value in ms */
1041 uint16_t missing_tx_completion_timeout;
1042
1043 uint16_t missed_tx_completion_count_threshold_to_reset;
1044
1045 /* value in ms */
1046 uint16_t admin_completion_tx_timeout;
1047
1048 uint16_t netdev_wd_timeout;
1049
1050 uint16_t max_tx_sgl_size;
1051
1052 uint16_t max_rx_sgl_size;
1053
1054 uint16_t reserved[8];
1055 };
1056
1057 struct ena_admin_get_feat_cmd {
1058 struct ena_admin_aq_common_desc aq_common_descriptor;
1059
1060 struct ena_admin_ctrl_buff_info control_buffer;
1061
1062 struct ena_admin_get_set_feature_common_desc feat_common;
1063
1064 uint32_t raw[11];
1065 };
1066
1067 struct ena_admin_queue_ext_feature_desc {
1068 /* version */
1069 uint8_t version;
1070
1071 uint8_t reserved1[3];
1072
1073 union {
1074 struct ena_admin_queue_ext_feature_fields max_queue_ext;
1075
1076 uint32_t raw[10];
1077 };
1078 };
1079
1080 struct ena_admin_feature_phc_desc {
1081 /* PHC type as defined in enum ena_admin_get_phc_type,
1082 * used only for GET command.
1083 */
1084 uint8_t type;
1085
1086 /* Reserved - MBZ */
1087 uint8_t reserved1[3];
1088
1089 /* PHC doorbell address as an offset to PCIe MMIO REG BAR,
1090 * used only for GET command.
1091 */
1092 uint32_t doorbell_offset;
1093
1094 /* Max time for valid PHC retrieval, passing this threshold will
1095 * fail the get-time request and block PHC requests for
1096 * block_timeout_usec, used only for GET command.
1097 */
1098 uint32_t expire_timeout_usec;
1099
1100 /* PHC requests block period, blocking starts if PHC request expired
1101 * in order to prevent floods on busy device,
1102 * used only for GET command.
1103 */
1104 uint32_t block_timeout_usec;
1105
1106 /* Shared PHC physical address (ena_admin_phc_resp),
1107 * used only for SET command.
1108 */
1109 struct ena_common_mem_addr output_address;
1110
1111 /* Shared PHC Size (ena_admin_phc_resp),
1112 * used only for SET command.
1113 */
1114 uint32_t output_length;
1115 };
1116
1117 struct ena_admin_get_feat_resp {
1118 struct ena_admin_acq_common_desc acq_common_desc;
1119
1120 union {
1121 uint32_t raw[14];
1122
1123 struct ena_admin_device_attr_feature_desc dev_attr;
1124
1125 struct ena_admin_feature_llq_desc llq;
1126
1127 struct ena_admin_queue_feature_desc max_queue;
1128
1129 struct ena_admin_queue_ext_feature_desc max_queue_ext;
1130
1131 struct ena_admin_feature_aenq_desc aenq;
1132
1133 struct ena_admin_get_feature_link_desc link;
1134
1135 struct ena_admin_feature_offload_desc offload;
1136
1137 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1138
1139 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1140
1141 struct ena_admin_feature_rss_ind_table ind_table;
1142
1143 struct ena_admin_feature_intr_moder_desc intr_moderation;
1144
1145 struct ena_admin_ena_hw_hints hw_hints;
1146
1147 struct ena_admin_feature_phc_desc phc;
1148
1149 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
1150
1151 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
1152 } u;
1153 };
1154
1155 struct ena_admin_set_feat_cmd {
1156 struct ena_admin_aq_common_desc aq_common_descriptor;
1157
1158 struct ena_admin_ctrl_buff_info control_buffer;
1159
1160 struct ena_admin_get_set_feature_common_desc feat_common;
1161
1162 union {
1163 uint32_t raw[11];
1164
1165 /* mtu size */
1166 struct ena_admin_set_feature_mtu_desc mtu;
1167
1168 /* host attributes */
1169 struct ena_admin_set_feature_host_attr_desc host_attr;
1170
1171 /* AENQ configuration */
1172 struct ena_admin_feature_aenq_desc aenq;
1173
1174 /* rss flow hash function */
1175 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1176
1177 /* rss flow hash input */
1178 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1179
1180 /* rss indirection table */
1181 struct ena_admin_feature_rss_ind_table ind_table;
1182
1183 /* LLQ configuration */
1184 struct ena_admin_feature_llq_desc llq;
1185
1186 /* PHC configuration */
1187 struct ena_admin_feature_phc_desc phc;
1188 } u;
1189 };
1190
1191 struct ena_admin_set_feat_resp {
1192 struct ena_admin_acq_common_desc acq_common_desc;
1193
1194 union {
1195 uint32_t raw[14];
1196 } u;
1197 };
1198
1199 struct ena_admin_aenq_common_desc {
1200 uint16_t group;
1201
1202 uint16_t syndrome;
1203
1204 /* 0 : phase
1205 * 7:1 : reserved - MBZ
1206 */
1207 uint8_t flags;
1208
1209 uint8_t reserved1[3];
1210
1211 uint32_t timestamp_low;
1212
1213 uint32_t timestamp_high;
1214 };
1215
1216 /* asynchronous event notification groups */
1217 enum ena_admin_aenq_group {
1218 ENA_ADMIN_LINK_CHANGE = 0,
1219 ENA_ADMIN_FATAL_ERROR = 1,
1220 ENA_ADMIN_WARNING = 2,
1221 ENA_ADMIN_NOTIFICATION = 3,
1222 ENA_ADMIN_KEEP_ALIVE = 4,
1223 ENA_ADMIN_REFRESH_CAPABILITIES = 5,
1224 ENA_ADMIN_AENQ_GROUPS_NUM = 6,
1225 };
1226
1227 enum ena_admin_aenq_notification_syndrome {
1228 ENA_ADMIN_UPDATE_HINTS = 2,
1229 };
1230
1231 struct ena_admin_aenq_entry {
1232 struct ena_admin_aenq_common_desc aenq_common_desc;
1233
1234 /* command specific inline data */
1235 uint32_t inline_data_w4[12];
1236 };
1237
1238 struct ena_admin_aenq_link_change_desc {
1239 struct ena_admin_aenq_common_desc aenq_common_desc;
1240
1241 /* 0 : link_status */
1242 uint32_t flags;
1243 };
1244
1245 struct ena_admin_aenq_keep_alive_desc {
1246 struct ena_admin_aenq_common_desc aenq_common_desc;
1247
1248 uint32_t rx_drops_low;
1249
1250 uint32_t rx_drops_high;
1251
1252 uint32_t tx_drops_low;
1253
1254 uint32_t tx_drops_high;
1255 };
1256
1257 struct ena_admin_ena_mmio_req_read_less_resp {
1258 uint16_t req_id;
1259
1260 uint16_t reg_off;
1261
1262 /* value is valid when poll is cleared */
1263 uint32_t reg_val;
1264 };
1265
1266 struct ena_admin_phc_resp {
1267 uint16_t req_id;
1268
1269 uint8_t reserved1[6];
1270
1271 uint64_t timestamp;
1272
1273 uint8_t reserved2[48];
1274 };
1275
1276 /* aq_common_desc */
1277 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1278 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1279 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1280 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1281 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1282 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1283
1284 /* sq */
1285 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1286 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1287
1288 /* acq_common_desc */
1289 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1290 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1291
1292 /* aq_create_sq_cmd */
1293 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1294 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1295 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1296 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1297 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1298 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1299
1300 /* aq_create_cq_cmd */
1301 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1302 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1303 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1304
1305 /* get_set_feature_common_desc */
1306 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1307
1308 /* get_feature_link_desc */
1309 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1310 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1311 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1312
1313 /* feature_offload_desc */
1314 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1315 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1316 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1317 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1318 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1319 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1320 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1321 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1322 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1323 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1324 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1325 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1326 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1327 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1328 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1329 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1330 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1331 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1332 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1333 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1334 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1335 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1336
1337 /* feature_rss_flow_hash_function */
1338 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1339 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1340
1341 /* feature_rss_flow_hash_input */
1342 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1343 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1344 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1345 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1346 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1347 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1348 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1349 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1350
1351 /* host_info */
1352 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1353 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1354 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1355 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1356 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1357 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1358 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1359 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1360 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1361 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1362 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1363 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1364 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1365 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1366 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1367 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1368 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
1369 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
1370 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1371 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1372 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6
1373 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)
1374
1375 /* feature_rss_ind_table */
1376 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1377
1378 /* aenq_common_desc */
1379 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1380
1381 /* aenq_link_change_desc */
1382 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1383
1384 #if !defined(DEFS_LINUX_MAINLINE)
get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc * p)1385 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1386 {
1387 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1388 }
1389
set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc * p,uint16_t val)1390 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1391 {
1392 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1393 }
1394
get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc * p)1395 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1396 {
1397 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1398 }
1399
set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc * p,uint8_t val)1400 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1401 {
1402 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1403 }
1404
get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc * p)1405 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1406 {
1407 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1408 }
1409
set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc * p,uint8_t val)1410 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1411 {
1412 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1413 }
1414
get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc * p)1415 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1416 {
1417 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1418 }
1419
set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc * p,uint8_t val)1420 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1421 {
1422 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1423 }
1424
get_ena_admin_sq_sq_direction(const struct ena_admin_sq * p)1425 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1426 {
1427 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1428 }
1429
set_ena_admin_sq_sq_direction(struct ena_admin_sq * p,uint8_t val)1430 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1431 {
1432 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1433 }
1434
get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc * p)1435 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1436 {
1437 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1438 }
1439
set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc * p,uint16_t val)1440 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1441 {
1442 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1443 }
1444
get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc * p)1445 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1446 {
1447 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1448 }
1449
set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc * p,uint8_t val)1450 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1451 {
1452 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1453 }
1454
get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd * p)1455 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1456 {
1457 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1458 }
1459
set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1460 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1461 {
1462 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1463 }
1464
get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd * p)1465 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1466 {
1467 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1468 }
1469
set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1470 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1471 {
1472 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1473 }
1474
get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd * p)1475 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1476 {
1477 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1478 }
1479
set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1480 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1481 {
1482 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1483 }
1484
get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd * p)1485 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1486 {
1487 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1488 }
1489
set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1490 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1491 {
1492 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1493 }
1494
get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd * p)1495 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1496 {
1497 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1498 }
1499
set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd * p,uint8_t val)1500 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1501 {
1502 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1503 }
1504
get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd * p)1505 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1506 {
1507 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1508 }
1509
set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd * p,uint8_t val)1510 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1511 {
1512 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1513 }
1514
get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc * p)1515 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1516 {
1517 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1518 }
1519
set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc * p,uint8_t val)1520 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1521 {
1522 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1523 }
1524
get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc * p)1525 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1526 {
1527 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1528 }
1529
set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc * p,uint32_t val)1530 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1531 {
1532 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1533 }
1534
get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc * p)1535 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1536 {
1537 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1538 }
1539
set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc * p,uint32_t val)1540 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1541 {
1542 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1543 }
1544
get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc * p)1545 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1546 {
1547 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1548 }
1549
set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1550 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1551 {
1552 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1553 }
1554
get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc * p)1555 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1556 {
1557 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1558 }
1559
set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc * p,uint32_t val)1560 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1561 {
1562 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1563 }
1564
get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc * p)1565 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1566 {
1567 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1568 }
1569
set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc * p,uint32_t val)1570 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1571 {
1572 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1573 }
1574
get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc * p)1575 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1576 {
1577 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1578 }
1579
set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc * p,uint32_t val)1580 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1581 {
1582 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1583 }
1584
get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc * p)1585 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1586 {
1587 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1588 }
1589
set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc * p,uint32_t val)1590 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1591 {
1592 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1593 }
1594
get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc * p)1595 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1596 {
1597 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1598 }
1599
set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1600 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1601 {
1602 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1603 }
1604
get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc * p)1605 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1606 {
1607 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1608 }
1609
set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc * p,uint32_t val)1610 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1611 {
1612 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1613 }
1614
get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc * p)1615 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1616 {
1617 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1618 }
1619
set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc * p,uint32_t val)1620 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1621 {
1622 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1623 }
1624
get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc * p)1625 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1626 {
1627 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1628 }
1629
set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1630 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1631 {
1632 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1633 }
1634
get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc * p)1635 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1636 {
1637 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1638 }
1639
set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc * p,uint32_t val)1640 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1641 {
1642 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1643 }
1644
get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc * p)1645 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1646 {
1647 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1648 }
1649
set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc * p,uint32_t val)1650 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1651 {
1652 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1653 }
1654
get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc * p)1655 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1656 {
1657 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1658 }
1659
set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc * p,uint32_t val)1660 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1661 {
1662 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1663 }
1664
get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function * p)1665 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1666 {
1667 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1668 }
1669
set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function * p,uint32_t val)1670 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1671 {
1672 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1673 }
1674
get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function * p)1675 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1676 {
1677 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1678 }
1679
set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function * p,uint32_t val)1680 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1681 {
1682 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1683 }
1684
get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1685 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1686 {
1687 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1688 }
1689
set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1690 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1691 {
1692 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1693 }
1694
get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1695 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1696 {
1697 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1698 }
1699
set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1700 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1701 {
1702 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1703 }
1704
get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1705 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1706 {
1707 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1708 }
1709
set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1710 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1711 {
1712 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1713 }
1714
get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1715 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1716 {
1717 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1718 }
1719
set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1720 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1721 {
1722 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1723 }
1724
get_ena_admin_host_info_major(const struct ena_admin_host_info * p)1725 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1726 {
1727 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1728 }
1729
set_ena_admin_host_info_major(struct ena_admin_host_info * p,uint32_t val)1730 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1731 {
1732 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1733 }
1734
get_ena_admin_host_info_minor(const struct ena_admin_host_info * p)1735 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1736 {
1737 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1738 }
1739
set_ena_admin_host_info_minor(struct ena_admin_host_info * p,uint32_t val)1740 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1741 {
1742 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1743 }
1744
get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info * p)1745 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1746 {
1747 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1748 }
1749
set_ena_admin_host_info_sub_minor(struct ena_admin_host_info * p,uint32_t val)1750 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1751 {
1752 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1753 }
1754
get_ena_admin_host_info_module_type(const struct ena_admin_host_info * p)1755 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1756 {
1757 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1758 }
1759
set_ena_admin_host_info_module_type(struct ena_admin_host_info * p,uint32_t val)1760 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1761 {
1762 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1763 }
1764
get_ena_admin_host_info_function(const struct ena_admin_host_info * p)1765 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1766 {
1767 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1768 }
1769
set_ena_admin_host_info_function(struct ena_admin_host_info * p,uint16_t val)1770 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1771 {
1772 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1773 }
1774
get_ena_admin_host_info_device(const struct ena_admin_host_info * p)1775 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1776 {
1777 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1778 }
1779
set_ena_admin_host_info_device(struct ena_admin_host_info * p,uint16_t val)1780 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1781 {
1782 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1783 }
1784
get_ena_admin_host_info_bus(const struct ena_admin_host_info * p)1785 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1786 {
1787 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1788 }
1789
set_ena_admin_host_info_bus(struct ena_admin_host_info * p,uint16_t val)1790 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1791 {
1792 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1793 }
1794
get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info * p)1795 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1796 {
1797 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1798 }
1799
set_ena_admin_host_info_rx_offset(struct ena_admin_host_info * p,uint32_t val)1800 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1801 {
1802 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1803 }
1804
get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info * p)1805 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1806 {
1807 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1808 }
1809
set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info * p,uint32_t val)1810 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1811 {
1812 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1813 }
1814
get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info * p)1815 static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p)
1816 {
1817 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT;
1818 }
1819
set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info * p,uint32_t val)1820 static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val)
1821 {
1822 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK;
1823 }
1824
get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info * p)1825 static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p)
1826 {
1827 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT;
1828 }
1829
set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info * p,uint32_t val)1830 static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val)
1831 {
1832 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
1833 }
1834
get_ena_admin_host_info_rx_page_reuse(const struct ena_admin_host_info * p)1835 static inline uint32_t get_ena_admin_host_info_rx_page_reuse(const struct ena_admin_host_info *p)
1836 {
1837 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK) >> ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT;
1838 }
1839
set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_info * p,uint32_t val)1840 static inline void set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_info *p, uint32_t val)
1841 {
1842 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT) & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK;
1843 }
1844
get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table * p)1845 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1846 {
1847 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1848 }
1849
set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table * p,uint8_t val)1850 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1851 {
1852 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1853 }
1854
get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc * p)1855 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1856 {
1857 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1858 }
1859
set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc * p,uint8_t val)1860 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1861 {
1862 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1863 }
1864
get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc * p)1865 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1866 {
1867 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1868 }
1869
set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc * p,uint32_t val)1870 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1871 {
1872 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1873 }
1874
1875 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1876 #endif /* _ENA_ADMIN_H_ */
1877