1 /* 2 * PROJECT: NEC PC-98 series onboard hardware 3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later) 4 * PURPOSE: Intel 8255A PPI header file 5 * COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com) 6 */ 7 8 #pragma once 9 10 #define PPI_IO_o_PORT_C 0x35 11 12 #define PPI_IO_o_CONTROL 0x37 13 #define PPI_TIMER_1_GATE_TO_SPEAKER 0x06 14 #define PPI_TIMER_1_UNGATE_TO_SPEAKER 0x07 15 #define PPI_SHUTDOWN_1_ENABLE 0x0B 16 #define PPI_SHUTDOWN_0_ENABLE 0x0F 17 18 #define PPI_IO_i_PORT_A 0x31 19 #define PPI_IO_i_PORT_B 0x33 20 #define PPI_IO_i_PORT_C 0x35 21 22 typedef union _SYSTEM_CONTROL_PORT_A_REGISTER 23 { 24 struct 25 { 26 UCHAR DipSw2_1:1; 27 UCHAR DipSw2_2:1; 28 UCHAR DipSw2_3:1; 29 UCHAR DipSw2_4:1; 30 UCHAR DipSw2_5:1; 31 UCHAR DipSw2_6:1; 32 UCHAR DipSw2_7:1; 33 UCHAR DipSw2_8:1; 34 }; 35 UCHAR Bits; 36 } SYSTEM_CONTROL_PORT_A_REGISTER, *PSYSTEM_CONTROL_PORT_A_REGISTER; 37 38 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER 39 { 40 struct 41 { 42 UCHAR RtcData:1; 43 44 /* NMI */ 45 UCHAR ExtendedMemoryParityCheck:1; 46 UCHAR MemoryParityCheck:1; 47 48 UCHAR HighResolution:1; 49 UCHAR Int3:1; 50 UCHAR DataCarrierDetect:1; 51 UCHAR ClearToSend:1; 52 UCHAR RingIndicator:1; 53 }; 54 UCHAR Bits; 55 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER; 56 57 typedef union _SYSTEM_CONTROL_PORT_C_REGISTER 58 { 59 struct 60 { 61 UCHAR InterruptEnableRxReady:1; 62 UCHAR InterruptEnableTxEmpty:1; 63 UCHAR InterruptEnableTxReady:1; 64 UCHAR Timer1GateToSpeaker:1; 65 UCHAR Mcke:1; 66 UCHAR Shut1:1; 67 UCHAR PrinterStrobeSignal:1; 68 UCHAR Shut0:1; 69 }; 70 UCHAR Bits; 71 } SYSTEM_CONTROL_PORT_C_REGISTER, *PSYSTEM_CONTROL_PORT_C_REGISTER; 72