1 /*
2 * Copyright (c) 2007-2013 Michael Mondy
3 * Copyright (c) 2012-2016 Harry Reed
4 * Copyright (c) 2013-2016 Charles Anthony
5 * Copyright (c) 2021 The DPS8M Development Team
6 *
7 * All rights reserved.
8 *
9 * This software is made available under the terms of the ICU
10 * License, version 1.8.1 or later. For more details, see the
11 * LICENSE.md file at the top-level directory of this distribution.
12 */
13
14 #ifndef DPS8_HW_CONSTS_H
15 # define DPS8_HW_CONSTS_H
16
17 # include "dps8_math128.h"
18
19 /////////////////////////////////////
20 //
21 // SCU/Memory
22 //
23
24 # define XXX_TEMP_SCU_SUBPORT 0
25
26 enum { N_SCU_PORTS = 8 };
27 enum { N_SCU_SUBPORTS = 4 };
28 enum { N_ASSIGNMENTS = 2 };
29 // Number of interrupts in an interrupt cell register
30 enum { N_CELL_INTERRUPTS = 32 };
31
32 # define PASIZE 24 /* phys addr width */
33 # define PAMASK ((1U << PASIZE) - 1U)
34 // Mask out low bit
35 # define PAEVEN (((1U << (PASIZE - 1)) - 1U) << 1)
36 # define MEM_SIZE_MAX (1U << PASIZE) /* maximum memory */
37
38 // The minimum allocation size of a SCU is 64K (2^16)
39 // (2 banks of 32K). Call it an SCBANK
40 # define SCBANK_SZ (1U << 16)
41
42 // Maximum memory size is MEM_SIZE_MAX, number of
43 // scbanks is:
44 # define N_SCBANKS ((MEM_SIZE_MAX) / (SCBANK_SZ))
45
46 //
47 // Memory addressing
48 //
49
50
51 # define VASIZE 18 // virtual addr width
52 # define AMASK ((1U << VASIZE) - 1U) // virtual addr mask
53 # define SEGSIZE (1U << VASIZE) // size of segment in words
54
55
56 /////////////////////////////////////
57 //
58 // Append unit memory paging
59 //
60
61 # define PGSZ 1024u
62 # define PGMK 1023u
63
64 //
65 // IOM
66 //
67
68
69 enum { MAX_CHANNELS = 64 };
70 enum { N_IOM_PORTS = 8 };
71 // The number of devices that a dev_code can address (6 bit number)
72 enum { N_DEV_CODES = 64 };
73 enum { IOM_CONNECT_CHAN = 2 };
74
75 /////////////////////////////////////
76 //
77 // Words
78 //
79
80
81 # define MAX18 0777777U
82 # define MAX18POS 0377777U // 2**17-1
83 # define MAX18NEG 0400000U // -2**17
84 # define SIGN18 0400000U
85 // NB. these 2 use the wrong bit number convention
86 # define BIT19 01000000U // carry out bit from 18 bit arithmetic
87 # define BIT20 02000000U // carry out bit from 19 bit arithmetic
88 # define MASK36 0777777777777LLU // data mask
89 # define DMASK MASK36
90 # define MASK10 0001777U // 10-bit data mask
91 # define MASK14 0037777U // 14-bit data mask
92 # define MASK16 0177777U // 16-bit data mask
93 # define MASK17 0377777U // 17-bit data mask
94 # define MASK18 0777777U // 18-bit data mask
95 # define WMASK MASK18 // WORDNO mask
96 # define MASKLO18 0000000777777LLU
97 # define MASKHI18 0777777000000LLU
98 # define MASK20 03777777U // 20-bit data mask
99 # define MASK24 077777777U // 24-bit data mask
100 # define MASK28 01777777777U // 28-bit data mask
101 # define SIGN24 040000000U
102 # define SIGN36 0400000000000LLU // sign bit of a 36-bit word
103 // NB. these 3 use the wrong bit number convention
104 # define BIT37 01000000000000LLU // carry out bit from 36 bit arithmetic
105 # define BIT38 02000000000000LLU // carry out bit from 37 bit arithmetic
106 # define BIT35 0200000000000LLU // next to the sign bit
107 # define MASK32 037777777777U
108 # define MASK15 077777U
109 # define SMASK MASK15 // Segment number mask
110 # define SIGN15 040000U // sign mask 15-bit number
111 # define MAGMASK 0377777777777LLU // magnitude mask
112 # define ONES 0777777777777LLU
113 # define NEG136 0777777777777LLU // -1
114 # define MAXPOS 0377777777777LLU // 2**35-1
115 # define MAXNEG 0400000000000LLU // -2**35
116 # define MAX36 0777777777777LLU // 2**36-1
117 # define MAX72 (((word72)1U << 72) - 1U) // 72 1's
118
119 # define CARRY 01000000000000LLU // carry from 2 36-bit additions/subs
120 # define ZEROEXT 0777777777777LLU // mask to zero extend a 36 => 64-bit int
121 # define ZEROEXT18 0777777U // mask to zero extend a 18 => 32-bit int
122
123 # ifdef NEED_128
124
125 # define SIGN72 (construct_128 (0200U, 0U))
126 // NB. these use the wrong bit number convention
127 # define BIT68 (construct_128 (010U, 0U))
128 # define BIT69 (construct_128 (020U, 0U))
129 # define BIT70 (construct_128 (040U, 0U))
130 # define BIT71 (construct_128 (0100U, 0U)) // next to the sign bit
131 # define BIT73 (construct_128 (0400U, 0U)) // carry out bit from 72 bit arithmetic
132 # define BIT74 (construct_128 (01000U, 0U)) // carry out bit from 73 bit arithmetic
133 # define MASK63 0x7FFFFFFFFFFFFFFF
134 # define MASK64 0xFFFFFFFFFFFFFFFF
135 # define MASK68 (construct_128 (017U, MASK64)) // Hex mode mantissa normalization mask
136 # define MASK70 (construct_128 (0077U, MASK64))
137 # define MASK71 (construct_128 (0177U, MASK64))
138 # define MASK72 (construct_128 (0377U, MASK64))
139
140 # else
141
142 # define SIGN72 ((word72)1U << 71)
143 // NB. these use the wrong bit number convention
144 # define BIT68 ((word72)1U << 67)
145 # define BIT69 ((word72)1U << 68)
146 # define BIT70 ((word72)1U << 69)
147 # define BIT71 ((word72)1U << 70) // next to the sign bit
148 # define BIT73 ((word72)1U << 72) // carry out bit from 72 bit arithmetic
149 # define BIT74 ((word72)1U << 73) // carry out bit from 73 bit arithmetic
150
151 # define MASK68 (((word72)1U << 68) - 1U) // Hex mode mantissa normalization mask
152 # define MASK70 (((word72)1U << 70) - 1U)
153 # define MASK71 (((word72)1U << 71) - 1U)
154 # define MASK72 (((word72)1U << 72) - 1U)
155 # define ZEROEXT72 (((word72)1U << 72) - 1U) // mask to zero extend a 72 => 128 int
156
157 # endif
158
159 # define SIGN64 ((uint64)1U << 63)
160
161 # define MASK2 03U
162 # define MASK3 07U
163 # define MASK4 017U
164 # define MASK5 037U
165 # define MASK6 077U
166 # define MASK7 0177U
167
168 # define SIGN8 0200U // sign mask 8-bit number
169 # define MASK8 0377U // 8-bit mask
170 # define MASK9 0777U // 9-bit mask
171
172 # define MASK11 03777U
173
174 # define SIGN12 0x800U // sign mask 12-bit number
175 # define MASK12 07777U
176
177 # define SIGN6 0040U // sign bit of 6-bit signed numfer (e.g. Scaling Factor)
178
179 # define MASK35 0377777777777llu
180
181 # define MASKBITS(x) ( ~(~((uint64)0)<<x) ) // lower (x) bits all ones
182 # define MASKBITS18(x) ( ~(~((word18)0)<<x) ) // lower (x) bits all ones
183 # define MASKBITS72(x) ( ~(~((word72)0)<<x) ) // lower (x) bits all ones
184
185 # define GETHI36(a) ((word18) (((a) >> 18) & MASK18))
186 # define GETLO36(a) ((word18) ((a) & MASK18))
187 # define SETHI36(a,b) (((a) &= MASKLO18), ((a) |= ((((word36)(b) & MASKLO18) << 18))))
188 # define SETLO36(a,b) (((a) &= MASKHI18), ((a) |= ((word36)(b) & MASKLO18)))
189 # define GETHI(a) GETHI36((a))
190 # define GETLO(a) GETLO36((a))
191 # define SETHI(a,b) SETHI36((a),(b))
192 # define SETLO(a,b) SETLO36((a),(b))
193
194 # define GETHI72(a) ((word36) (((a) >> 36) & MASK36))
195 # define GETLO72(a) ((word36) ((a) & MASK36))
196 # define SETHI72(a,b) ((a) &= MASK36, (a) |= ((((word72)(b) & MASK36)) << 36))
197 # define SETLO72(a,b) ((a) &= MASK36 << 36, (a) |= ((word72)(b) & MASK36))
198
199 # define GET24(a) ((word24) ((a) & MASK24))
200 # define MASK21 07777777llu
201 # define SIGN21 04000000llu
202 # define MASK22 017777777llu
203 # define SIGN22 010000000llu
204 # define MASK27 0777777777llu
205
206
207 // Sign extend DPS8M words into host words
208
SIGNEXT6_int(word6 w)209 static inline int SIGNEXT6_int (word6 w)
210 {
211 if (w & SIGN6)
212 {
213 return ((int) w) | (int) (((uint) -1) << 6);
214 }
215 return w & MASK6;
216 }
217
SIGNEXT8_int(word8 w)218 static inline int SIGNEXT8_int (word8 w)
219 {
220 if (w & SIGN8)
221 {
222 return ((int) w) | (int) (((uint) -1) << 8);
223 }
224 return w & MASK8;
225 }
226
SIGNEXT15_32(word15 w)227 static inline int32 SIGNEXT15_32 (word15 w)
228 {
229 if (w & SIGN15)
230 {
231 return ((int32) w) | (int32) (((uint32) -1) << 15);
232 }
233 return w & MASK15;
234 }
235
SIGNEXT18_32(word18 w)236 static inline int32 SIGNEXT18_32 (word18 w)
237 {
238 if (w & SIGN18)
239 {
240 return ((int32) w) | (int32) (((uint32) -1) << 18);
241 }
242 return w & MASK18;
243 }
244
SIGNEXT21_32(word21 w)245 static inline int32 SIGNEXT21_32 (word21 w)
246 {
247 if (w & SIGN21)
248 {
249 return ((int32) w) | (int32) (((uint32) -1) << 21);
250 }
251 return w & MASK21;
252 }
253
SIGNEXT22_32(word22 w)254 static inline int32 SIGNEXT22_32 (word22 w)
255 {
256 if (w & SIGN22)
257 {
258 return ((int32) w) | (int32) (((uint32) -1) << 22);
259 }
260 return w & MASK22;
261 }
262
SIGNEXT24_32(word24 w)263 static inline int32 SIGNEXT24_32 (word24 w)
264 {
265 if (w & SIGN24)
266 {
267 return ((int32) w) | (int32) (((uint32) -1) << 24);
268 }
269 return w & MASK24;
270 }
271
SIGNEXT36_64(word36 w)272 static inline t_int64 SIGNEXT36_64 (word36 w)
273 {
274 if (w & SIGN36)
275 {
276 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 36);
277 }
278 return w & MASK36;
279 }
280
SIGNEXT18_64(word36 w)281 static inline t_int64 SIGNEXT18_64 (word36 w)
282 {
283 if (w & SIGN18)
284 {
285 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 18);
286 }
287 return w & MASK18;
288 }
289
SIGNEXT21_64(word36 w)290 static inline t_int64 SIGNEXT21_64 (word36 w)
291 {
292 if (w & SIGN21)
293 {
294 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 21);
295 }
296 return w & MASK21;
297 }
298
SIGNEXT22_64(word36 w)299 static inline t_int64 SIGNEXT22_64 (word36 w)
300 {
301 if (w & SIGN22)
302 {
303 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 22);
304 }
305 return w & MASK22;
306 }
307
SIGNEXT24_64(word36 w)308 static inline t_int64 SIGNEXT24_64 (word36 w)
309 {
310 if (w & SIGN24)
311 {
312 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 24);
313 }
314 return w & MASK24;
315 }
316
SIGNEXT72_128(word72 w)317 static inline int128 SIGNEXT72_128 (word72 w)
318 {
319 # ifdef NEED_128
320 if (isnonzero_128 (and_128 (w, SIGN72)))
321 {
322 uint128 v = or_128 (w, construct_128 (0xFFFFFFFFFFFFFF80, 0));
323 return cast_s128 (v);
324 }
325 uint128 v = and_128 (w, MASK72);
326 # if defined(__sun__) || defined(_AIX)
327 return (int128) { (uint64_t) v.h, v.l};
328 # elif defined(__MINGW32__)
329 return (int128) { (int64_t) v.h, v.l};
330 # else
331 return (int128) { (__int64_t) v.h, v.l};
332 # endif
333 # else
334 if (w & SIGN72)
335 {
336 return ((int128) w) | (int128) (((uint128) -1ll) << 72);
337 }
338 return w & MASK72;
339 # endif
340 }
341
342 # ifdef NEED_128
SIGNEXT36_128(word36 w)343 static inline int128 SIGNEXT36_128 (word36 w)
344 {
345 if (w & SIGN36)
346 {
347 return construct_s128 ((int64_t) MASK64, w | 0xFFFFFFF000000000);
348 }
349 return construct_s128 (0, w);
350 }
351 # endif
352
353 // Sign extend DPS8M words into DPS8M words
354 // NB: The high order bits in the host container will
355 // set to 0; you cannot do host math with
356 // these results.
357
SIGNEXT15_18(word15 w)358 static inline word18 SIGNEXT15_18 (word15 w)
359 {
360 if (w & SIGN15)
361 {
362 return (w | ((word18) -1) << 15) & MASK18;
363 }
364 return w & MASK15;
365 }
366
SIGNEXT18_24(word18 w)367 static inline word24 SIGNEXT18_24 (word18 w)
368 {
369 if (w & SIGN18)
370 {
371 return (w | ((word24) -1) << 18) & MASK24;
372 }
373 return w & MASK18;
374 }
375
SIGNEXT36_72(word36 w)376 static inline word72 SIGNEXT36_72 (word36 w)
377 {
378 # ifdef NEED_128
379 if (w & SIGN36)
380 {
381 //return (w | ((word72) DMASK) << 36) & MASK72;
382 return construct_128 (0377U, (w & MASK36) | 0xFFFFFFF000000000);
383 }
384 //return w & MASK36;
385 return construct_128 (0, w & MASK36);
386 # else
387 if (w & SIGN36)
388 {
389 return (w | ((word72) DMASK) << 36) & MASK72;
390 }
391 return w & MASK36;
392 # endif
393 }
394
395 # define SETS36(x) ((x) | SIGN36)
396 # define CLRS36(x) ((x) & ~SIGN36)
397 # define TSTS36(x) ((x) & SIGN36)
398
399 /////////////////////////////////////
400 //
401 // Instruction format
402 //
403
404 # define INST_V_TAG 0 // Tag
405 # define INST_M_TAG 077U
406 # define INST_V_A 6 // Indirect via pointer
407 # define INST_M_A 1U
408 # define INST_V_I 7 // Interrupt Inhibit
409 # define INST_M_I 1U
410 # define INST_V_OP 9 // opcode
411 # define INST_M_OP 0777U
412 # define INST_V_OPX 8 // opcode etension
413 # define INST_M_OPX 1U
414
415 # define INST_V_ADDR 18 // Address
416 # define INST_M_ADDR 0777777U
417 # define INST_V_OFFSET 18 // Offset (Bit29=1)
418 # define INST_M_OFFSET 077777U
419 # define INST_V_PRN 33 // n of PR[n] (Bit29=1)
420 # define INST_M_PRN 07U
421 # define INST_V_ARN 33 // n of AR[n] (Bit29=1)
422 # define INST_M_ARN 07U
423
424
425 # define GET_TAG(x) ((word6) ( (x) & INST_M_TAG ))
426 # define GET_A(x) ((word1) (((x) >> INST_V_A) & INST_M_A ))
427 # define GET_I(x) ((int32) (((x) >> INST_V_I) & INST_M_I ))
428 # define GET_OP(x) ((word9) (((x) >> INST_V_OP) & INST_M_OP ))
429 # define GET_OPX(x) ((bool) (((x) >> INST_V_OPX) & INST_M_OPX))
430
431 # define GET_OFFSET(x) ((word15) (((x) >> INST_V_OFFSET) & INST_M_OFFSET))
432 # define GET_PRN(x) ((word3) (((x) >> INST_V_PRN) & INST_M_PRN))
433 # define GET_ARN(x) ((word3) (((x) >> INST_V_ARN) & INST_M_ARN))
434
435 # define GET_TM(x) ( (GET_TAG(x) & 060U))
436 # define GET_TD(x) ( (GET_TAG(x) & 017U))
437
438 # define GET_ADDR(x) ((uint32) (((x) >> INST_V_ADDR) & INST_M_ADDR))
439
440 // tag defines ...
441 # define TAG_R 0U
442 # define TAG_RI 1U
443 # define TAG_IT 2U
444 # define TAG_IR 3U
445
446
447 # define _TD(tag) ((tag) & 017U)
448 # define _TM(tag) ((tag) & 060U)
449
450 enum {
451 TD_N = 000U,
452 TD_AU = 001U,
453 TD_QU = 002U,
454 TD_DU = 003U,
455 TD_IC = 004U,
456 TD_AL = 005U,
457 TD_QL = 006U,
458 TD_DL = 007U,
459 TD_X0 = 010U,
460 TD_X1 = 011U,
461 TD_X2 = 012U,
462 TD_X3 = 013U,
463 TD_X4 = 014U,
464 TD_X5 = 015U,
465 TD_X6 = 016U,
466 TD_X7 = 017U
467 };
468
469 enum {
470 TM_R = 000U,
471 TM_RI = 020U,
472 TM_IT = 040U, // HWR - next 2 had values swapped
473 TM_IR = 060U
474 };
475
476 /* see AL39, pp 6-13, tbl 6-3 */
477 enum {
478 IT_F1 = 000U,
479 IT_SD = 004U,
480 IT_SCR = 005U,
481 IT_F2 = 006U,
482 IT_F3 = 007U,
483 IT_CI = 010U,
484 IT_I = 011U,
485 IT_SC = 012U,
486 IT_AD = 013U,
487 IT_DI = 014U,
488 IT_DIC = 015U,
489 IT_ID = 016U,
490 IT_IDC = 017U,
491
492 // not really IT, but they're in it's namespace
493 SPEC_ITP = 001U,
494 SPEC_ITS = 003U
495 };
496
497 # define GET_TB(tag) ((tag) & 040U)
498 # define GET_CF(tag) ((tag) & 007U)
499
500 # define _TB(tag) GET_TB((tag))
501 # define _CF(tag) GET_CF((tag))
502
503 # define TB6 000U // 6-bit characters
504 # define TB9 040U // 9-bit characters
505
506 /////////////////////////////////////
507 //
508 // ITS/ITP
509 //
510
511 # define ISITP(x) (((x) & INST_M_TAG) == 041U)
512 # define GET_ITP_PRNUM(Ypair) ((word3) (((Ypair)[0] >> 33) & 07U))
513 # define GET_ITP_WORDNO(Ypair) ((word18) (((Ypair)[1] >> 18) & WMASK))
514 # define GET_ITP_BITNO(Ypair) ((word6) (((Ypair)[1] >> 9) & 077U))
515 # define GET_ITP_MOD(Ypair) (GET_TAG((Ypair)[1]))
516
517 # define ISITS(x) (((x) & INST_M_TAG) == 043U)
518 # define GET_ITS_SEGNO(Ypair) ((word15) (((Ypair)[0] >> 18) & SMASK))
519 # define GET_ITS_RN(Ypair) ((word3) (((Ypair)[0] >> 15) & 07))
520 # define GET_ITS_WORDNO(Ypair) ((word18) (((Ypair)[1] >> 18) & WMASK))
521 # define GET_ITS_BITNO(Ypair) ((word6) (((Ypair)[1] >> 9) & 077))
522 # define GET_ITS_MOD(Ypair) (GET_TAG((Ypair)[1]))
523
524 /////////////////////////////////////
525 //
526 // Indicator register bits
527 //
528
529 # define F_V_A 17 // Zero
530 # define F_V_B 16 // Negative
531 # define F_V_C 15 // Carry
532 # define F_V_D 14 // Overflow
533 # define F_V_E 13 // Exponent Overflow
534 # define F_V_F 12 // Exponent Underflow
535 # define F_V_G 11 // Overflow Mask
536 # define F_V_H 10 // Tally Runout
537 # define F_V_I 9 // Parity Error
538 # define F_V_J 8 // Parity Mask
539 # define F_V_K 7 // Not BAR mode
540 # define F_V_L 6 // Truncation
541 # define F_V_M 5 // Mid Instruction Interrupt Fault
542 # define F_V_N 4 // Absolute Mode
543 # define F_V_O 3 // Hex Mode
544
545 # define F_A (1LLU << F_V_A)
546 # define F_B (1LLU << F_V_B)
547 # define F_C (1LLU << F_V_C)
548 # define F_D (1LLU << F_V_D)
549 # define F_E (1LLU << F_V_E)
550 # define F_F (1LLU << F_V_F)
551 # define F_G (1LLU << F_V_G)
552 # define F_H (1LLU << F_V_H)
553 # define F_I (1LLU << F_V_I)
554 # define F_J (1LLU << F_V_J)
555 # define F_K (1LLU << F_V_K)
556 # define F_L (1LLU << F_V_L)
557 # define F_M (1LLU << F_V_M)
558 # define F_N (1LLU << F_V_N)
559 # define F_O (1LLU << F_V_O)
560
561 # ifdef DPS8M
562 # define I_HEX F_O // base-16 exponent 0000010
563 # endif
564 # define I_ABS F_N // absolute mode 0000020
565 # define I_MIF F_M // mid-instruction interrupt fault 0000040
566 # define I_TRUNC F_L // truncation 0000100
567 # define I_NBAR F_K // not BAR mode 0000200
568 # define I_PMASK F_J // parity mask 0000400
569 # define I_PERR F_I // parity error 0001000
570 # define I_TALLY F_H // tally runout 0002000
571 # define I_OMASK F_G // overflow mask 0004000
572 # define I_EUFL F_F // exponent underflow 0010000
573 # define I_EOFL F_E // exponent overflow 0020000
574 # define I_OFLOW F_D // overflow 0040000
575 # define I_CARRY F_C // carry 0100000
576 # define I_NEG F_B // negative 0200000
577 # define I_ZERO F_A // zero 0400000
578
579 # define I_ZNOC (I_ZERO | I_NEG | I_OFLOW | I_CARRY)
580 # define I_ZNC (I_ZERO | I_NEG | I_CARRY)
581
582 # define CLR_I_ABS CLRF (cpu.cu.IR, I_ABS)
583 # define CLR_I_MIF CLRF (cpu.cu.IR, I_MIF)
584 # define CLR_I_TRUNC CLRF (cpu.cu.IR, I_TRUNC)
585 # define CLR_I_NBAR CLRF (cpu.cu.IR, I_NBAR)
586 # define CLR_I_TALLY CLRF (cpu.cu.IR, I_TALLY)
587 # define CLR_I_PMASK CLRF (cpu.cu.IR, I_PMASK)
588 # define CLR_I_EOFL CLRF (cpu.cu.IR, I_EOFL)
589 # define CLR_I_EUFL CLRF (cpu.cu.IR, I_EUFL)
590 # define CLR_I_OFLOW CLRF (cpu.cu.IR, I_OFLOW)
591 # define CLR_I_CARRY CLRF (cpu.cu.IR, I_CARRY)
592 # define CLR_I_NEG CLRF (cpu.cu.IR, I_NEG)
593 # define CLR_I_ZERO CLRF (cpu.cu.IR, I_ZERO)
594
595 # define SET_I_ABS SETF (cpu.cu.IR, I_ABS)
596 # define SET_I_NBAR SETF (cpu.cu.IR, I_NBAR)
597 # define SET_I_TRUNC SETF (cpu.cu.IR, I_TRUNC)
598 # define SET_I_TALLY SETF (cpu.cu.IR, I_TALLY)
599 # define SET_I_EOFL SETF (cpu.cu.IR, I_EOFL)
600 # define SET_I_EUFL SETF (cpu.cu.IR, I_EUFL)
601 # define SET_I_OFLOW SETF (cpu.cu.IR, I_OFLOW)
602 # define SET_I_CARRY SETF (cpu.cu.IR, I_CARRY)
603 # define SET_I_NEG SETF (cpu.cu.IR, I_NEG)
604 # define SET_I_ZERO SETF (cpu.cu.IR, I_ZERO)
605
606 # define TST_I_ABS TSTF (cpu.cu.IR, I_ABS)
607 # define TST_I_MIF TSTF (cpu.cu.IR, I_MIF)
608 # define TST_I_NBAR TSTF (cpu.cu.IR, I_NBAR)
609 # define TST_I_PMASK TSTF (cpu.cu.IR, I_PMASK)
610 # define TST_I_TRUNC TSTF (cpu.cu.IR, I_TRUNC)
611 # define TST_I_TALLY TSTF (cpu.cu.IR, I_TALLY)
612 # define TST_I_OMASK TSTF (cpu.cu.IR, I_OMASK)
613 # define TST_I_EUFL TSTF (cpu.cu.IR, I_EUFL )
614 # define TST_I_EOFL TSTF (cpu.cu.IR, I_EOFL )
615 # define TST_I_OFLOW TSTF (cpu.cu.IR, I_OFLOW)
616 # define TST_I_CARRY TSTF (cpu.cu.IR, I_CARRY)
617 # define TST_I_NEG TSTF (cpu.cu.IR, I_NEG)
618 # define TST_I_ZERO TSTF (cpu.cu.IR, I_ZERO)
619 # define TST_I_HEX TSTF (cpu.cu.IR, I_HEX)
620
621 # ifdef DPS8M
622 # define SC_I_HEX(v) SCF (v, cpu.cu.IR, I_HEX)
623 # endif
624 # define SC_I_MIF(v) SCF (v, cpu.cu.IR, I_MIF)
625 # define SC_I_TALLY(v) SCF (v, cpu.cu.IR, I_TALLY)
626 # define SC_I_NEG(v) SCF (v, cpu.cu.IR, I_NEG)
627 # define SC_I_ZERO(v) SCF (v, cpu.cu.IR, I_ZERO)
628 # define SC_I_CARRY(v) SCF (v, cpu.cu.IR, I_CARRY);
629 # define SC_I_OFLOW(v) SCF (v, cpu.cu.IR, I_OFLOW);
630 # define SC_I_EOFL(v) SCF (v, cpu.cu.IR, I_EOFL);
631 # define SC_I_EUFL(v) SCF (v, cpu.cu.IR, I_EUFL);
632 # define SC_I_OMASK(v) SCF (v, cpu.cu.IR, I_OMASK);
633 # define SC_I_PERR(v) SCF (v, cpu.cu.IR, I_PERR);
634 # define SC_I_PMASK(v) SCF (v, cpu.cu.IR, I_PMASK);
635 # define SC_I_TRUNC(v) SCF (v, cpu.cu.IR, I_TRUNC);
636
637 /////////////////////////////////////
638 //
639 // floating-point constants
640 //
641
642 # define FLOAT36MASK 01777777777LLU ///< user to extract mantissa from single precision C(CEAQ)
643 # define FLOAT72MASK 01777777777777777777777LLU ///< use to extract mastissa from double precision C(EAQ)
644 # define FLOAT72SIGN (1LLU << 63) ///< mantissa sign mask for full precision C(EAQ)
645 // XXX beware the 72's are not what they seem!
646
647 /////////////////////////////////////
648 //
649 // Faults
650 //
651
652 # define N_FAULT_GROUPS 7
653 # define N_FAULTS 32
654
655 enum _fault
656 {
657 FAULT_SDF = 0U, // shutdown fault
658 FAULT_STR = 1U, // store fault
659 FAULT_MME = 2U, // master mode entry
660 FAULT_F1 = 3U, // fault tag 1
661 FAULT_TRO = 4U, // timer runout fault
662 FAULT_CMD = 5U, // command
663 FAULT_DRL = 6U, // derail
664 FAULT_LUF = 7U, // lockup
665 FAULT_CON = 8U, // connect
666 FAULT_PAR = 9U, // parity
667 FAULT_IPR = 10U, // illegal proceedure
668 FAULT_ONC = 11U, // operation not complete
669 FAULT_SUF = 12U, // startup
670 FAULT_OFL = 13U, // overflow
671 FAULT_DIV = 14U, // divide check
672 FAULT_EXF = 15U, // execute
673 FAULT_DF0 = 16U, // directed fault 0
674 FAULT_DF1 = 17U, // directed fault 1
675 FAULT_DF2 = 18U, // directed fault 2
676 FAULT_DF3 = 19U, // directed fault 3
677 FAULT_ACV = 20U, // access violation
678 FAULT_MME2 = 21U, // Master mode entry 2
679 FAULT_MME3 = 22U, // Master mode entry 3
680 FAULT_MME4 = 23U, // Master mode entry 4
681 FAULT_F2 = 24U, // fault tag 2
682 FAULT_F3 = 25U, // fault tag 3
683 FAULT_UN1 = 26U, // unassigned
684 FAULT_UN2 = 27U, // unassigned
685 FAULT_UN3 = 28U, // unassigned
686 FAULT_UN4 = 29U, // unassigned
687 FAULT_UN5 = 30U, // unassigned
688 FAULT_TRB = 31U // Trouble
689 };
690
691 # define FAULTBASE_MASK 07740U ///< mask off all but top 7 msb
692
693
694 typedef enum _fault _fault;
695
696 # if 0
697 //no_fault_subtype = 0,
698
699 // FAULT_IPR
700
701 //flt_ipr_ill_op, // An illegal operation code has been detected.
702 //flt_ipr_ill_mod, // An illegal address modifier has been detected.
703 //flt_ipr_ill_slv, // An illegal BAR mode procedure has been encountered.
704 //flt_ipr_ill_dig, // An illegal decimal digit or sign has been detected by the decimal unit.
705 //flt_ipr_ill_proc, // An illegal procedure other than the four above has been encountered.
706
707 // FAULT_PAR
708
709 //proc_paru, // A parity error has been detected in the upper 36 bits of data. (Yeah, right)
710 //proc_parl, // A parity error has been detected in the lower 36 bits of data. (Yeah, right)
711
712 // FAULT_ONC
713
714 //da_err, // Operation not complete. Processor/system controller interface sequence error 1 has been detected. (Yeah, right)
715 //da_err2, // Operation not completed. Processor/system controller interface sequence error 2 has been detected.
716
717 // Misc
718
719 //cpar_dir, // A parity error has been detected in the cache memory directory. (Not likely)
720 //cpar_str, // PAR fault. A data parity error has been detected in the cache memory.
721 //cpar_ia, // PAR fault. An illegal action has been received from a system controller during a store operation with cache memory enabled.
722 //cpar_blk, // PAR fault. A cache memory parity error has occurred during a cache memory data block load.
723
724 // odd word
725 // Cache Duplicate Directory WNO Buffer Overflow
726 //port_a,
727 //port_b,
728 //port_c,
729 //port_d,
730
731 //cpd, // Cache Primary Directory WNO Buffer Overflow
732 // Write Notify (WNO) Parity Error on Port A, B, C, or D.
733
734 // Cache Duplicate Directory Parity Error
735 //level_0,
736 ////level_1,
737 ////level_2,
738 ////level_3,
739
740 // Cache Duplicate Directory Multiple Match
741 //cdd,
742
743 //par_sdwam, // A parity error has been detected in the SDWAM.
744 //par_ptwam, // A parity error has been detected in the PTWAM.
745
746
747 };
748 typedef enum _fault_subtype _fault_subtype;
749 # endif
750
751 typedef enum fault_onc_subtype_
752 {
753 flt_onc_nem, // A nonexistent main memory address has been requested.
754 flt_onc_FORCE = 0400000000000llu // Force enum size to 36 bits.
755 } fault_onc_subtype_;
756
757 typedef enum fault_str_subtype_
758 {
759 flt_str_oob, // A BAR mode boundary violation has occurred.
760 flt_str_ill_ptr, // SPRPn illegal ptr.
761 flt_str_nea, // non-existent address
762 flt_str_FORCE = 0400000000000llu // Force enum size to 36 bits.
763 } fault_str_subtype_;
764
765 typedef enum fault_con_subtype_
766 {
767 con_a = 0, // A $CONNECT signal has been received through port A.
768 con_b = 1, // A $CONNECT signal has been received through port B.
769 con_c = 2, // A $CONNECT signal has been received through port C.
770 con_d = 3, // A $CONNECT signal has been received through port D.
771 flt_con_FORCE = 0400000000000llu // Force enum size to 36 bits.
772 } fault_con_subtype_;
773
774 typedef enum fault_acv_subtype_
775 {
776 ACV0 = (1U << 15), ///< 15.Illegal ring order (ACV0=IRO)
777 ACV1 = (1U << 14), ///< 3. Not in execute bracket (ACV1=OEB)
778 ACV2 = (1U << 13), ///< 6. No execute permission (ACV2=E-OFF)
779 ACV3 = (1U << 12), ///< 1. Not in read bracket (ACV3=ORB)
780 ACV4 = (1U << 11), ///< 4. No read permission (ACV4=R-OFF)
781 ACV5 = (1U << 10), ///< 2. Not in write bracket (ACV5=OWB)
782 ACV6 = (1U << 9), ///< 5. No write permission (ACV6=W-OFF)
783 ACV7 = (1U << 8), ///< 8. Call limiter fault (ACV7=NO GA)
784 ACV8 = (1U << 7), ///< 16.Out of call brackets (ACV8=OCB)
785 ACV9 = (1U << 6), ///< 9. Outward call (ACV9=OCALL)
786 ACV10 = (1U << 5), ///< 10.Bad outward call (ACV10=BOC)
787 ACV11 = (1U << 4), ///< 11.Inward return (ACV11=INRET)
788 ACV12 = (1U << 3), ///< 7. Invalid ring crossing (ACV12=CRT)
789 ACV13 = (1U << 2), ///< 12.Ring alarm (ACV13=RALR)
790 ACV14 = (1U << 1), ///< 13.Associative memory error
791 ACV15 = (1U << 0), ///< 14.Out of segment bounds (ACV15=OOSB)
792 flt_acv_FORCE = 0400000000000llu // Force enum size to 36 bits.
793 } fault_acv_subtype_;
794
795 typedef enum fault_ipr_subtype_
796 {
797 FR_ILL_OP = 0400000000000llu, // 0 a ILL OP
798 FR_ILL_MOD = 0200000000000llu, // 1 b ILL MOD
799 FR_ILL_SLV = 0100000000000llu, // 2 c ILL SLV
800 FR_ILL_PROC = 0040000000000llu, // 3 d ILL PROC
801 FR_ILL_PROC_MOD = 0240000000000llu, // 1,3 d ILL PROC | ILL MOD
802 FR_NEM = 0020000000000llu, // 4 e NEM
803 FR_OOB = 0010000000000llu, // 5 f OOB
804 FR_ILL_DIG = 0004000000000llu, // 6 g ILL DIG
805 FR_PROC_PARU = 0002000000000llu, // 7 h PROC PARU
806 FR_PROC_PARL = 0001000000000llu, // 8 i PROC PARU
807 FR_CON_A = 0000400000000llu, // 9 j $CON A
808 FR_CON_B = 0000200000000llu, // 10 k $CON B
809 FR_CON_C = 0000100000000llu, // 11 l $CON C
810 FR_CON_D = 0000040000000llu, // 12 m $CON D
811 FR_DA_ERR = 0000020000000llu, // 13 n DA ERR
812 FR_DA_ERR2 = 0000010000000llu // 14 o DA ERR2
813 } fault_ipr_subtype_;
814
815 typedef enum fault_cmd_subtype_
816 {
817 flt_cmd_lprpn_bits, // illegal bits in lprpn instruction
818 flt_cmd_not_control, // not control
819 flt_cmd_FORCE = 0400000000000llu // Force enum size to 36 bits.
820 } fault_cmd_subtype_;
821
822 typedef union _fault_subtype
823 {
824 fault_onc_subtype_ fault_onc_subtype;
825 fault_str_subtype_ fault_str_subtype;
826 fault_con_subtype_ fault_con_subtype;
827 fault_acv_subtype_ fault_acv_subtype;
828 fault_ipr_subtype_ fault_ipr_subtype;
829 fault_cmd_subtype_ fault_cmd_subtype;
830 word36 bits;
831 } _fault_subtype;
832
833 // Fault Register bits
834 enum _faultRegisterBits0
835 {
836 FR_IA_MASK = 017,
837 FR_IAA_SHIFT = 16, // 0000003600000llu,
838 FR_IAB_SHIFT = 12, // 0000000170000llu,
839 FR_IAC_SHIFT = 8, // 0000000007400llu,
840 FR_IAD_SHIFT = 4, // 0000000000360llu,
841
842 FR_CPAR_DIR = 0000000000010llu, // 32 p CPAR DIR
843 FR_CPAR_STR = 0000000000004llu, // 33 q CPAR STR
844 FR_CPAR_IA = 0000000000002llu, // 34 r CPAR IA
845 FR_CPAR_BLK = 0000000000001llu // 35 s CPAR BLK
846 };
847
848 enum _faultRegisterBits1
849 {
850 FR_PORT_A = 0400000000000llu, // 0 t PORT A
851 FR_PORT_B = 0200000000000llu, // 1 u PORT B
852 FR_PORT_C = 0100000000000llu, // 2 v PORT C
853 FR_PORT_D = 0040000000000llu, // 3 w PORT D
854 FR_WNO_BO = 0020000000000llu, // 4 x Cache Primary Directory WNO Buffer Overflow
855 FR_WNO_PAR = 0010000000000llu, // 5 y Write Notify (WNO) Parity Error on Port A, B, C or D.
856 FR_LEVEL_0 = 0004000000000llu, // 6 z Level 0
857 FR_LEVEL_1 = 0002000000000llu, // 7 A Level 1
858 FR_LEVEL_2 = 0001000000000llu, // 8 B Level 2
859 FR_LEVEL_3 = 0000400000000llu, // 0 C Level 3
860 FR_CDDMM = 0000200000000llu, // 10 D Cache Duplicate Directory Multiple Match
861 FR_PAR_SDWAM = 0000100000000llu, // 11 E SDWAM parity error
862 FR_PAR_PTWAM = 0000040000000llu // 12 F PTWAM parity error
863 };
864
865 enum _systemControllerIllegalActionCodes
866 {
867 SCIAC_NONE = 000,
868 SCIAC_NEA = 002,
869 SCIAC_SOC = 003,
870 SCIAC_PAR5 = 005,
871 SCIAC_PAR6 = 006,
872 SCIAC_PAR7 = 007,
873 SCIAC_NC = 010,
874 SCIAC_PNE = 011,
875 SCIAC_ILL_CMD = 012,
876 SCIAC_NR = 013,
877 SCIAC_PAR14 = 014,
878 SCIAC_PAR15 = 015,
879 SCIAC_PAR16 = 016,
880 SCIAC_PAR17 = 017
881 };
882
883
884 /////////////////////////////////////
885 //
886 // Interrupts
887 //
888
889 # define N_INTERRUPTS 32
890
891 /////////////////////////////////////
892 //
893 // Memory map
894 //
895
896 # define IOM_MBX_LOW 01200
897 # define IOM_MBX_LEN 02200
898 # define DN355_MBX_LOW 03400
899 # define DN355_MBX_LEN 03000
900
901 /////////////////////////////////////
902 //
903 // Opcodes
904 //
905
906 // MM's opcode stuff ...
907
908 // Opcodes with low bit (bit 27) == 0. Enum value is value of upper 9 bits.
909 typedef enum {
910 opcode0_mme = 0001U, // (1 decimal)
911 opcode0_drl = 0002U, // (2 decimal)
912 opcode0_mme2 = 0004U, // (4 decimal)
913 opcode0_mme3 = 0005U, // (5 decimal)
914 opcode0_mme4 = 0007U, // (7 decimal)
915 opcode0_nop = 0011U, // (9 decimal)
916 opcode0_puls1 = 0012U, // (10 decimal)
917 opcode0_puls2 = 0013U, // (11 decimal)
918 opcode0_cioc = 0015U, // (13 decimal)
919 opcode0_adlx0 = 0020U, // (16 decimal)
920 opcode0_adlx1 = 0021U, // (17 decimal)
921 opcode0_adlx2 = 0022U, // (18 decimal)
922 opcode0_adlx3 = 0023U, // (19 decimal)
923 opcode0_adlx4 = 0024U, // (20 decimal)
924 opcode0_adlx5 = 0025U, // (21 decimal)
925 opcode0_adlx6 = 0026U, // (22 decimal)
926 opcode0_adlx7 = 0027U, // (23 decimal)
927 opcode0_ldqc = 0032U, // (26 decimal)
928 opcode0_adl = 0033U, // (27 decimal)
929 opcode0_ldac = 0034U, // (28 decimal)
930 opcode0_adla = 0035U, // (29 decimal)
931 opcode0_adlq = 0036U, // (30 decimal)
932 opcode0_adlaq = 0037U, // (31 decimal)
933 opcode0_asx0 = 0040U, // (32 decimal)
934 opcode0_asx1 = 0041U, // (33 decimal)
935 opcode0_asx2 = 0042U, // (34 decimal)
936 opcode0_asx3 = 0043U, // (35 decimal)
937 opcode0_asx4 = 0044U, // (36 decimal)
938 opcode0_asx5 = 0045U, // (37 decimal)
939 opcode0_asx6 = 0046U, // (38 decimal)
940 opcode0_asx7 = 0047U, // (39 decimal)
941 opcode0_adwp0 = 0050U, // (40 decimal)
942 opcode0_adwp1 = 0051U, // (41 decimal)
943 opcode0_adwp2 = 0052U, // (42 decimal)
944 opcode0_adwp3 = 0053U, // (43 decimal)
945 opcode0_aos = 0054U, // (44 decimal)
946 opcode0_asa = 0055U, // (45 decimal)
947 opcode0_asq = 0056U, // (46 decimal)
948 opcode0_sscr = 0057U, // (47 decimal)
949 opcode0_adx0 = 0060U, // (48 decimal)
950 opcode0_adx1 = 0061U, // (49 decimal)
951 opcode0_adx2 = 0062U, // (50 decimal)
952 opcode0_adx3 = 0063U, // (51 decimal)
953 opcode0_adx4 = 0064U, // (52 decimal)
954 opcode0_adx5 = 0065U, // (53 decimal)
955 opcode0_adx6 = 0066U, // (54 decimal)
956 opcode0_adx7 = 0067U, // (55 decimal)
957 opcode0_awca = 0071U, // (57 decimal)
958 opcode0_awcq = 0072U, // (58 decimal)
959 opcode0_lreg = 0073U, // (59 decimal)
960 opcode0_ada = 0075U, // (61 decimal)
961 opcode0_adq = 0076U, // (62 decimal)
962 opcode0_adaq = 0077U, // (63 decimal)
963 opcode0_cmpx0 = 0100U, // (64 decimal)
964 opcode0_cmpx1 = 0101U, // (65 decimal)
965 opcode0_cmpx2 = 0102U, // (66 decimal)
966 opcode0_cmpx3 = 0103U, // (67 decimal)
967 opcode0_cmpx4 = 0104U, // (68 decimal)
968 opcode0_cmpx5 = 0105U, // (69 decimal)
969 opcode0_cmpx6 = 0106U, // (70 decimal)
970 opcode0_cmpx7 = 0107U, // (71 decimal)
971 opcode0_cwl = 0111U, // (73 decimal)
972 opcode0_cmpa = 0115U, // (77 decimal)
973 opcode0_cmpq = 0116U, // (78 decimal)
974 opcode0_cmpaq = 0117U, // (79 decimal)
975 opcode0_sblx0 = 0120U, // (80 decimal)
976 opcode0_sblx1 = 0121U, // (81 decimal)
977 opcode0_sblx2 = 0122U, // (82 decimal)
978 opcode0_sblx3 = 0123U, // (83 decimal)
979 opcode0_sblx4 = 0124U, // (84 decimal)
980 opcode0_sblx5 = 0125U, // (85 decimal)
981 opcode0_sblx6 = 0126U, // (86 decimal)
982 opcode0_sblx7 = 0127U, // (87 decimal)
983 opcode0_sbla = 0135U, // (93 decimal)
984 opcode0_sblq = 0136U, // (94 decimal)
985 opcode0_sblaq = 0137U, // (95 decimal)
986 opcode0_ssx0 = 0140U, // (96 decimal)
987 opcode0_ssx1 = 0141U, // (97 decimal)
988 opcode0_ssx2 = 0142U, // (98 decimal)
989 opcode0_ssx3 = 0143U, // (99 decimal)
990 opcode0_ssx4 = 0144U, // (100 decimal)
991 opcode0_ssx5 = 0145U, // (101 decimal)
992 opcode0_ssx6 = 0146U, // (102 decimal)
993 opcode0_ssx7 = 0147U, // (103 decimal)
994 opcode0_adwp4 = 0150U, // (104 decimal)
995 opcode0_adwp5 = 0151U, // (105 decimal)
996 opcode0_adwp6 = 0152U, // (106 decimal)
997 opcode0_adwp7 = 0153U, // (107 decimal)
998 opcode0_sdbr = 0154U, // (108 decimal)
999 opcode0_ssa = 0155U, // (109 decimal)
1000 opcode0_ssq = 0156U, // (110 decimal)
1001 opcode0_sbx0 = 0160U, // (112 decimal)
1002 opcode0_sbx1 = 0161U, // (113 decimal)
1003 opcode0_sbx2 = 0162U, // (114 decimal)
1004 opcode0_sbx3 = 0163U, // (115 decimal)
1005 opcode0_sbx4 = 0164U, // (116 decimal)
1006 opcode0_sbx5 = 0165U, // (117 decimal)
1007 opcode0_sbx6 = 0166U, // (118 decimal)
1008 opcode0_sbx7 = 0167U, // (119 decimal)
1009 opcode0_swca = 0171U, // (121 decimal)
1010 opcode0_swcq = 0172U, // (122 decimal)
1011 opcode0_lpri = 0173U, // (123 decimal)
1012 opcode0_sba = 0175U, // (125 decimal)
1013 opcode0_sbq = 0176U, // (126 decimal)
1014 opcode0_sbaq = 0177U, // (127 decimal)
1015 opcode0_cnax0 = 0200U, // (128 decimal)
1016 opcode0_cnax1 = 0201U, // (129 decimal)
1017 opcode0_cnax2 = 0202U, // (130 decimal)
1018 opcode0_cnax3 = 0203U, // (131 decimal)
1019 opcode0_cnax4 = 0204U, // (132 decimal)
1020 opcode0_cnax5 = 0205U, // (133 decimal)
1021 opcode0_cnax6 = 0206U, // (134 decimal)
1022 opcode0_cnax7 = 0207U, // (135 decimal)
1023 opcode0_cmk = 0211U, // (137 decimal)
1024 opcode0_absa = 0212U, // (138 decimal)
1025 opcode0_epaq = 0213U, // (139 decimal)
1026 opcode0_sznc = 0214U, // (140 decimal)
1027 opcode0_cnaa = 0215U, // (141 decimal)
1028 opcode0_cnaq = 0216U, // (142 decimal)
1029 opcode0_cnaaq = 0217U, // (143 decimal)
1030 opcode0_ldx0 = 0220U, // (144 decimal)
1031 opcode0_ldx1 = 0221U, // (145 decimal)
1032 opcode0_ldx2 = 0222U, // (146 decimal)
1033 opcode0_ldx3 = 0223U, // (147 decimal)
1034 opcode0_ldx4 = 0224U, // (148 decimal)
1035 opcode0_ldx5 = 0225U, // (149 decimal)
1036 opcode0_ldx6 = 0226U, // (150 decimal)
1037 opcode0_ldx7 = 0227U, // (151 decimal)
1038 opcode0_lbar = 0230U, // (152 decimal)
1039 opcode0_rsw = 0231U, // (153 decimal)
1040 opcode0_ldbr = 0232U, // (154 decimal)
1041 opcode0_rmcm = 0233U, // (155 decimal)
1042 opcode0_szn = 0234U, // (156 decimal)
1043 opcode0_lda = 0235U, // (157 decimal)
1044 opcode0_ldq = 0236U, // (158 decimal)
1045 opcode0_ldaq = 0237U, // (159 decimal)
1046 opcode0_orsx0 = 0240U, // (160 decimal)
1047 opcode0_orsx1 = 0241U, // (161 decimal)
1048 opcode0_orsx2 = 0242U, // (162 decimal)
1049 opcode0_orsx3 = 0243U, // (163 decimal)
1050 opcode0_orsx4 = 0244U, // (164 decimal)
1051 opcode0_orsx5 = 0245U, // (165 decimal)
1052 opcode0_orsx6 = 0246U, // (166 decimal)
1053 opcode0_orsx7 = 0247U, // (167 decimal)
1054 opcode0_spri0 = 0250U, // (168 decimal)
1055 opcode0_spbp1 = 0251U, // (169 decimal)
1056 opcode0_spri2 = 0252U, // (170 decimal)
1057 opcode0_spbp3 = 0253U, // (171 decimal)
1058 opcode0_spri = 0254U, // (172 decimal)
1059 opcode0_orsa = 0255U, // (173 decimal)
1060 opcode0_orsq = 0256U, // (174 decimal)
1061 opcode0_lsdp = 0257U, // (175 decimal)
1062 opcode0_orx0 = 0260U, // (176 decimal)
1063 opcode0_orx1 = 0261U, // (177 decimal)
1064 opcode0_orx2 = 0262U, // (178 decimal)
1065 opcode0_orx3 = 0263U, // (179 decimal)
1066 opcode0_orx4 = 0264U, // (180 decimal)
1067 opcode0_orx5 = 0265U, // (181 decimal)
1068 opcode0_orx6 = 0266U, // (182 decimal)
1069 opcode0_orx7 = 0267U, // (183 decimal)
1070 opcode0_tsp0 = 0270U, // (184 decimal)
1071 opcode0_tsp1 = 0271U, // (185 decimal)
1072 opcode0_tsp2 = 0272U, // (186 decimal)
1073 opcode0_tsp3 = 0273U, // (187 decimal)
1074 opcode0_ora = 0275U, // (189 decimal)
1075 opcode0_orq = 0276U, // (190 decimal)
1076 opcode0_oraq = 0277U, // (191 decimal)
1077 opcode0_canx0 = 0300U, // (192 decimal)
1078 opcode0_canx1 = 0301U, // (193 decimal)
1079 opcode0_canx2 = 0302U, // (194 decimal)
1080 opcode0_canx3 = 0303U, // (195 decimal)
1081 opcode0_canx4 = 0304U, // (196 decimal)
1082 opcode0_canx5 = 0305U, // (197 decimal)
1083 opcode0_canx6 = 0306U, // (198 decimal)
1084 opcode0_canx7 = 0307U, // (199 decimal)
1085 opcode0_eawp0 = 0310U, // (200 decimal)
1086 opcode0_easp0 = 0311U, // (201 decimal)
1087 opcode0_eawp2 = 0312U, // (202 decimal)
1088 opcode0_easp2 = 0313U, // (203 decimal)
1089 opcode0_cana = 0315U, // (205 decimal)
1090 opcode0_canq = 0316U, // (206 decimal)
1091 opcode0_canaq = 0317U, // (207 decimal)
1092 opcode0_lcx0 = 0320U, // (208 decimal)
1093 opcode0_lcx1 = 0321U, // (209 decimal)
1094 opcode0_lcx2 = 0322U, // (210 decimal)
1095 opcode0_lcx3 = 0323U, // (211 decimal)
1096 opcode0_lcx4 = 0324U, // (212 decimal)
1097 opcode0_lcx5 = 0325U, // (213 decimal)
1098 opcode0_lcx6 = 0326U, // (214 decimal)
1099 opcode0_lcx7 = 0327U, // (215 decimal)
1100 opcode0_eawp4 = 0330U, // (216 decimal)
1101 opcode0_easp4 = 0331U, // (217 decimal)
1102 opcode0_eawp6 = 0332U, // (218 decimal)
1103 opcode0_easp6 = 0333U, // (219 decimal)
1104 opcode0_lca = 0335U, // (221 decimal)
1105 opcode0_lcq = 0336U, // (222 decimal)
1106 opcode0_lcaq = 0337U, // (223 decimal)
1107 opcode0_ansx0 = 0340U, // (224 decimal)
1108 opcode0_ansx1 = 0341U, // (225 decimal)
1109 opcode0_ansx2 = 0342U, // (226 decimal)
1110 opcode0_ansx3 = 0343U, // (227 decimal)
1111 opcode0_ansx4 = 0344U, // (228 decimal)
1112 opcode0_ansx5 = 0345U, // (229 decimal)
1113 opcode0_ansx6 = 0346U, // (230 decimal)
1114 opcode0_ansx7 = 0347U, // (231 decimal)
1115 opcode0_epp0 = 0350U, // (232 decimal)
1116 opcode0_epbp1 = 0351U, // (233 decimal)
1117 opcode0_epp2 = 0352U, // (234 decimal)
1118 opcode0_epbp3 = 0353U, // (235 decimal)
1119 opcode0_stac = 0354U, // (236 decimal)
1120 opcode0_ansa = 0355U, // (237 decimal)
1121 opcode0_ansq = 0356U, // (238 decimal)
1122 opcode0_stcd = 0357U, // (239 decimal)
1123 opcode0_anx0 = 0360U, // (240 decimal)
1124 opcode0_anx1 = 0361U, // (241 decimal)
1125 opcode0_anx2 = 0362U, // (242 decimal)
1126 opcode0_anx3 = 0363U, // (243 decimal)
1127 opcode0_anx4 = 0364U, // (244 decimal)
1128 opcode0_anx5 = 0365U, // (245 decimal)
1129 opcode0_anx6 = 0366U, // (246 decimal)
1130 opcode0_anx7 = 0367U, // (247 decimal)
1131 opcode0_epp4 = 0370U, // (248 decimal)
1132 opcode0_epbp5 = 0371U, // (249 decimal)
1133 opcode0_epp6 = 0372U, // (250 decimal)
1134 opcode0_epbp7 = 0373U, // (251 decimal)
1135 opcode0_ana = 0375U, // (253 decimal)
1136 opcode0_anq = 0376U, // (254 decimal)
1137 opcode0_anaq = 0377U, // (255 decimal)
1138 opcode0_mpf = 0401U, // (257 decimal)
1139 opcode0_mpy = 0402U, // (258 decimal)
1140 opcode0_cmg = 0405U, // (261 decimal)
1141 opcode0_lde = 0411U, // (265 decimal)
1142 opcode0_rscr = 0413U, // (267 decimal)
1143 opcode0_ade = 0415U, // (269 decimal)
1144 opcode0_ufm = 0421U, // (273 decimal)
1145 opcode0_dufm = 0423U, // (275 decimal)
1146 opcode0_fcmg = 0425U, // (277 decimal)
1147 opcode0_dfcmg = 0427U, // (279 decimal)
1148 opcode0_fszn = 0430U, // (280 decimal)
1149 opcode0_fld = 0431U, // (281 decimal)
1150 opcode0_dfld = 0433U, // (283 decimal)
1151 opcode0_ufa = 0435U, // (285 decimal)
1152 opcode0_dufa = 0437U, // (287 decimal)
1153 opcode0_sxl0 = 0440U, // (288 decimal)
1154 opcode0_sxl1 = 0441U, // (289 decimal)
1155 opcode0_sxl2 = 0442U, // (290 decimal)
1156 opcode0_sxl3 = 0443U, // (291 decimal)
1157 opcode0_sxl4 = 0444U, // (292 decimal)
1158 opcode0_sxl5 = 0445U, // (293 decimal)
1159 opcode0_sxl6 = 0446U, // (294 decimal)
1160 opcode0_sxl7 = 0447U, // (295 decimal)
1161 opcode0_stz = 0450U, // (296 decimal)
1162 opcode0_smic = 0451U, // (297 decimal)
1163 opcode0_scpr = 0452U, // (298 decimal)
1164 opcode0_stt = 0454U, // (300 decimal)
1165 opcode0_fst = 0455U, // (301 decimal)
1166 opcode0_ste = 0456U, // (302 decimal)
1167 opcode0_dfst = 0457U, // (303 decimal)
1168 opcode0_fmp = 0461U, // (305 decimal)
1169 opcode0_dfmp = 0463U, // (307 decimal)
1170 opcode0_fstr = 0470U, // (312 decimal)
1171 opcode0_frd = 0471U, // (313 decimal)
1172 opcode0_dfstr = 0472U, // (314 decimal)
1173 opcode0_dfrd = 0473U, // (315 decimal)
1174 opcode0_fad = 0475U, // (317 decimal)
1175 opcode0_dfad = 0477U, // (319 decimal)
1176 opcode0_rpl = 0500U, // (320 decimal)
1177 opcode0_bcd = 0505U, // (325 decimal)
1178 opcode0_div = 0506U, // (326 decimal)
1179 opcode0_dvf = 0507U, // (327 decimal)
1180 opcode0_fneg = 0513U, // (331 decimal)
1181 opcode0_fcmp = 0515U, // (333 decimal)
1182 opcode0_dfcmp = 0517U, // (335 decimal)
1183 opcode0_rpt = 0520U, // (336 decimal)
1184 opcode0_fdi = 0525U, // (341 decimal)
1185 opcode0_dfdi = 0527U, // (343 decimal)
1186 opcode0_neg = 0531U, // (345 decimal)
1187 opcode0_cams = 0532U, // (346 decimal)
1188 opcode0_negl = 0533U, // (347 decimal)
1189 opcode0_ufs = 0535U, // (349 decimal)
1190 opcode0_dufs = 0537U, // (351 decimal)
1191 opcode0_sprp0 = 0540U, // (352 decimal)
1192 opcode0_sprp1 = 0541U, // (353 decimal)
1193 opcode0_sprp2 = 0542U, // (354 decimal)
1194 opcode0_sprp3 = 0543U, // (355 decimal)
1195 opcode0_sprp4 = 0544U, // (356 decimal)
1196 opcode0_sprp5 = 0545U, // (357 decimal)
1197 opcode0_sprp6 = 0546U, // (358 decimal)
1198 opcode0_sprp7 = 0547U, // (359 decimal)
1199 opcode0_sbar = 0550U, // (360 decimal)
1200 opcode0_stba = 0551U, // (361 decimal)
1201 opcode0_stbq = 0552U, // (362 decimal)
1202 opcode0_smcm = 0553U, // (363 decimal)
1203 opcode0_stc1 = 0554U, // (364 decimal)
1204 opcode0_ssdp = 0557U, // (367 decimal)
1205 opcode0_rpd = 0560U, // (368 decimal)
1206 opcode0_fdv = 0565U, // (373 decimal)
1207 opcode0_dfdv = 0567U, // (375 decimal)
1208 opcode0_fno = 0573U, // (379 decimal)
1209 opcode0_fsb = 0575U, // (381 decimal)
1210 opcode0_dfsb = 0577U, // (383 decimal)
1211 opcode0_tze = 0600U, // (384 decimal)
1212 opcode0_tnz = 0601U, // (385 decimal)
1213 opcode0_tnc = 0602U, // (386 decimal)
1214 opcode0_trc = 0603U, // (387 decimal)
1215 opcode0_tmi = 0604U, // (388 decimal)
1216 opcode0_tpl = 0605U, // (389 decimal)
1217 opcode0_ttf = 0607U, // (391 decimal)
1218 opcode0_rtcd = 0610U, // (392 decimal)
1219 opcode0_rcu = 0613U, // (395 decimal)
1220 opcode0_teo = 0614U, // (396 decimal)
1221 opcode0_teu = 0615U, // (397 decimal)
1222 opcode0_dis = 0616U, // (398 decimal)
1223 opcode0_tov = 0617U, // (399 decimal)
1224 opcode0_eax0 = 0620U, // (400 decimal)
1225 opcode0_eax1 = 0621U, // (401 decimal)
1226 opcode0_eax2 = 0622U, // (402 decimal)
1227 opcode0_eax3 = 0623U, // (403 decimal)
1228 opcode0_eax4 = 0624U, // (404 decimal)
1229 opcode0_eax5 = 0625U, // (405 decimal)
1230 opcode0_eax6 = 0626U, // (406 decimal)
1231 opcode0_eax7 = 0627U, // (407 decimal)
1232 opcode0_ret = 0630U, // (408 decimal)
1233 opcode0_rccl = 0633U, // (411 decimal)
1234 opcode0_ldi = 0634U, // (412 decimal)
1235 opcode0_eaa = 0635U, // (413 decimal)
1236 opcode0_eaq = 0636U, // (414 decimal)
1237 opcode0_ldt = 0637U, // (415 decimal)
1238 opcode0_ersx0 = 0640U, // (416 decimal)
1239 opcode0_ersx1 = 0641U, // (417 decimal)
1240 opcode0_ersx2 = 0642U, // (418 decimal)
1241 opcode0_ersx3 = 0643U, // (419 decimal)
1242 opcode0_ersx4 = 0644U, // (420 decimal)
1243 opcode0_ersx5 = 0645U, // (421 decimal)
1244 opcode0_ersx6 = 0646U, // (422 decimal)
1245 opcode0_ersx7 = 0647U, // (423 decimal)
1246 opcode0_spri4 = 0650U, // (424 decimal)
1247 opcode0_spbp5 = 0651U, // (425 decimal)
1248 opcode0_spri6 = 0652U, // (426 decimal)
1249 opcode0_spbp7 = 0653U, // (427 decimal)
1250 opcode0_stacq = 0654U, // (428 decimal)
1251 opcode0_ersa = 0655U, // (429 decimal)
1252 opcode0_ersq = 0656U, // (430 decimal)
1253 opcode0_scu = 0657U, // (431 decimal)
1254 opcode0_erx0 = 0660U, // (432 decimal)
1255 opcode0_erx1 = 0661U, // (433 decimal)
1256 opcode0_erx2 = 0662U, // (434 decimal)
1257 opcode0_erx3 = 0663U, // (435 decimal)
1258 opcode0_erx4 = 0664U, // (436 decimal)
1259 opcode0_erx5 = 0665U, // (437 decimal)
1260 opcode0_erx6 = 0666U, // (438 decimal)
1261 opcode0_erx7 = 0667U, // (439 decimal)
1262 opcode0_tsp4 = 0670U, // (440 decimal)
1263 opcode0_tsp5 = 0671U, // (441 decimal)
1264 opcode0_tsp6 = 0672U, // (442 decimal)
1265 opcode0_tsp7 = 0673U, // (443 decimal)
1266 opcode0_lcpr = 0674U, // (444 decimal)
1267 opcode0_era = 0675U, // (445 decimal)
1268 opcode0_erq = 0676U, // (446 decimal)
1269 opcode0_eraq = 0677U, // (447 decimal)
1270 opcode0_tsx0 = 0700U, // (448 decimal)
1271 opcode0_tsx1 = 0701U, // (449 decimal)
1272 opcode0_tsx2 = 0702U, // (450 decimal)
1273 opcode0_tsx3 = 0703U, // (451 decimal)
1274 opcode0_tsx4 = 0704U, // (452 decimal)
1275 opcode0_tsx5 = 0705U, // (453 decimal)
1276 opcode0_tsx6 = 0706U, // (454 decimal)
1277 opcode0_tsx7 = 0707U, // (455 decimal)
1278 opcode0_tra = 0710U, // (456 decimal)
1279 opcode0_call6 = 0713U, // (459 decimal)
1280 opcode0_tss = 0715U, // (461 decimal)
1281 opcode0_xec = 0716U, // (462 decimal)
1282 opcode0_xed = 0717U, // (463 decimal)
1283 opcode0_lxl0 = 0720U, // (464 decimal)
1284 opcode0_lxl1 = 0721U, // (465 decimal)
1285 opcode0_lxl2 = 0722U, // (466 decimal)
1286 opcode0_lxl3 = 0723U, // (467 decimal)
1287 opcode0_lxl4 = 0724U, // (468 decimal)
1288 opcode0_lxl5 = 0725U, // (469 decimal)
1289 opcode0_lxl6 = 0726U, // (470 decimal)
1290 opcode0_lxl7 = 0727U, // (471 decimal)
1291 opcode0_ars = 0731U, // (473 decimal)
1292 opcode0_qrs = 0732U, // (474 decimal)
1293 opcode0_lrs = 0733U, // (475 decimal)
1294 opcode0_als = 0735U, // (477 decimal)
1295 opcode0_qls = 0736U, // (478 decimal)
1296 opcode0_lls = 0737U, // (479 decimal)
1297 opcode0_stx0 = 0740U, // (480 decimal)
1298 opcode0_stx1 = 0741U, // (481 decimal)
1299 opcode0_stx2 = 0742U, // (482 decimal)
1300 opcode0_stx3 = 0743U, // (483 decimal)
1301 opcode0_stx4 = 0744U, // (484 decimal)
1302 opcode0_stx5 = 0745U, // (485 decimal)
1303 opcode0_stx6 = 0746U, // (486 decimal)
1304 opcode0_stx7 = 0747U, // (487 decimal)
1305 opcode0_stc2 = 0750U, // (488 decimal)
1306 opcode0_stca = 0751U, // (489 decimal)
1307 opcode0_stcq = 0752U, // (490 decimal)
1308 opcode0_sreg = 0753U, // (491 decimal)
1309 opcode0_sti = 0754U, // (492 decimal)
1310 opcode0_sta = 0755U, // (493 decimal)
1311 opcode0_stq = 0756U, // (494 decimal)
1312 opcode0_staq = 0757U, // (495 decimal)
1313 opcode0_lprp0 = 0760U, // (496 decimal)
1314 opcode0_lprp1 = 0761U, // (497 decimal)
1315 opcode0_lprp2 = 0762U, // (498 decimal)
1316 opcode0_lprp3 = 0763U, // (499 decimal)
1317 opcode0_lprp4 = 0764U, // (500 decimal)
1318 opcode0_lprp5 = 0765U, // (501 decimal)
1319 opcode0_lprp6 = 0766U, // (502 decimal)
1320 opcode0_lprp7 = 0767U, // (503 decimal)
1321 opcode0_arl = 0771U, // (505 decimal)
1322 opcode0_qrl = 0772U, // (506 decimal)
1323 opcode0_lrl = 0773U, // (507 decimal)
1324 opcode0_gtb = 0774U, // (508 decimal)
1325 opcode0_alr = 0775U, // (509 decimal)
1326 opcode0_qlr = 0776U, // (510 decimal)
1327 opcode0_llr = 0777U // (511 decimal)
1328 } opcode0_t;
1329
1330 // Opcodes with low bit (bit 27) == 1. Enum value is value of upper 9 bits.
1331 typedef enum {
1332 opcode1_mve = 0020U, // (16 decimal)
1333 opcode1_mvne = 0024U, // (20 decimal)
1334 opcode1_csl = 0060U, // (48 decimal)
1335 opcode1_csr = 0061U, // (49 decimal)
1336 opcode1_sztl = 0064U, // (52 decimal)
1337 opcode1_sztr = 0065U, // (53 decimal)
1338 opcode1_cmpb = 0066U, // (54 decimal)
1339 opcode1_mlr = 0100U, // (64 decimal)
1340 opcode1_mrl = 0101U, // (65 decimal)
1341 opcode1_cmpc = 0106U, // (70 decimal)
1342 opcode1_scd = 0120U, // (80 decimal)
1343 opcode1_scdr = 0121U, // (81 decimal)
1344 opcode1_scm = 0124U, // (84 decimal)
1345 opcode1_scmr = 0125U, // (85 decimal)
1346 opcode1_sptr = 0154U, // (108 decimal)
1347 opcode1_mvt = 0160U, // (112 decimal)
1348 opcode1_tct = 0164U, // (116 decimal)
1349 opcode1_tctr = 0165U, // (117 decimal)
1350 opcode1_lptr = 0173U, // (123 decimal)
1351 opcode1_ad2d = 0202U, // (130 decimal)
1352 opcode1_sb2d = 0203U, // (131 decimal)
1353 opcode1_mp2d = 0206U, // (134 decimal)
1354 opcode1_dv2d = 0207U, // (135 decimal)
1355 opcode1_ad3d = 0222U, // (146 decimal)
1356 opcode1_sb3d = 0223U, // (147 decimal)
1357 opcode1_mp3d = 0226U, // (150 decimal)
1358 opcode1_dv3d = 0227U, // (151 decimal)
1359 opcode1_lsdr = 0232U, // (154 decimal)
1360 opcode1_spbp0 = 0250U, // (168 decimal)
1361 opcode1_spri1 = 0251U, // (169 decimal)
1362 opcode1_spbp2 = 0252U, // (170 decimal)
1363 opcode1_spri3 = 0253U, // (171 decimal)
1364 opcode1_ssdr = 0254U, // (172 decimal)
1365 opcode1_lptp = 0257U, // (175 decimal)
1366 opcode1_mvn = 0300U, // (192 decimal)
1367 opcode1_btd = 0301U, // (193 decimal)
1368 opcode1_cmpn = 0303U, // (195 decimal)
1369 opcode1_dtb = 0305U, // (197 decimal)
1370 opcode1_easp1 = 0310U, // (200 decimal)
1371 opcode1_eawp1 = 0311U, // (201 decimal)
1372 opcode1_easp3 = 0312U, // (202 decimal)
1373 opcode1_eawp3 = 0313U, // (203 decimal)
1374 opcode1_easp5 = 0330U, // (216 decimal)
1375 opcode1_eawp5 = 0331U, // (217 decimal)
1376 opcode1_easp7 = 0332U, // (218 decimal)
1377 opcode1_eawp7 = 0333U, // (219 decimal)
1378 opcode1_epbp0 = 0350U, // (232 decimal)
1379 opcode1_epp1 = 0351U, // (233 decimal)
1380 opcode1_epbp2 = 0352U, // (234 decimal)
1381 opcode1_epp3 = 0353U, // (235 decimal)
1382 opcode1_epbp4 = 0370U, // (248 decimal)
1383 opcode1_epp5 = 0371U, // (249 decimal)
1384 opcode1_epbp6 = 0372U, // (250 decimal)
1385 opcode1_epp7 = 0373U, // (251 decimal)
1386 opcode1_sareg = 0443U, // (291 decimal)
1387 opcode1_spl = 0447U, // (295 decimal)
1388 opcode1_lareg = 0463U, // (307 decimal)
1389 opcode1_lpl = 0467U, // (311 decimal)
1390 opcode1_a9bd = 0500U, // (320 decimal)
1391 opcode1_a6bd = 0501U, // (321 decimal)
1392 opcode1_a4bd = 0502U, // (322 decimal)
1393 opcode1_abd = 0503U, // (323 decimal)
1394 opcode1_awd = 0507U, // (327 decimal)
1395 opcode1_s9bd = 0520U, // (336 decimal)
1396 opcode1_s6bd = 0521U, // (337 decimal)
1397 opcode1_s4bd = 0522U, // (338 decimal)
1398 opcode1_sbd = 0523U, // (339 decimal)
1399 opcode1_swd = 0527U, // (343 decimal)
1400 opcode1_camp = 0532U, // (346 decimal)
1401 opcode1_ara0 = 0540U, // (352 decimal)
1402 opcode1_ara1 = 0541U, // (353 decimal)
1403 opcode1_ara2 = 0542U, // (354 decimal)
1404 opcode1_ara3 = 0543U, // (355 decimal)
1405 opcode1_ara4 = 0544U, // (356 decimal)
1406 opcode1_ara5 = 0545U, // (357 decimal)
1407 opcode1_ara6 = 0546U, // (358 decimal)
1408 opcode1_ara7 = 0547U, // (359 decimal)
1409 opcode1_sptp = 0557U, // (367 decimal)
1410 opcode1_aar0 = 0560U, // (368 decimal)
1411 opcode1_aar1 = 0561U, // (369 decimal)
1412 opcode1_aar2 = 0562U, // (370 decimal)
1413 opcode1_aar3 = 0563U, // (371 decimal)
1414 opcode1_aar4 = 0564U, // (372 decimal)
1415 opcode1_aar5 = 0565U, // (373 decimal)
1416 opcode1_aar6 = 0566U, // (374 decimal)
1417 opcode1_aar7 = 0567U, // (375 decimal)
1418 opcode1_trtn = 0600U, // (384 decimal)
1419 opcode1_trtf = 0601U, // (385 decimal)
1420 opcode1_tmoz = 0604U, // (388 decimal)
1421 opcode1_tpnz = 0605U, // (389 decimal)
1422 opcode1_ttn = 0606U, // (390 decimal)
1423 opcode1_arn0 = 0640U, // (416 decimal)
1424 opcode1_arn1 = 0641U, // (417 decimal)
1425 opcode1_arn2 = 0642U, // (418 decimal)
1426 opcode1_arn3 = 0643U, // (419 decimal)
1427 opcode1_arn4 = 0644U, // (420 decimal)
1428 opcode1_arn5 = 0645U, // (421 decimal)
1429 opcode1_arn6 = 0646U, // (422 decimal)
1430 opcode1_arn7 = 0647U, // (423 decimal)
1431 opcode1_spbp4 = 0650U, // (424 decimal)
1432 opcode1_spri5 = 0651U, // (425 decimal)
1433 opcode1_spbp6 = 0652U, // (426 decimal)
1434 opcode1_spri7 = 0653U, // (427 decimal)
1435 opcode1_nar0 = 0660U, // (432 decimal)
1436 opcode1_nar1 = 0661U, // (433 decimal)
1437 opcode1_nar2 = 0662U, // (434 decimal)
1438 opcode1_nar3 = 0663U, // (435 decimal)
1439 opcode1_nar4 = 0664U, // (436 decimal)
1440 opcode1_nar5 = 0665U, // (437 decimal)
1441 opcode1_nar6 = 0666U, // (438 decimal)
1442 opcode1_nar7 = 0667U, // (439 decimal)
1443 opcode1_sar0 = 0740U, // (480 decimal)
1444 opcode1_sar1 = 0741U, // (481 decimal)
1445 opcode1_sar2 = 0742U, // (482 decimal)
1446 opcode1_sar3 = 0743U, // (483 decimal)
1447 opcode1_sar4 = 0744U, // (484 decimal)
1448 opcode1_sar5 = 0745U, // (485 decimal)
1449 opcode1_sar6 = 0746U, // (486 decimal)
1450 opcode1_sar7 = 0747U, // (487 decimal)
1451 opcode1_sra = 0754U, // (492 decimal)
1452 opcode1_lar0 = 0760U, // (496 decimal)
1453 opcode1_lar1 = 0761U, // (497 decimal)
1454 opcode1_lar2 = 0762U, // (498 decimal)
1455 opcode1_lar3 = 0763U, // (499 decimal)
1456 opcode1_lar4 = 0764U, // (500 decimal)
1457 opcode1_lar5 = 0765U, // (501 decimal)
1458 opcode1_lar6 = 0766U, // (502 decimal)
1459 opcode1_lar7 = 0767U, // (503 decimal)
1460 opcode1_lra = 0774U // (508 decimal)
1461 } opcode1_t;
1462
1463 /////////////////////////////////////
1464 //
1465 // History registers
1466 //
1467
1468 enum { N_HIST_SETS = 4 };
1469 # ifdef DPS8M
1470 enum { N_HIST_SIZE = 64 };
1471 # endif
1472 # ifdef L68
1473 enum { N_HIST_SIZE = 16 };
1474 # endif
1475
1476 // Bit in CU history register word 0
1477
1478 // cu_hist_t flags
1479 enum
1480 {
1481 CU_HIST_PIA = 0400000000000, // 0 Prepare instruction address
1482 CU_HIST_POA = 0200000000000, // 1 Prepare operand address
1483 CU_HIST_RIW = 0100000000000, // 2 Request indirect word
1484 CU_HIST_SIW = 0040000000000, // 3 Restore indirect word
1485 CU_HIST_POT = 0020000000000, // 4 Prepare operand tally (indirect tally chain)
1486 CU_HIST_PON = 0010000000000, // 5 Prepare operand no tally (as for POT except no chain)
1487 CU_HIST_RAW = 0004000000000, // 6 Request read-alter-rewrite word
1488 CU_HIST_SAW = 0002000000000, // 7 Restore read-later-rewrite word
1489 CU_HIST_TRGO = 0001000000000, // 8 Transfer GO (conditions met)
1490 CU_HIST_XDE = 0000400000000, // 9 Execute XED even instruction
1491 CU_HIST_XDO = 0000200000000, // 10 Execute XED odd instruction
1492 CU_HIST_IC = 0000100000000, // 11 Execute odd instruction of the current pair
1493 CU_HIST_RPTS = 0000040000000, // 12 Execute a repeat instruction
1494 CU_HIST_PORTF = 0000020000000, // 13 Memory cycle to port on previous cycle
1495 CU_HIST_INTERNAL = 0000010000000, // 14 Memory cycle to cache or direct on previous cycle
1496 CU_HIST_PAI = 0000004000000, // 15 Prepare interrupt address
1497 CU_HIST_PFA = 0000002000000, // 16 Prepare fault address
1498 CU_HIST_PRIV = 0000001000000 // 17 In privileged mode
1499 };
1500
1501 // cu_hist_t flags2
1502 enum
1503 {
1504 CU_HIST_XINT = 0100, // 29 Execute instruction
1505 CU_HIST_IFT = 0040, // 30 Perform an instruction fetch
1506 CU_HIST_CRD = 0020, // 31 Cache read, this CU cycle
1507 CU_HIST_MRD = 0010, // 32 Memory read, this CU cycle
1508 CU_HIST_MSTO = 0004, // 33 Memory store, this CU cycle
1509 CU_HIST_PIB = 0002, // 34 Memory port interface busy
1510 };
1511
1512 enum
1513 {
1514 DU_FANLD1 = 0400000000000, // 0 Alpha-num load desc l (complemented)
1515 DU_FANLD2 = 0200000000000, // 1 Alpha-num load desc 2 (complemented)
1516 DU_FANSTR = 0100000000000, // 2 Alpha-num store (complemented)
1517 DU_FLDWRT1 = 0040000000000, // 3 Load re-write reg l (complemented)
1518 DU_FLDWRT2 = 0020000000000, // 4 Load re-write reg 2 (complemented)
1519 DU_FNLD1 = 0010000000000, // 5 Numeric load desc l (complemented)
1520 DU_FNLD2 = 0004000000000, // 6 Numeric load desc 2 (complemented)
1521 DU_NOSEQF = 0002000000000, // 7 End sequence flag
1522 DU_FDUD = 0001000000000, // 8 Decimal unit idle (complemented)
1523 DU_FGSTR = 0000400000000, // 9 General store flag (complemented)
1524 DU_NOSEQ = 0000200000000, // 10 End of sequence (complemented)
1525 DU_NINE = 0000100000000, // 11 9-bit character operation
1526 DU_SIX = 0000040000000, // 12 6-bit character operation
1527 DU_FOUR = 0000020000000, // 13 4-bit character operation
1528 DU_DUBIT = 0000010000000, // 14 Bit operation
1529 DU_UWORD = 0000004000000, // 15 Word operation
1530 DU_PTR1 = 0000002000000, // 16 Select ptr l
1531 DU_PTR2 = 0000001000000, // 17 Select ptr 2
1532 DU_PRT3 = 0000000400000, // 18 Select ptr 3
1533 DU_FPOP = 0000000200000, // 19 Prepare operand pointer
1534 DU_GEAM = 0000000100000, // 20 Add timing gates (complemented)
1535 DU_LPD12 = 0000000040000, // 21 Load pointer l or 2 (complemented)
1536 DU_GEMAE = 0000000020000, // 22 Multiply gates A E (complemented)
1537 DU_BTDS = 0000000010000, // 23 Binary to decimal gates (complemented)
1538 DU_SP15 = 0000000004000, // 24 Align cycles (complemented)
1539 DU_FSWEQ = 0000000002000, // 25 Single word sequence flag (complemented)
1540 DU_FGCH = 0000000001000, // 26 Character cycle (complemented)
1541 DU_DFRST = 0000000000400, // 27 Processing descriptor for first time
1542 DU_EXH = 0000000000200, // 28 Exhaust
1543 DU_FGADO = 0000000000100, // 29 Add cycle (complemented)
1544 DU_INTRPTD = 0000000000040, // 30 Interrupted
1545 DU_GLDP2 = 0000000000020, // 31 Load DP2
1546 DU_GEMC = 0000000000010, // 32 Multiply gate C
1547 DU_GBDA = 0000000000004, // 33 Binary to decimal gate A
1548 DU_GSP5 = 0000000000002 // 34 Final align cycle
1549 };
1550
1551 // apu_hist_t flags
1552 enum
1553 {
1554 APU_PIA_OVF = 04000000, // 15 PIA Page overflow
1555 APU_PIA_OOB = 02000000, // 16 PIA out of segment bounds
1556 APU_FDSPTW = 01000000, // 17 Fetch descriptor segment PTW
1557 APU_MDSPTW = 00400000, // 18 Descriptor segment PTW is modified
1558 APU_FSDW = 00200000, // 19 Fetch SDW
1559 APU_FPTW = 00100000, // 20 Fetch PTW
1560 APU_FPTW2 = 00040000, // 21 Fetch pre-page PTW
1561 APU_MPTW = 00020000, // 22 PTW modified
1562 APU_FANP = 00010000, // 23 Final address nonpaged
1563 APU_FAP = 00004000, // 24 Final address paged
1564 APU_MTCHSDW = 00002000, // 25 SDW match found
1565 APU_SDWMF = 00001000, // 26 SDW match found and used
1566 // BSY Data source for ESN
1567 APU_BSY_IC = 00000000, // 27-28 00 = from ppr.ic
1568 APU_BSY_TSE = 00000200, // 27-28 01 = from prn.tsr
1569 APU_BSY_SWR = 00000400, // 27-28 10 = from tpr.swr
1570 APU_BSY_CA = 00000600, // 27-28 11 = from tpr.ca
1571 APU_MTCHPTW = 00000100, // 29 PTW match found (AM)
1572 //APU_PTWMF = 00000000, // 30-31 PTW match found (AM) and used
1573 //APU_PTWAM = 00000000 // 32-35 PTW AM direct address (ZCA bits 4-7)
1574 };
1575
1576 // apu_hist_t flags2
1577 enum
1578 {
1579 APU_SDWME = 0400, // 27 SDW match error
1580 //APU_SDWLVL = 0000, // 28-29 SDW match level count (0 = Level A)
1581 APU_CACHE = 0040, // 30 Cache used this cycle
1582 APU_PTW = 0020, // 31 match error
1583 //APU_PTWLVL = 0000, // 32-33 PTW match level count (0 = level A)
1584 APU_FLTHLD = 0002, // 34 A directed fault or access violation fault is waiting
1585 // bit 35 is marked 'w' but undocumented
1586 };
1587
1588 # ifdef DPS8M
1589 enum { CU_HIST_REG = 0, DU_OU_HIST_REG = 1, APU_HIST_REG = 2, EAPU_HIST_REG = 3 };
1590 # endif
1591 # ifdef L68
1592 enum { CU_HIST_REG = 0, DU_HIST_REG = 1, OU_HIST_REG = 2, APU_HIST_REG = 3 };
1593 # endif
1594
1595 #endif // DPS8_HW_CONSTS_H
1596