1 #ifndef IVL_xilinx_H 2 #define IVL_xilinx_H 3 /* 4 * Copyright (c) 2003-2014 Stephen Williams (steve at icarus.com) 5 * 6 * This source code is free software; you can redistribute it 7 * and/or modify it in source code form under the terms of the GNU 8 * General Public License as published by the Free Software 9 * Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 */ 21 22 /* 23 * This header file includes XILINX library support functions. They 24 * manage the creation and reference of cells from the library. Use 25 * the xilinx_cell_* functions to get an edif_cell_t from the 26 * library. The function will create the cell in the library if 27 * needed, or will return the existing cell if it was already called. 28 */ 29 # include "edif.h" 30 31 32 /* === BUF Devices === */ 33 34 /* Buffer types of devices have the BUF_O and BUF_I pin 35 assignments. The BUF, INV, and certain specialized devices fit in 36 this category. */ 37 extern edif_cell_t xilinx_cell_buf (edif_xlibrary_t xlib); 38 extern edif_cell_t xilinx_cell_bufe(edif_xlibrary_t xlib); 39 extern edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib); 40 extern edif_cell_t xilinx_cell_buft(edif_xlibrary_t xlib); 41 extern edif_cell_t xilinx_cell_inv (edif_xlibrary_t xlib); 42 extern edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib); 43 extern edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib); 44 #define BUF_O 0 45 #define BUF_I 1 46 /* Only bufe and buft buffers have this input. */ 47 #define BUF_T 2 48 49 /* === LUT Devices === */ 50 51 /* Most Xilinx devices have LUT2/3/4 devices that take, respectively, 52 2, 3 or 4 inputs. All forms have a single bit output. Also, the 53 real behavior of the device will need to be specified by an INIT 54 parameter string. */ 55 extern edif_cell_t xilinx_cell_lut2(edif_xlibrary_t xlib); 56 extern edif_cell_t xilinx_cell_lut3(edif_xlibrary_t xlib); 57 extern edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib); 58 #define LUT_O 0 59 #define LUT_I0 1 60 #define LUT_I1 2 61 #define LUT_I2 3 62 #define LUT_I3 4 63 64 65 /* === Flip-Flop Devices === */ 66 67 /* 68 * These are flip-flops of various sort, but similar pinouts. 69 */ 70 extern edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib); 71 extern edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib); 72 extern edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib); 73 #define FDCE_Q 0 74 #define FDCE_C 1 75 #define FDCE_D 2 76 #define FDCE_CE 3 77 #define FDCE_CLR 4 78 #define FDCE_PRE 5 79 80 81 /* === Virtex/Virtex2 Carry Chain Logic === */ 82 83 extern edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib); 84 #define MULT_AND_LO 0 85 #define MULT_AND_I0 1 86 #define MULT_AND_I1 2 87 88 extern edif_cell_t xilinx_cell_muxcy(edif_xlibrary_t xlib); 89 extern edif_cell_t xilinx_cell_muxcy_l(edif_xlibrary_t xlib); 90 #define MUXCY_O 0 91 #define MUXCY_DI 1 92 #define MUXCY_CI 2 93 #define MUXCY_S 3 94 95 extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib); 96 #define XORCY_O 0 97 #define XORCY_CI 1 98 #define XORCY_LI 2 99 100 /* === Virtex/Virtex2 MUX devices */ 101 extern edif_cell_t xilinx_cell_muxf5(edif_xlibrary_t xlib); 102 extern edif_cell_t xilinx_cell_muxf6(edif_xlibrary_t xlib); 103 extern edif_cell_t xilinx_cell_muxf7(edif_xlibrary_t xlib); 104 extern edif_cell_t xilinx_cell_muxf8(edif_xlibrary_t xlib); 105 #define MUXF_O 0 106 #define MUXF_I0 1 107 #define MUXF_I1 2 108 #define MUXF_S 3 109 110 /* === Inheritable Methods === */ 111 112 extern void virtex_logic(ivl_net_logic_t net); 113 extern void virtex_generic_dff(ivl_lpm_t net); 114 extern void virtex_eq(ivl_lpm_t net); 115 extern void virtex_ge(ivl_lpm_t net); 116 extern void virtex_mux(ivl_lpm_t net); 117 extern void virtex_add(ivl_lpm_t net); 118 119 extern void xilinx_common_header(ivl_design_t des); 120 extern void xilinx_show_footer(ivl_design_t des); 121 extern void xilinx_show_scope(ivl_scope_t scope); 122 extern void xilinx_pad(ivl_signal_t, const char*str); 123 extern void xilinx_logic(ivl_net_logic_t net); 124 extern void xilinx_mux(ivl_lpm_t net); 125 extern void xilinx_add(ivl_lpm_t net); 126 extern void xilinx_shiftl(ivl_lpm_t net); 127 128 #endif /* IVL_xilinx_H */ 129