1 /*************************************************************************** 2 * Copyright (C) 2013 Andes Technology * 3 * Hsiangkai Wang <hkwang@andestech.com> * 4 * * 5 * This program is free software; you can redistribute it and/or modify * 6 * it under the terms of the GNU General Public License as published by * 7 * the Free Software Foundation; either version 2 of the License, or * 8 * (at your option) any later version. * 9 * * 10 * This program is distributed in the hope that it will be useful, * 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of * 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 13 * GNU General Public License for more details. * 14 * * 15 * You should have received a copy of the GNU General Public License * 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. * 17 ***************************************************************************/ 18 19 #ifndef OPENOCD_TARGET_NDS32_INSN_H 20 #define OPENOCD_TARGET_NDS32_INSN_H 21 22 #define NOP (0x40000009) 23 #define DSB (0x64000008) 24 #define ISB (0x64000009) 25 #define BEQ_MINUS_12 (0x4C000000 | 0x3FFA) 26 #define MTSR_DTR(a) (0x64000003 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) 27 #define MFSR_DTR(a) (0x64000002 | (((0x03 << 7) | (0x08 << 3) | (0x00 << 0)) << 10) | (((a) & 0x1F) << 20)) 28 #define SETHI(a, b) (0x46000000 | ((a) << 20) | (b)) 29 #define ORI(a, b, c) (0x58000000 | ((a) << 20) | ((b) << 15) | (c)) 30 #define LWI_BI(a, b) (0x0C000001 | (a << 20) | (b << 15)) 31 #define LHI_BI(a, b) (0x0A000001 | (a << 20) | (b << 15)) 32 #define LBI_BI(a, b) (0x08000001 | (a << 20) | (b << 15)) 33 #define SWI_BI(a, b) (0x1C000001 | (a << 20) | (b << 15)) 34 #define SHI_BI(a, b) (0x1A000001 | (a << 20) | (b << 15)) 35 #define SBI_BI(a, b) (0x18000001 | (a << 20) | (b << 15)) 36 #define IRET (0x64000004) 37 #define L1D_IX_WB(a) (0x64000021 | ((a) << 15)) 38 #define L1D_IX_INVAL(a) (0x64000001 | ((a) << 15)) 39 #define L1D_VA_INVAL(a) (0x64000101 | ((a) << 15)) 40 #define L1D_VA_WB(a) (0x64000121 | ((a) << 15)) 41 #define L1D_IX_RTAG(a) (0x64000061 | ((a) << 15)) 42 #define L1D_IX_RWD(a) (0x64000081 | ((a) << 15)) 43 #define L1I_IX_INVAL(a) (0x64000201 | ((a) << 15)) 44 #define L1I_VA_INVAL(a) (0x64000301 | ((a) << 15)) 45 #define L1I_IX_RTAG(a) (0x64000261 | ((a) << 15)) 46 #define L1I_IX_RWD(a) (0x64000281 | ((a) << 15)) 47 #define L1I_VA_FILLCK(a) (0x64000361 | ((a) << 15)) 48 #define ISYNC(a) (0x6400000d | ((a) << 20)) 49 #define MSYNC_STORE (0x6400002c) 50 #define MSYNC_ALL (0x6400000c) 51 #define TLBOP_TARGET_READ(a) (0x6400000e | ((a) << 15)) 52 #define TLBOP_TARGET_PROBE(a, b) (0x640000AE | ((a) << 20) | ((b) << 15)) 53 #define MFCPD(a, b, c) (0x6A000041 | (a << 20) | (b << 8) | (c << 4)) 54 #define MFCPW(a, b, c) (0x6A000001 | (a << 20) | (b << 8) | (c << 4)) 55 #define MTCPD(a, b, c) (0x6A000049 | (a << 20) | (b << 8) | (c << 4)) 56 #define MTCPW(a, b, c) (0x6A000009 | (a << 20) | (b << 8) | (c << 4)) 57 #define MOVI_(a, b) (0x44000000 | (a << 20) | (b & 0xFFFFF)) 58 #define MFUSR_G0(a, b) (0x42000020 | (a << 20) | (b << 15)) 59 #define MTUSR_G0(a, b) (0x42000021 | (a << 20) | (b << 15)) 60 #define MFSR(a, b) (0x64000002 | (b << 10) | (a << 20)) 61 #define MTSR(a, b) (0x64000003 | (b << 10) | (a << 20)) 62 #define AMFAR(a, b) (0x60300060 | (a << 15) | b) 63 #define AMTAR(a, b) (0x60300040 | (a << 15) | b) 64 #define AMFAR2(a, b) (0x60300260 | (a << 15) | b) 65 #define AMTAR2(a, b) (0x60300240 | (a << 15) | b) 66 #define FMFCSR (0x6A000701) 67 #define FMTCSR (0x6A000709) 68 #define FMFCFG (0x6A000301) 69 #define FMFSR(a, b) (0x6A000001 | ((a) << 20) | ((b) << 15)) 70 #define FMTSR(a, b) (0x6A000009 | ((a) << 20) | ((b) << 15)) 71 #define FMFDR(a, b) (0x6A000041 | ((a) << 20) | ((b) << 15)) 72 #define FMTDR(a, b) (0x6A000049 | ((a) << 20) | ((b) << 15)) 73 74 /* break instructions */ 75 extern const int NDS32_BREAK_16; 76 extern const int NDS32_BREAK_32; 77 78 #endif /* OPENOCD_TARGET_NDS32_INSN_H */ 79