| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/sparc/math-emu/ |
| H A D | math_32.c | 131 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) macro
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| H A D | math_64.c | 91 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) macro
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/sparc/math-emu/ |
| H A D | math_32.c | 131 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) macro
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| H A D | math_64.c | 91 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/arch/sparc/math-emu/ |
| H A D | math_32.c | 131 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) macro
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| H A D | math_64.c | 91 #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) macro
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| /dports/emulators/mess/mame-mame0226/src/devices/cpu/sparc/ |
| H A D | sparcdefs.h | 392 #define FSR_CEXC_MASK 0x0000001f macro
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| /dports/emulators/mame/mame-mame0226/src/devices/cpu/sparc/ |
| H A D | sparcdefs.h | 392 #define FSR_CEXC_MASK 0x0000001f macro
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| /dports/emulators/unicorn/unicorn-1.0.2/qemu/target-sparc/ |
| H A D | cpu.h | 179 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-sparc/ |
| H A D | cpu.h | 179 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/sparc/ |
| H A D | cpu.h | 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu5/qemu-5.2.0/target/sparc/ |
| H A D | cpu.h | 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/sparc/ |
| H A D | cpu.h | 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/sparc/ |
| H A D | cpu.h | 177 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu42/qemu-4.2.1/target/sparc/ |
| H A D | cpu.h | 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/sparc/ |
| H A D | cpu.h | 192 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/sparc/ |
| H A D | cpu.h | 194 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu/qemu-6.2.0/target/sparc/ |
| H A D | cpu.h | 194 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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| /dports/emulators/qemu60/qemu-6.0.0/target/sparc/ |
| H A D | cpu.h | 194 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) macro
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