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Searched defs:FSR_RD (Results 1 – 15 of 15) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/arch/sparc/include/
H A Dfsr.h49 #define FSR_RD 0xc0000000 /* rounding direction */ macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/riscv/
H A Dcpu_bits.h12 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu42/qemu-4.2.1/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu60/qemu-6.0.0/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/qemu/qemu-6.2.0/target/riscv/
H A Dcpu_bits.h14 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Ddecode.h50 #define FSR_RD (0x7 << FSR_RD_SHIFT) macro
/dports/lang/python-legacy/Python-2.7.18/Lib/plat-sunos5/
H A DIN.py670 FSR_RD = 0xc0000000 variable
H A DSTROPTS.py667 FSR_RD = 0xc0000000 variable
/dports/lang/python27/Python-2.7.18/Lib/plat-sunos5/
H A DIN.py670 FSR_RD = 0xc0000000 variable
H A DSTROPTS.py667 FSR_RD = 0xc0000000 variable