1 /* $OpenBSD: gemreg.h,v 1.17 2009/07/12 15:54:32 kettenis Exp $ */ 2 /* $NetBSD: gemreg.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 #ifndef _IF_GEMREG_H 34 #define _IF_GEMREG_H 35 36 /* Register definitions for Sun GEM gigabit ethernet */ 37 38 /* 39 * First bank: this registers live at the start of the PCI 40 * mapping, and at the start of the second bank of the SBUS 41 * version. 42 */ 43 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 44 #define GEM_CONFIG 0x0004 /* config reg */ 45 #define GEM_STATUS 0x000c /* status reg */ 46 /* Note: Reading the status reg clears bits 0-6 */ 47 #define GEM_INTMASK 0x0010 48 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 49 #define GEM_STATUS_ALIAS 0x001c 50 51 /* 52 * Second bank: this registers live at offset 0x1000 of the PCI 53 * mapping, and at the start of the first bank of the SBUS 54 * version. 55 */ 56 #define GEM_PCI_BANK2_OFFSET 0x1000 57 #define GEM_PCI_BANK2_SIZE 0x14 58 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 59 #define GEM_ERROR_STATUS 0x0000 /* PCI error status R/C */ 60 #define GEM_SBUS_RESET 0x0000 /* Sbus Reset */ 61 #define GEM_ERROR_MASK 0x0004 62 #define GEM_SBUS_CONFIG 0x0004 63 #define GEM_BIF_CONFIG 0x0008 /* BIF config reg */ 64 #define GEM_BIF_DIAG 0x000c 65 #define GEM_RESET 0x0010 /* Software reset register */ 66 67 /* Bits in GEM_SEB register */ 68 #define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 69 #define GEM_SEB_RXWON 0x000000004 70 71 /* Bits in GEM_SBUS_CONFIG register */ 72 #define GEM_SBUS_CFG_BSIZE32 0x00000001 73 #define GEM_SBUS_CFG_BSIZE64 0x00000002 74 #define GEM_SBUS_CFG_BSIZE128 0x00000004 75 #define GEM_SBUS_CFG_BMODE64 0x00000008 76 #define GEM_SBUS_CFG_PARITY 0x00000200 77 78 /* Bits in GEM_CONFIG register */ 79 #define GEM_CONFIG_BURST_64 0x000000000 /* 0->infinity, 1->64KB */ 80 #define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infinity, 1->64KB */ 81 #define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 82 #define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 83 /* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 84 #define GEM_CONFIG_RONPAULBIT 0x000000800 /* after infinite burst use 85 * memory read multiple for 86 * PCI commands */ 87 #define GEM_CONFIG_BUG2FIX 0x000001000 /* fix RX hang after overflow */ 88 89 90 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 91 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 92 93 /* Top part of GEM_STATUS has TX completion information */ 94 #define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 95 96 /* 97 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. 98 * Bits 0-6 auto-clear when read. 99 */ 100 #define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 101 #define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 102 #define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 103 #define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 104 #define GEM_INTR_RX_NOBUF 0x000000020 105 #define GEM_INTR_RX_TAG_ERR 0x000000040 106 #define GEM_INTR_PCS 0x000002000 /* Physical Code Sub-layer */ 107 #define GEM_INTR_TX_MAC 0x000004000 108 #define GEM_INTR_RX_MAC 0x000008000 109 #define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 110 #define GEM_INTR_MIF 0x000020000 111 #define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 112 #define GEM_INTR_BITS "\020" \ 113 "\1INTME\2TXEMPTY\3TXDONE" \ 114 "\5RXDONE\6RXNOBUF\7RX_TAG_ERR" \ 115 "\16PCS\17TXMAC\20RXMAC" \ 116 "\21MACCONTROL\22MIF\23BERR" 117 118 /* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */ 119 #define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 120 #define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 121 #define GEM_ERROR_STAT_OTHERS 0x000000004 122 123 /* GEM_BIF_CONFIG register bits */ 124 #define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 125 #define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 126 #define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 127 #define GEM_BIF_CONFIG_M66EN 0x000000008 128 129 /* GEM_RESET register bits -- TX and RX self clear when complete. */ 130 #define GEM_RESET_TX 0x000000001 /* Reset TX half */ 131 #define GEM_RESET_RX 0x000000002 /* Reset RX half */ 132 #define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 133 134 /* GEM TX DMA registers */ 135 #define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 136 #define GEM_TX_CONFIG 0x2004 137 #define GEM_TX_RING_PTR_LO 0x2008 138 #define GEM_TX_RING_PTR_HI 0x200c 139 140 #define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 141 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 142 #define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 143 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 144 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 145 146 #define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 147 #define GEM_TX_DATA_PTR 0x2030 /* ETX state machine reg (64-bit)*/ 148 149 #define GEM_TX_COMPLETION 0x2100 150 #define GEM_TX_FIFO_ADDRESS 0x2104 151 #define GEM_TX_FIFO_TAG 0x2108 152 #define GEM_TX_FIFO_DATA_LO 0x210c 153 #define GEM_TX_FIFO_DATA_HI_T1 0x2110 154 #define GEM_TX_FIFO_DATA_HI_T0 0x2114 155 #define GEM_TX_FIFO_SIZE 0x2118 156 #define GEM_TX_DEBUG 0x3028 157 158 /* GEM_TX_CONFIG register bits. */ 159 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 160 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 161 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 162 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 163 164 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 165 #define GEM_RING_SZ_64 (1<<1) 166 #define GEM_RING_SZ_128 (2<<1) 167 #define GEM_RING_SZ_256 (3<<1) 168 #define GEM_RING_SZ_512 (4<<1) 169 #define GEM_RING_SZ_1024 (5<<1) 170 #define GEM_RING_SZ_2048 (6<<1) 171 #define GEM_RING_SZ_4096 (7<<1) 172 #define GEM_RING_SZ_8192 (8<<1) 173 174 /* GEM_TX_COMPLETION register bits */ 175 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 176 177 /* GEM RX DMA registers */ 178 #define GEM_RX_CONFIG 0x4000 179 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 180 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 181 182 #define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 183 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 184 #define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 185 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 186 187 #define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 188 #define GEM_RX_PAUSE_THRESH 0x4020 189 190 #define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 191 #define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 192 193 #define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 194 #define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 195 #define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 196 197 #define GEM_RX_FIFO_ADDRESS 0x410c 198 #define GEM_RX_FIFO_TAG 0x4110 199 #define GEM_RX_FIFO_DATA_LO 0x4114 200 #define GEM_RX_FIFO_DATA_HI_T1 0x4118 201 #define GEM_RX_FIFO_DATA_HI_T0 0x411c 202 #define GEM_RX_FIFO_SIZE 0x4120 203 204 /* GEM_RX_CONFIG register bits. */ 205 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 206 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 207 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 208 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 209 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 210 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 211 212 #define GEM_THRSH_64 0 213 #define GEM_THRSH_128 1 214 #define GEM_THRSH_256 2 215 #define GEM_THRSH_512 3 216 #define GEM_THRSH_1024 4 217 #define GEM_THRSH_2048 5 218 219 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 220 #define GEM_RX_CONFIG_FBOFF_SHFT 10 221 #define GEM_RX_CONFIG_CXM_START_SHFT 13 222 223 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 224 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff 225 #define GEM_RX_PTH_XON_THRESH 0x07fc0000 226 227 /* GEM_RX_BLANKING register bits */ 228 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 229 #define GEM_RX_BLANKING_TIME 0x03fc0000 /* Delay intr for x ticks */ 230 /* One tick is 1048 PCI clocs, or 16us at 66MHz */ 231 232 /* GEM_MAC registers */ 233 #define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 234 #define GEM_MAC_RXRESET 0x6004 /* ditto */ 235 #define GEM_MAC_SEND_PAUSE_CMD 0x6008 236 #define GEM_MAC_TX_STATUS 0x6010 237 #define GEM_MAC_RX_STATUS 0x6014 238 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 239 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 240 #define GEM_MAC_RX_MASK 0x6024 241 #define GEM_MAC_CONTROL_MASK 0x6028 242 #define GEM_MAC_TX_CONFIG 0x6030 243 #define GEM_MAC_RX_CONFIG 0x6034 244 #define GEM_MAC_CONTROL_CONFIG 0x6038 245 #define GEM_MAC_XIF_CONFIG 0x603c 246 #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 247 #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 248 #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 249 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 250 #define GEM_MAC_MAC_MIN_FRAME 0x6050 251 #define GEM_MAC_MAC_MAX_FRAME 0x6054 252 #define GEM_MAC_PREAMBLE_LEN 0x6058 253 #define GEM_MAC_JAM_SIZE 0x605c 254 #define GEM_MAC_ATTEMPT_LIMIT 0x6060 255 #define GEM_MAC_CONTROL_TYPE 0x6064 256 257 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 258 #define GEM_MAC_ADDR1 0x6084 259 #define GEM_MAC_ADDR2 0x6088 260 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 261 #define GEM_MAC_ADDR4 0x6090 262 #define GEM_MAC_ADDR5 0x6094 263 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 264 #define GEM_MAC_ADDR7 0x609c 265 #define GEM_MAC_ADDR8 0x60a0 266 267 #define GEM_MAC_ADDR_FILTER0 0x60a4 268 #define GEM_MAC_ADDR_FILTER1 0x60a8 269 #define GEM_MAC_ADDR_FILTER2 0x60ac 270 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 271 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 272 273 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 274 #define GEM_MAC_HASH1 0x60c4 275 #define GEM_MAC_HASH2 0x60c8 276 #define GEM_MAC_HASH3 0x60cc 277 #define GEM_MAC_HASH4 0x60d0 278 #define GEM_MAC_HASH5 0x60d4 279 #define GEM_MAC_HASH6 0x60d8 280 #define GEM_MAC_HASH7 0x60dc 281 #define GEM_MAC_HASH8 0x60e0 282 #define GEM_MAC_HASH9 0x60e4 283 #define GEM_MAC_HASH10 0x60e8 284 #define GEM_MAC_HASH11 0x60ec 285 #define GEM_MAC_HASH12 0x60f0 286 #define GEM_MAC_HASH13 0x60f4 287 #define GEM_MAC_HASH14 0x60f8 288 #define GEM_MAC_HASH15 0x60fc 289 290 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 291 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 292 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 293 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 294 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 295 #define GEM_MAC_PEAK_ATTEMPTS 0x6114 296 #define GEM_MAC_RX_FRAME_COUNT 0x6118 297 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c 298 #define GEM_MAC_RX_ALIGN_ERR 0x6120 299 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124 300 #define GEM_MAC_RX_CODE_VIOL 0x6128 301 #define GEM_MAC_RANDOM_SEED 0x6130 302 #define GEM_MAC_MAC_STATE 0x6134 /* MAC sstate machine reg */ 303 304 /* GEM_MAC_SEND_PAUSE_CMD register bits */ 305 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 306 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000 307 308 /* GEM_MAC_TX_STATUS and _MASK register bits */ 309 #define GEM_MAC_TX_XMIT_DONE 0x00000001 310 #define GEM_MAC_TX_UNDERRUN 0x00000002 311 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 312 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 313 #define GEM_MAC_TX_ECC_EXP 0x00000010 314 #define GEM_MAC_TX_LCC_EXP 0x00000020 315 #define GEM_MAC_TX_FCC_EXP 0x00000040 316 #define GEM_MAC_TX_DEFER_EXP 0x00000080 317 #define GEM_MAC_TX_PEAK_EXP 0x00000100 318 319 /* GEM_MAC_RX_STATUS and _MASK register bits */ 320 #define GEM_MAC_RX_DONE 0x00000001 321 #define GEM_MAC_RX_OVERFLOW 0x00000002 322 #define GEM_MAC_RX_FRAME_CNT 0x00000004 323 #define GEM_MAC_RX_ALIGN_EXP 0x00000008 324 #define GEM_MAC_RX_CRC_EXP 0x00000010 325 #define GEM_MAC_RX_LEN_EXP 0x00000020 326 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 327 328 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 329 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 330 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 331 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 332 #define GEM_MAC_PAUSE_TIME 0xffff0000 333 334 /* GEM_MAC_XIF_CONFIG register bits */ 335 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 336 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 337 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 338 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 339 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 340 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 341 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 342 343 /* GEM_MAC_SLOT_TIME register bits */ 344 #define GEM_MAC_SLOT_INT 0x40 345 #define GEM_MAC_SLOT_EXT 0x200 /* external phy */ 346 347 /* GEM_MAC_TX_CONFIG register bits */ 348 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 349 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 350 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 351 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 352 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 353 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 354 #define GEM_MAC_TX_NO_BACKOFF 0x00000040 355 #define GEM_MAC_TX_SLOWDOWN 0x00000080 356 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 357 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 358 /* Carrier Extension is required for half duplex Gbps operation */ 359 360 /* GEM_MAC_RX_CONFIG register bits */ 361 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 362 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 363 #define GEM_MAC_RX_STRIP_CRC 0x00000004 364 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 365 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 366 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 367 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 368 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 369 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 370 /* 371 * Carrier Extension enables reception of packet bursts generated by 372 * senders with carrier extension enabled. 373 */ 374 375 /* GEM_MAC_CONTROL_CONFIG bits */ 376 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 377 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 378 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 379 380 /* GEM_MAC_MAC_STATE register bits */ 381 #define GEM_MAC_STATE_OVERFLOW 0x03800000 382 383 /* GEM MIF registers */ 384 /* Bit bang registers use low bit only */ 385 #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 386 #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 387 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 388 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 389 #define GEM_MIF_CONFIG 0x6210 390 #define GEM_MIF_INTERRUPT_MASK 0x6214 391 #define GEM_MIF_BASIC_STATUS 0x6218 392 #define GEM_MIF_STATE_MACHINE 0x621c 393 394 /* GEM_MIF_FRAME bits */ 395 #define GEM_MIF_FRAME_DATA 0x0000ffff 396 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 397 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 398 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000 399 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */ 400 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 401 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 402 403 #define GEM_MIF_FRAME_READ 0x60020000 404 #define GEM_MIF_FRAME_WRITE 0x50020000 405 406 #define GEM_MIF_REG_SHIFT 18 407 #define GEM_MIF_PHY_SHIFT 23 408 409 /* GEM_MIF_CONFIG register bits */ 410 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */ 411 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 412 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 413 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 414 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 415 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 416 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 417 /* MDI0 is onboard transceiver MDI1 is external, PHYAD for both is 0 */ 418 419 /* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 420 #define GEM_MIF_STATUS 0x0000ffff 421 #define GEM_MIF_BASIC 0xffff0000 422 /* 423 * The Basic part is the last value read in the POLL field of the config 424 * register. 425 * 426 * The status part indicates the bits that have changed. 427 */ 428 429 /* The GEM PCS/Serial link registers. */ 430 /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 431 #define GEM_MII_CONTROL 0x9000 432 #define GEM_MII_STATUS 0x9004 433 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 434 #define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 435 #define GEM_MII_CONFIG 0x9010 436 #define GEM_MII_STATE_MACHINE 0x9014 437 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 438 #define GEM_MII_DATAPATH_MODE 0x9050 439 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 440 #define GEM_MII_OUTPUT_SELECT 0x9058 441 #define GEM_MII_SLINK_STATUS 0x905c /* serial link status */ 442 443 /* GEM_MII_CONTROL bits */ 444 /* 445 * DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS. 446 */ 447 #define GEM_MII_CONTROL_RESET 0x00008000 448 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 449 #define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */ 450 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 451 #define GEM_MII_CONTROL_POWERDN 0x00000800 452 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */ 453 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */ 454 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 455 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 456 457 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 458 #define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 459 #define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 460 #define GEM_MII_STATUS_UNK 0x00000100 461 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ 462 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 463 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ 464 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 465 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 466 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ 467 468 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 469 #define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ 470 #define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ 471 /* Link Partner Capability */ 472 #define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */ 473 #define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */ 474 #define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ 475 #define GEM_MII_ANEG_HLF_DUPLX 0x00000040 476 #define GEM_MII_ANEG_FUL_DUPLX 0x00000020 477 478 /* GEM_MII_CONFIG reg */ 479 #define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */ 480 #define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */ 481 #define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal 482 * 1 high freq, 2 low freq */ 483 #define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */ 484 #define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */ 485 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 486 487 /* 488 * GEM_MII_STATE_MACHINE 489 * XXX These are best guesses from observed behavior. 490 */ 491 #define GEM_MII_FSM_STOP 0x00000000 /* stopped */ 492 #define GEM_MII_FSM_RUN 0x00000001 /* running */ 493 #define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */ 494 #define GEM_MII_FSM_DONE 0x00000101 /* complete */ 495 496 /* 497 * GEM_MII_INTERRUP_STATUS reg 498 * No mask register; mask with the global interrupt mask register. 499 */ 500 #define GEM_MII_INTERRUP_LINK 0x00000002 /* PCS link status change */ 501 502 /* GEM_MII_DATAPATH_MODE reg */ 503 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ 504 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 505 #define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */ 506 #define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ 507 508 /* GEM_MII_SLINK_CONTROL reg */ 509 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl, logic 510 * reversed for SERDES */ 511 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 512 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 513 #define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ 514 #define GEM_MII_SLINK_SELFTEST 0x000001c0 515 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ 516 517 /* GEM_MII_SLINK_STATUS reg */ 518 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 519 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 520 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 521 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 522 523 /* Wired GEM PHY addresses */ 524 #define GEM_PHYAD_INTERNAL 1 525 #define GEM_PHYAD_EXTERNAL 0 526 527 /* 528 * GEM descriptor table structures. 529 */ 530 struct gem_desc { 531 uint64_t gd_flags; 532 uint64_t gd_addr; 533 }; 534 535 /* Transmit flags */ 536 #define GEM_TD_BUFSIZE 0x0000000000007fffLL 537 #define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 538 #define GEM_TD_CXSUM_STARTSHFT 15 539 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 540 #define GEM_TD_CXSUM_STUFFSHFT 21 541 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 542 #define GEM_TD_END_OF_PACKET 0x0000000040000000LL 543 #define GEM_TD_START_OF_PACKET 0x0000000080000000LL 544 #define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 545 #define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 546 /* 547 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 548 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 549 */ 550 551 /* Receive flags */ 552 #define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */ 553 #define GEM_RD_BUFSIZE 0x000000007fff0000LL 554 #define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 555 #define GEM_RD_HASHVAL 0x0ffff00000000000LL 556 #define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 557 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 558 #define GEM_RD_BAD_CRC 0x4000000000000000LL 559 560 #define GEM_RD_BUFSHIFT 16 561 #define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 562 563 #endif /* _IF_GEMREG_H */ 564