1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_STATE_H
34 #define BRW_STATE_H
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 enum intel_msaa_layout;
43
44 extern const struct brw_tracked_state brw_blend_constant_color;
45 extern const struct brw_tracked_state brw_clip_unit;
46 extern const struct brw_tracked_state brw_vs_pull_constants;
47 extern const struct brw_tracked_state brw_tcs_pull_constants;
48 extern const struct brw_tracked_state brw_tes_pull_constants;
49 extern const struct brw_tracked_state brw_gs_pull_constants;
50 extern const struct brw_tracked_state brw_wm_pull_constants;
51 extern const struct brw_tracked_state brw_cs_pull_constants;
52 extern const struct brw_tracked_state brw_constant_buffer;
53 extern const struct brw_tracked_state brw_curbe_offsets;
54 extern const struct brw_tracked_state brw_binding_table_pointers;
55 extern const struct brw_tracked_state brw_depthbuffer;
56 extern const struct brw_tracked_state brw_recalculate_urb_fence;
57 extern const struct brw_tracked_state brw_sf_vp;
58 extern const struct brw_tracked_state brw_cs_texture_surfaces;
59 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
60 extern const struct brw_tracked_state brw_vs_image_surfaces;
61 extern const struct brw_tracked_state brw_tcs_ubo_surfaces;
62 extern const struct brw_tracked_state brw_tcs_image_surfaces;
63 extern const struct brw_tracked_state brw_tes_ubo_surfaces;
64 extern const struct brw_tracked_state brw_tes_image_surfaces;
65 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
66 extern const struct brw_tracked_state brw_gs_image_surfaces;
67 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
68 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces;
69 extern const struct brw_tracked_state brw_texture_surfaces;
70 extern const struct brw_tracked_state brw_wm_binding_table;
71 extern const struct brw_tracked_state brw_gs_binding_table;
72 extern const struct brw_tracked_state brw_tes_binding_table;
73 extern const struct brw_tracked_state brw_tcs_binding_table;
74 extern const struct brw_tracked_state brw_vs_binding_table;
75 extern const struct brw_tracked_state brw_wm_ubo_surfaces;
76 extern const struct brw_tracked_state brw_wm_image_surfaces;
77 extern const struct brw_tracked_state brw_cs_ubo_surfaces;
78 extern const struct brw_tracked_state brw_cs_image_surfaces;
79
80 extern const struct brw_tracked_state brw_psp_urb_cbs;
81
82 extern const struct brw_tracked_state brw_indices;
83 extern const struct brw_tracked_state brw_index_buffer;
84 extern const struct brw_tracked_state gen7_cs_push_constants;
85 extern const struct brw_tracked_state gen6_binding_table_pointers;
86 extern const struct brw_tracked_state gen6_gs_binding_table;
87 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
88 extern const struct brw_tracked_state gen6_sampler_state;
89 extern const struct brw_tracked_state gen6_sol_surface;
90 extern const struct brw_tracked_state gen6_sf_vp;
91 extern const struct brw_tracked_state gen6_urb;
92 extern const struct brw_tracked_state gen7_l3_state;
93 extern const struct brw_tracked_state gen7_push_constant_space;
94 extern const struct brw_tracked_state gen7_urb;
95 extern const struct brw_tracked_state gen8_pma_fix;
96 extern const struct brw_tracked_state brw_cs_work_groups_surface;
97
98 void gen4_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
99 struct brw_bo *bo, uint32_t offset,
100 uint64_t imm);
101 void gen45_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
102 struct brw_bo *bo, uint32_t offset,
103 uint64_t imm);
104 void gen5_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
105 struct brw_bo *bo, uint32_t offset,
106 uint64_t imm);
107 void gen6_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
108 struct brw_bo *bo, uint32_t offset,
109 uint64_t imm);
110 void gen7_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
111 struct brw_bo *bo, uint32_t offset,
112 uint64_t imm);
113 void gen75_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
114 struct brw_bo *bo, uint32_t offset,
115 uint64_t imm);
116 void gen8_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
117 struct brw_bo *bo, uint32_t offset,
118 uint64_t imm);
119 void gen9_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
120 struct brw_bo *bo, uint32_t offset,
121 uint64_t imm);
122 void gen10_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
123 struct brw_bo *bo, uint32_t offset,
124 uint64_t imm);
125 void gen11_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
126 struct brw_bo *bo, uint32_t offset,
127 uint64_t imm);
128
129 static inline bool
brw_state_dirty(const struct brw_context * brw,GLuint mesa_flags,uint64_t brw_flags)130 brw_state_dirty(const struct brw_context *brw,
131 GLuint mesa_flags, uint64_t brw_flags)
132 {
133 return ((brw->NewGLState & mesa_flags) |
134 (brw->ctx.NewDriverState & brw_flags)) != 0;
135 }
136
137 /* brw_binding_tables.c */
138 void brw_upload_binding_table(struct brw_context *brw,
139 uint32_t packet_name,
140 const struct brw_stage_prog_data *prog_data,
141 struct brw_stage_state *stage_state);
142
143 /* brw_misc_state.c */
144 void brw_upload_invariant_state(struct brw_context *brw);
145 uint32_t
146 brw_depthbuffer_format(struct brw_context *brw);
147
148 void brw_upload_state_base_address(struct brw_context *brw);
149
150 /* gen8_depth_state.c */
151 void gen8_write_pma_stall_bits(struct brw_context *brw,
152 uint32_t pma_stall_bits);
153
154 /* brw_disk_cache.c */
155 void brw_disk_cache_init(struct intel_screen *screen);
156 bool brw_disk_cache_upload_program(struct brw_context *brw,
157 gl_shader_stage stage);
158 void brw_disk_cache_write_compute_program(struct brw_context *brw);
159 void brw_disk_cache_write_render_programs(struct brw_context *brw);
160
161 /***********************************************************************
162 * brw_state_upload.c
163 */
164 void brw_upload_render_state(struct brw_context *brw);
165 void brw_render_state_finished(struct brw_context *brw);
166 void brw_upload_compute_state(struct brw_context *brw);
167 void brw_compute_state_finished(struct brw_context *brw);
168 void brw_init_state(struct brw_context *brw);
169 void brw_destroy_state(struct brw_context *brw);
170 void brw_emit_select_pipeline(struct brw_context *brw,
171 enum brw_pipeline pipeline);
172 void brw_enable_obj_preemption(struct brw_context *brw, bool enable);
173
174 static inline void
brw_select_pipeline(struct brw_context * brw,enum brw_pipeline pipeline)175 brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
176 {
177 if (unlikely(brw->last_pipeline != pipeline)) {
178 assert(pipeline < BRW_NUM_PIPELINES);
179 brw_emit_select_pipeline(brw, pipeline);
180 brw->last_pipeline = pipeline;
181 }
182 }
183
184 /***********************************************************************
185 * brw_program_cache.c
186 */
187
188 void brw_upload_cache(struct brw_cache *cache,
189 enum brw_cache_id cache_id,
190 const void *key,
191 GLuint key_sz,
192 const void *data,
193 GLuint data_sz,
194 const void *aux,
195 GLuint aux_sz,
196 uint32_t *out_offset, void *out_aux);
197
198 bool brw_search_cache(struct brw_cache *cache, enum brw_cache_id cache_id,
199 const void *key, GLuint key_size, uint32_t *inout_offset,
200 void *inout_aux, bool flag_state);
201
202 const void *brw_find_previous_compile(struct brw_cache *cache,
203 enum brw_cache_id cache_id,
204 unsigned program_string_id);
205
206 void brw_program_cache_check_size(struct brw_context *brw);
207
208 void brw_init_caches( struct brw_context *brw );
209 void brw_destroy_caches( struct brw_context *brw );
210
211 void brw_print_program_cache(struct brw_context *brw);
212
213 enum brw_cache_id brw_stage_cache_id(gl_shader_stage stage);
214
215 /* intel_batchbuffer.c */
216 void brw_require_statebuffer_space(struct brw_context *brw, int size);
217 void *brw_state_batch(struct brw_context *brw,
218 int size, int alignment, uint32_t *out_offset);
219
220 /* brw_wm_surface_state.c */
221 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
222 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
223 enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format);
224
225 GLuint translate_tex_target(GLenum target);
226
227 enum isl_format translate_tex_format(struct brw_context *brw,
228 mesa_format mesa_format,
229 GLenum srgb_decode);
230
231 int brw_get_texture_swizzle(const struct gl_context *ctx,
232 const struct gl_texture_object *t);
233
234 void brw_emit_buffer_surface_state(struct brw_context *brw,
235 uint32_t *out_offset,
236 struct brw_bo *bo,
237 unsigned buffer_offset,
238 unsigned surface_format,
239 unsigned buffer_size,
240 unsigned pitch,
241 unsigned reloc_flags);
242
243 /* brw_sampler_state.c */
244 void brw_emit_sampler_state(struct brw_context *brw,
245 uint32_t *sampler_state,
246 uint32_t batch_offset_for_sampler_state,
247 unsigned min_filter,
248 unsigned mag_filter,
249 unsigned mip_filter,
250 unsigned max_anisotropy,
251 unsigned address_rounding,
252 unsigned wrap_s,
253 unsigned wrap_t,
254 unsigned wrap_r,
255 unsigned base_level,
256 unsigned min_lod,
257 unsigned max_lod,
258 int lod_bias,
259 unsigned shadow_function,
260 bool non_normalized_coordinates,
261 uint32_t border_color_offset);
262
263 /* gen6_constant_state.c */
264 void
265 brw_populate_constant_data(struct brw_context *brw,
266 const struct gl_program *prog,
267 const struct brw_stage_state *stage_state,
268 void *dst,
269 const uint32_t *param,
270 unsigned nr_params);
271 void
272 brw_upload_pull_constants(struct brw_context *brw,
273 GLbitfield64 brw_new_constbuf,
274 const struct gl_program *prog,
275 struct brw_stage_state *stage_state,
276 const struct brw_stage_prog_data *prog_data);
277 void
278 brw_upload_cs_push_constants(struct brw_context *brw,
279 const struct gl_program *prog,
280 const struct brw_cs_prog_data *cs_prog_data,
281 struct brw_stage_state *stage_state);
282
283 /* gen7_vs_state.c */
284 void
285 gen7_upload_constant_state(struct brw_context *brw,
286 const struct brw_stage_state *stage_state,
287 bool active, unsigned opcode);
288
289 /* brw_clip.c */
290 void brw_upload_clip_prog(struct brw_context *brw);
291
292 /* brw_sf.c */
293 void brw_upload_sf_prog(struct brw_context *brw);
294
295 bool brw_is_drawing_points(const struct brw_context *brw);
296 bool brw_is_drawing_lines(const struct brw_context *brw);
297
298 /* gen7_l3_state.c */
299 void
300 gen7_restore_default_l3_config(struct brw_context *brw);
301
302 static inline bool
use_state_point_size(const struct brw_context * brw)303 use_state_point_size(const struct brw_context *brw)
304 {
305 const struct gl_context *ctx = &brw->ctx;
306
307 /* Section 14.4 (Points) of the OpenGL 4.5 specification says:
308 *
309 * "If program point size mode is enabled, the derived point size is
310 * taken from the (potentially clipped) shader built-in gl_PointSize
311 * written by:
312 *
313 * * the geometry shader, if active;
314 * * the tessellation evaluation shader, if active and no
315 * geometry shader is active;
316 * * the vertex shader, otherwise
317 *
318 * and clamped to the implementation-dependent point size range. If
319 * the value written to gl_PointSize is less than or equal to zero,
320 * or if no value was written to gl_PointSize, results are undefined.
321 * If program point size mode is disabled, the derived point size is
322 * specified with the command
323 *
324 * void PointSize(float size);
325 *
326 * size specifies the requested size of a point. The default value
327 * is 1.0."
328 *
329 * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and
330 * OES_tessellation_point_size specifications. To summarize: if the last
331 * stage before rasterization is a GS or TES, then use gl_PointSize from
332 * the shader if written. Otherwise, use 1.0. If the last stage is a
333 * vertex shader, use gl_PointSize, or it is undefined.
334 *
335 * We can combine these rules into a single condition for both APIs.
336 * Using the state point size when the last shader stage doesn't write
337 * gl_PointSize satisfies GL's requirements, as it's undefined. Because
338 * ES doesn't have a PointSize() command, the state point size will
339 * remain 1.0, satisfying the ES default value in the GS/TES case, and
340 * the VS case (1.0 works for "undefined"). Mesa sets the program point
341 * mode flag to always-enabled in ES, so we can safely check that, and
342 * it'll be ignored for ES.
343 *
344 * _NEW_PROGRAM | _NEW_POINT
345 * BRW_NEW_VUE_MAP_GEOM_OUT
346 */
347 return (!ctx->VertexProgram.PointSizeEnabled && !ctx->Point._Attenuated) ||
348 (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0;
349 }
350
351 void brw_copy_pipeline_atoms(struct brw_context *brw,
352 enum brw_pipeline pipeline,
353 const struct brw_tracked_state **atoms,
354 int num_atoms);
355 void gen4_init_atoms(struct brw_context *brw);
356 void gen45_init_atoms(struct brw_context *brw);
357 void gen5_init_atoms(struct brw_context *brw);
358 void gen6_init_atoms(struct brw_context *brw);
359 void gen7_init_atoms(struct brw_context *brw);
360 void gen75_init_atoms(struct brw_context *brw);
361 void gen8_init_atoms(struct brw_context *brw);
362 void gen9_init_atoms(struct brw_context *brw);
363 void gen10_init_atoms(struct brw_context *brw);
364 void gen11_init_atoms(struct brw_context *brw);
365
366 /* Memory Object Control State:
367 * Specifying zero for L3 means "uncached in L3", at least on Haswell
368 * and Baytrail, since there are no PTE flags for setting L3 cacheability.
369 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
370 * may still respect that.
371 */
372 #define GEN7_MOCS_L3 1
373
374 /* Ivybridge only: cache in LLC.
375 * Specifying zero here means to use the PTE values set by the kernel;
376 * non-zero overrides the PTE values.
377 */
378 #define IVB_MOCS_LLC (1 << 1)
379
380 /* Baytrail only: snoop in CPU cache */
381 #define BYT_MOCS_SNOOP (1 << 1)
382
383 /* Haswell only: LLC/eLLC controls (write-back or uncached).
384 * Specifying zero here means to use the PTE values set by the kernel,
385 * which is useful since it offers additional control (write-through
386 * cacheing and age). Non-zero overrides the PTE values.
387 */
388 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
389 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
390 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
391
392 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
393 * and let you force write-back (WB) or write-through (WT) caching, or leave
394 * it up to the page table entry (PTE) specified by the kernel.
395 */
396 #define BDW_MOCS_WB 0x78
397 #define BDW_MOCS_WT 0x58
398 #define BDW_MOCS_PTE 0x18
399
400 /* Skylake: MOCS is now an index into an array of 62 different caching
401 * configurations programmed by the kernel.
402 */
403 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
404 #define SKL_MOCS_WB (2 << 1)
405 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
406 #define SKL_MOCS_PTE (1 << 1)
407
408 /* Cannonlake: MOCS is now an index into an array of 62 different caching
409 * configurations programmed by the kernel.
410 */
411 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
412 #define CNL_MOCS_WB (2 << 1)
413 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
414 #define CNL_MOCS_PTE (1 << 1)
415
416 /* Ice Lake uses same MOCS settings as Cannonlake */
417 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
418 #define ICL_MOCS_WB (2 << 1)
419 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
420 #define ICL_MOCS_PTE (1 << 1)
421
422 uint32_t brw_get_bo_mocs(const struct gen_device_info *devinfo,
423 struct brw_bo *bo);
424
425 #ifdef __cplusplus
426 }
427 #endif
428
429 #endif
430