1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Chen, Peng <chen.c.peng@intel.com> 26 * 27 */ 28 29 #ifndef GEN9_HEVC_ENCODER_H 30 #define GEN9_HEVC_ENCODER_H 31 32 #include <drm.h> 33 #include <i915_drm.h> 34 #include <intel_bufmgr.h> 35 36 #include <va/va.h> 37 #include "i965_gpe_utils.h" 38 #include "gen9_hevc_enc_kernels.h" 39 40 // VME parameters 41 struct hevc_enc_kernel_walker_parameter { 42 unsigned int walker_degree; 43 unsigned int use_scoreboard; 44 unsigned int scoreboard_mask; 45 unsigned int no_dependency; 46 unsigned int resolution_x; 47 unsigned int resolution_y; 48 }; 49 50 typedef enum _GEN9_HEVC_ENC_MEDIA_STATE { 51 HEVC_ENC_MEDIA_STATE_OLP = 0, 52 HEVC_ENC_MEDIA_STATE_ENC_NORMAL = 1, 53 HEVC_ENC_MEDIA_STATE_ENC_PERFORMANCE = 2, 54 HEVC_ENC_MEDIA_STATE_ENC_QUALITY = 3, 55 HEVC_ENC_MEDIA_STATE_ENC_I_FRAME_DIST = 4, 56 HEVC_ENC_MEDIA_STATE_32X_SCALING = 5, 57 HEVC_ENC_MEDIA_STATE_16X_SCALING = 6, 58 HEVC_ENC_MEDIA_STATE_4X_SCALING = 7, 59 HEVC_ENC_MEDIA_STATE_32X_ME = 8, 60 HEVC_ENC_MEDIA_STATE_16X_ME = 9, 61 HEVC_ENC_MEDIA_STATE_4X_ME = 10, 62 HEVC_ENC_MEDIA_STATE_BRC_INIT_RESET = 11, 63 HEVC_ENC_MEDIA_STATE_BRC_UPDATE = 12, 64 HEVC_ENC_MEDIA_STATE_BRC_BLOCK_COPY = 13, 65 HEVC_ENC_MEDIA_STATE_HYBRID_PAK_P1 = 14, 66 HEVC_ENC_MEDIA_STATE_HYBRID_PAK_P2 = 15, 67 HEVC_ENC_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16, 68 HEVC_ENC_MEDIA_STATE_ENC_I_FRAME_LUMA = 17, 69 HEVC_ENC_MEDIA_STATE_MPU_FHB = 18, 70 HEVC_ENC_MEDIA_STATE_TPU_FHB = 19, 71 HEVC_ENC_MEDIA_STATE_PA_COPY = 20, 72 HEVC_ENC_MEDIA_STATE_PL2_COPY = 21, 73 HEVC_ENC_MEDIA_STATE_ENC_WIDI = 22, 74 HEVC_ENC_MEDIA_STATE_2X_SCALING = 23, 75 HEVC_ENC_MEDIA_STATE_32x32_PU_MODE_DECISION = 24, 76 HEVC_ENC_MEDIA_STATE_16x16_PU_SAD = 25, 77 HEVC_ENC_MEDIA_STATE_16x16_PU_MODE_DECISION = 26, 78 HEVC_ENC_MEDIA_STATE_8x8_PU = 27, 79 HEVC_ENC_MEDIA_STATE_8x8_PU_FMODE = 28, 80 HEVC_ENC_MEDIA_STATE_32x32_B_INTRA_CHECK = 29, 81 HEVC_ENC_MEDIA_STATE_HEVC_B_MBENC = 30, 82 HEVC_ENC_MEDIA_STATE_RESET_VLINE_STRIDE = 31, 83 HEVC_ENC_MEDIA_STATE_HEVC_B_PAK = 32, 84 HEVC_ENC_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33, 85 HEVC_ENC_MEDIA_STATE_ME_VDENC_STREAMIN = 34, 86 HEVC_ENC_MEDIA_STATE_PREPROC = 51, 87 HEVC_ENC_MEDIA_STATE_ENC_WP = 52, 88 HEVC_ENC_MEDIA_STATE_HEVC_I_MBENC = 53, 89 HEVC_ENC_MEDIA_STATE_CSC_DS_COPY = 54, 90 HEVC_ENC_MEDIA_STATE_2X_4X_SCALING = 55, 91 HEVC_ENC_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56, 92 HEVC_ENC_MEDIA_STATE_MB_BRC_UPDATE = 57, 93 HEVC_ENC_MEDIA_STATE_STATIC_FRAME_DETECTION = 58, 94 HEVC_ENC_MEDIA_STATE_HEVC_ROI = 59, 95 HEVC_ENC_MEDIA_STATE_SW_SCOREBOARD_INIT = 60, 96 97 HEVC_ENC_MEDIA_STATE_DS_COMBINED = 70, 98 HEVC_ENC_NUM_MEDIA_STATES = 71 99 } GEN9_HEVC_ENC_MEDIA_STATE; 100 101 // bti table id for MBEnc/BRC kernels 102 typedef enum _GEN9_HEVC_ENC_SURFACE_TYPE { 103 HEVC_ENC_SURFACE_RAW_Y = 0, 104 HEVC_ENC_SURFACE_RAW_Y_UV, 105 HEVC_ENC_SURFACE_Y_2X, 106 HEVC_ENC_SURFACE_32x32_PU_OUTPUT, 107 HEVC_ENC_SURFACE_SLICE_MAP, 108 HEVC_ENC_SURFACE_Y_2X_VME, 109 HEVC_ENC_SURFACE_BRC_INPUT, 110 HEVC_ENC_SURFACE_LCU_QP, 111 HEVC_ENC_SURFACE_ROI, 112 HEVC_ENC_SURFACE_BRC_DATA, 113 HEVC_ENC_SURFACE_KERNEL_DEBUG, 114 HEVC_ENC_SURFACE_SIMPLIFIED_INTRA, 115 HEVC_ENC_SURFACE_HME_MVP, 116 HEVC_ENC_SURFACE_HME_DIST, 117 HEVC_ENC_SURFACE_16x16PU_SAD, 118 HEVC_ENC_SURFACE_RAW_VME, 119 HEVC_ENC_SURFACE_VME_8x8, 120 HEVC_ENC_SURFACE_CU_RECORD, 121 HEVC_ENC_SURFACE_INTRA_MODE, 122 HEVC_ENC_SURFACE_HCP_PAK, 123 HEVC_ENC_SURFACE_INTRA_DIST, 124 HEVC_ENC_SURFACE_MIN_DIST, 125 HEVC_ENC_SURFACE_VME_UNI_SIC_DATA, 126 HEVC_ENC_SURFACE_COL_MB_MV, 127 HEVC_ENC_SURFACE_CONCURRENT_THREAD, 128 HEVC_ENC_SURFACE_MB_MV_INDEX, 129 HEVC_ENC_SURFACE_MVP_INDEX, 130 HEVC_ENC_SURFACE_REF_FRAME_VME, 131 HEVC_ENC_SURFACE_Y_4X, 132 HEVC_ENC_SURFACE_Y_4X_VME, 133 HEVC_ENC_SURFACE_BRC_HISTORY, 134 HEVC_ENC_SURFACE_BRC_ME_DIST, 135 HEVC_ENC_SURFACE_BRC_PAST_PAK_INFO, 136 HEVC_ENC_SURFACE_BRC_HCP_PIC_STATE, 137 HEVC_ENC_SURFACE_RAW_10bit_Y, 138 HEVC_ENC_SURFACE_RAW_10bit_Y_UV, 139 HEVC_ENC_SURFACE_RAW_FC_8bit_Y, 140 HEVC_ENC_SURFACE_RAW_FC_8bit_Y_UV, 141 HEVC_ENC_SURFACE_RAW_MBSTAT, 142 HEVC_ENC_SURFACE_TYPE_NUM 143 } GEN9_HEVC_ENC_SURFACE_TYPE; 144 145 struct gen9_hevc_surface_parameter { 146 struct i965_gpe_resource *gpe_resource; 147 struct object_surface *surface_object; 148 dri_bo *bo; 149 }; 150 151 #define GEN9_HEVC_ENC_MIN_LCU_SIZE 16 152 #define GEN9_HEVC_ENC_MAX_LCU_SIZE 32 153 154 #define MAX_HEVC_KERNELS_ENCODER_SURFACES 64 155 #define MAX_HEVC_KERNELS_URB_SIZE 4096 156 157 #define MAX_HEVC_MAX_NUM_ROI 16 158 159 // target usage mode 160 enum HEVC_TU_MODE { 161 HEVC_TU_UNKNOWN = 0, 162 163 HEVC_TU_BEST_QUALITY = 1, 164 HEVC_TU_HI_QUALITY = 2, 165 HEVC_TU_OPT_QUALITY = 3, 166 HEVC_TU_OK_QUALITY = 5, 167 168 HEVC_TU_NO_SPEED = 1, 169 HEVC_TU_OPT_SPEED = 3, 170 HEVC_TU_RT_SPEED = 4, 171 HEVC_TU_HI_SPEED = 6, 172 HEVC_TU_BEST_SPEED = 7, 173 174 NUM_TU_MODES 175 }; 176 177 enum HEVC_BRC_METHOD { 178 HEVC_BRC_CBR, 179 HEVC_BRC_VBR, 180 HEVC_BRC_CQP, 181 HEVC_BRC_AVBR, 182 HEVC_BRC_ICQ, 183 HEVC_BRC_VCM, 184 //HEVC_BRC_QVBR, 185 //HEVC_BRC_IWD_VBR 186 }; 187 188 struct gen9_hevc_scaling_parameter { 189 VASurfaceID curr_pic; 190 void *p_scaling_bti; 191 struct object_surface *input_surface; 192 struct object_surface *output_surface; 193 unsigned int input_frame_width; 194 unsigned int input_frame_height; 195 unsigned int output_frame_width; 196 unsigned int output_frame_height; 197 unsigned int vert_line_stride; 198 unsigned int vert_line_stride_offset; 199 bool scaling_out_use_16unorm_surf_fmt; 200 bool scaling_out_use_32unorm_surf_fmt; 201 bool mbv_proc_stat_enabled; 202 bool enable_mb_flatness_check; 203 bool enable_mb_variance_output; 204 bool enable_mb_pixel_average_output; 205 bool use_4x_scaling; 206 bool use_16x_scaling; 207 bool use_32x_scaling; 208 bool blk8x8_stat_enabled; 209 struct i965_gpe_resource *pres_mbv_proc_stat_buffer; 210 }; 211 212 enum HEVC_HME_TYPE { 213 HEVC_HME_4X, 214 HEVC_HME_16X, 215 HEVC_HME_32X 216 }; 217 218 #define GEN9_HEVC_HME_SUPPORTED 1 219 #define GEN9_HEVC_16XME_SUPPORTED 1 220 #define GEN9_HEVC_32XME_SUPPORTED 0 221 222 #define GEN9_HEVC_VME_MIN_ALLOWED_SIZE 48 223 224 #define HEVC_ENC_SCALING_4X 0 225 #define HEVC_ENC_SCALING_16X 1 226 #define HEVC_ENC_SCALING_32X 2 227 #define NUM_HEVC_ENC_SCALING 3 228 229 struct gen9_hevc_scaling_context { 230 struct i965_gpe_context gpe_contexts[NUM_HEVC_ENC_SCALING]; 231 }; 232 233 #define HEVC_ENC_ME_B 0 234 #define HEVC_ENC_ME_P 1 235 #define NUM_HEVC_ENC_ME 2 236 #define NUM_HEVC_ENC_ME_TYPES 3 237 238 struct gen9_hevc_me_context { 239 struct i965_gpe_context gpe_context[NUM_HEVC_ENC_ME_TYPES][NUM_HEVC_ENC_ME]; 240 }; 241 242 #define HEVC_ENC_INTRA_TRANS_REGULAR 0 243 #define HEVC_ENC_INTRA_TRANS_RESERVED 1 244 #define HEVC_ENC_INTRA_TRANS_HAAR 2 245 #define HEVC_ENC_INTRA_TRANS_HADAMARD 3 246 247 #define MBENC_IDX(krn) (krn - GEN9_HEVC_ENC_MBENC_2xSCALING) 248 249 #define HEVC_MBENC_2xSCALING_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_2xSCALING) 250 #define HEVC_MBENC_32x32MD_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_32x32MD) 251 #define HEVC_MBENC_16x16SAD_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_16x16SAD) 252 #define HEVC_MBENC_16x16MD_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_16x16MD) 253 #define HEVC_MBENC_8x8PU_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_8x8PU) 254 #define HEVC_MBENC_8x8FMODE_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_8x8FMODE) 255 #define HEVC_MBENC_32x32INTRACHECK_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_32x32INTRACHECK) 256 #define HEVC_MBENC_BENC_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_BENC) 257 #define HEVC_MBENC_BPAK_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_BPAK) 258 #define HEVC_MBENC_MBENC_WIDI_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_WIDI) 259 #define HEVC_MBENC_DS_COMBINED_IDX MBENC_IDX(GEN9_HEVC_ENC_MBENC_DS_COMBINED) 260 #define HEVC_MBENC_PENC_IDX MBENC_IDX(GEN9_HEVC_MBENC_PENC) 261 #define HEVC_MBENC_P_WIDI_IDX MBENC_IDX(GEN9_HEVC_MBENC_P_WIDI) 262 263 static const int hevc_mbenc_curbe_size[GEN8_HEVC_ENC_MBENC_TOTAL_NUM] = { 264 sizeof(gen9_hevc_mbenc_downscaling2x_curbe_data), 265 sizeof(gen9_hevc_mbenc_32x32_pu_mode_curbe_data), 266 sizeof(gen9_hevc_mbenc_16x16_sad_curbe_data), 267 sizeof(gen9_hevc_enc_16x16_pu_curbe_data), 268 sizeof(gen9_hevc_mbenc_8x8_pu_curbe_data), 269 sizeof(gen9_hevc_mbenc_8x8_pu_fmode_curbe_data), 270 sizeof(gen9_hevc_mbenc_b_32x32_pu_intra_curbe_data), 271 sizeof(gen9_hevc_mbenc_b_mb_enc_curbe_data), 272 sizeof(gen9_hevc_mbenc_b_pak_curbe_data), 273 sizeof(gen9_hevc_mbenc_b_mb_enc_curbe_data), 274 sizeof(gen95_hevc_mbenc_ds_combined_curbe_data), 275 sizeof(gen9_hevc_mbenc_b_mb_enc_curbe_data), 276 sizeof(gen9_hevc_mbenc_b_mb_enc_curbe_data), 277 }; 278 279 #define GEN9_HEVC_MEDIA_WALKER_MAX_COLORS 16 280 281 struct gen9_hevc_walking_pattern_parameter { 282 struct gpe_media_object_walker_parameter gpe_param; 283 284 int offset_y; 285 int offset_delta; 286 unsigned int num_region; 287 unsigned int max_height_in_region; 288 unsigned int num_units_in_region; 289 }; 290 291 struct gen9_hevc_mbenc_context { 292 struct i965_gpe_context gpe_contexts[GEN8_HEVC_ENC_MBENC_TOTAL_NUM]; 293 294 int kernel_num; 295 }; 296 297 #define HEVC_BRC_KBPS 1000 298 #define HEVC_BRC_MIN_TARGET_PERCENTAGE 50 299 300 #define BRC_IDX(krn) (krn - GEN9_HEVC_ENC_BRC_COARSE_INTRA) 301 302 #define HEVC_BRC_COARSE_INTRA_IDX BRC_IDX(GEN9_HEVC_ENC_BRC_COARSE_INTRA) 303 #define HEVC_BRC_INIT_IDX BRC_IDX(GEN9_HEVC_ENC_BRC_INIT) 304 #define HEVC_BRC_RESET_IDX BRC_IDX(GEN9_HEVC_ENC_BRC_RESET) 305 #define HEVC_BRC_FRAME_UPDATE_IDX BRC_IDX(GEN9_HEVC_ENC_BRC_FRAME_UPDATE) 306 #define HEVC_BRC_LCU_UPDATE_IDX BRC_IDX(GEN9_HEVC_ENC_BRC_LCU_UPDATE) 307 308 static int hevc_brc_curbe_size[GEN9_HEVC_ENC_BRC_NUM] = { 309 sizeof(gen9_hevc_brc_coarse_intra_curbe_data), 310 sizeof(gen9_hevc_brc_initreset_curbe_data), 311 sizeof(gen9_hevc_brc_initreset_curbe_data), 312 sizeof(gen9_hevc_brc_udpate_curbe_data), 313 sizeof(gen9_hevc_brc_udpate_curbe_data), 314 }; 315 316 struct gen9_hevc_brc_context { 317 struct i965_gpe_context gpe_contexts[GEN9_HEVC_ENC_BRC_NUM]; 318 }; 319 320 struct gen9_hevc_slice_map { 321 unsigned char slice_id; 322 unsigned char reserved[3]; 323 }; 324 325 // PAK paramerters 326 #define GEN9_HEVC_ENC_BRC_PIC_STATE_SIZE (128) 327 #define GEN9_HEVC_ENC_BRC_PAK_STATISTCS_SIZE (32) 328 #define GEN9_HEVC_ENC_BRC_HISTORY_BUFFER_SIZE (576) 329 330 #define GEN9_HEVC_ENC_BRC_CONSTANT_SURFACE_WIDTH (64) 331 #define GEN9_HEVC_ENC_BRC_CONSTANT_SURFACE_HEIGHT (53) 332 333 #define GEN9_HEVC_ENC_PAK_OBJ_SIZE (3 + 1) 334 #define GEN95_HEVC_ENC_PAK_OBJ_SIZE (5 + 3) 335 336 #define GEN9_HEVC_ENC_PAK_CU_RECORD_SIZE (16) 337 338 #define GEN9_HEVC_ENC_PAK_SLICE_STATE_SIZE 4096 339 340 #define GEN9_MAX_REF_SURFACES 8 341 #define GEN9_MAX_MV_TEMPORAL_BUFFERS (GEN9_MAX_REF_SURFACES + 1) 342 343 #define GEN9_HEVC_NUM_MAX_REF_L0 3 344 #define GEN9_HEVC_NUM_MAX_REF_L1 1 345 346 enum GEN9_HEVC_ENC_SURFACE_TYPE { 347 GEN9_HEVC_ENC_SURFACE_RECON = 0, 348 GEN9_HEVC_ENC_SURFACE_SOURCE = 1 349 }; 350 351 #define HEVC_SCALED_SURF_4X_ID 0 352 #define HEVC_SCALED_SURF_16X_ID 1 353 #define HEVC_SCALED_SURF_32X_ID 2 354 #define HEVC_SCALED_SURFS_NUM (HEVC_SCALED_SURF_32X_ID + 1) 355 356 struct gen9_hevc_surface_priv { 357 VADriverContextP ctx; 358 359 dri_bo *motion_vector_temporal_bo; 360 361 VASurfaceID scaled_surface_id[HEVC_SCALED_SURFS_NUM]; 362 struct object_surface *scaled_surface_obj[HEVC_SCALED_SURFS_NUM]; 363 364 VASurfaceID surface_id_nv12; 365 struct object_surface *surface_obj_nv12; 366 int surface_nv12_valid; 367 368 struct object_surface *surface_reff; 369 370 int qp_value; 371 }; 372 373 struct hevc_enc_image_status_ctrl { 374 unsigned int lcu_max_size_violate: 1; 375 unsigned int frame_bit_count_violate_overrun: 1; 376 unsigned int frame_bit_count_violate_underrun: 1; 377 unsigned int reserverd1: 5; 378 unsigned int total_pass: 4; 379 unsigned int reserverd2: 4; 380 unsigned int cumulative_frame_delta_lf: 7; 381 unsigned int reserverd3: 1; 382 unsigned int cumulative_frame_delta_qp: 8; 383 }; 384 385 struct hevc_encode_status { 386 // MUST don't move two fields image_status_mask 387 // and image_status_ctrl 388 unsigned int image_status_mask; 389 unsigned int image_status_ctrl; 390 unsigned int image_status_ctrl_last_pass; 391 unsigned int bs_byte_count; 392 unsigned int pass_num; 393 unsigned int media_state; 394 }; 395 396 #define MMIO_HCP_ENC_BITSTREAM_BYTECOUNT_FRAME_OFFSET 0x1E9A0 397 #define MMIO_HCP_ENC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER_OFFSET 0x1E9A4 398 #define MMIO_HCP_ENC_IMAGE_STATUS_MASK_OFFSET 0x1E9B8 399 #define MMIO_HCP_ENC_IMAGE_STATUS_CTRL_OFFSET 0x1E9BC 400 401 struct hevc_encode_status_buffer { 402 dri_bo *bo; 403 404 unsigned int status_bs_byte_count_offset; 405 unsigned int status_image_mask_offset; 406 unsigned int status_image_ctrl_offset; 407 unsigned int status_image_ctrl_last_pass_offset; 408 409 unsigned int mmio_bs_frame_offset; 410 unsigned int mmio_bs_frame_no_header_offset; 411 unsigned int mmio_image_mask_offset; 412 unsigned int mmio_image_ctrl_offset; 413 414 unsigned int status_pass_num_offset; 415 unsigned int status_media_state_offset; 416 }; 417 418 struct gen9_hevc_encoder_state { 419 int picture_width; 420 int picture_height; 421 unsigned int picture_coding_type; 422 unsigned int bit_depth_luma_minus8; 423 unsigned int bit_depth_chroma_minus8; 424 425 int cu_size; 426 int lcu_size; 427 int width_in_lcu; 428 int height_in_lcu; 429 int width_in_cu; 430 int height_in_cu; 431 int width_in_mb; 432 int height_in_mb; 433 434 int mb_data_offset; 435 int mb_code_size; 436 int pak_obj_size; 437 int cu_record_size; 438 int pic_state_size; 439 int slice_batch_offset[I965_MAX_NUM_SLICE]; 440 int slice_start_lcu[I965_MAX_NUM_SLICE]; 441 442 struct hevc_encode_status_buffer status_buffer; 443 enum HEVC_TU_MODE tu_mode; 444 445 //HME width&height 446 unsigned int frame_width_in_max_lcu; 447 unsigned int frame_height_in_max_lcu; 448 unsigned int frame_width_4x; 449 unsigned int frame_height_4x; 450 unsigned int frame_width_16x; 451 unsigned int frame_height_16x; 452 unsigned int frame_width_32x; 453 unsigned int frame_height_32x; 454 unsigned int downscaled_width_4x_in_mb; 455 unsigned int downscaled_height_4x_in_mb; 456 unsigned int downscaled_width_16x_in_mb; 457 unsigned int downscaled_height_16x_in_mb; 458 unsigned int downscaled_width_32x_in_mb; 459 unsigned int downscaled_height_32x_in_mb; 460 461 unsigned int flatness_check_enable : 1; 462 unsigned int flatness_check_supported : 1; 463 unsigned int res_bits : 30; 464 465 // brc state 466 enum HEVC_BRC_METHOD brc_method; 467 unsigned int frames_per_100s; 468 unsigned int user_max_frame_size; 469 unsigned int init_vbv_buffer_fullness_in_bit; 470 unsigned int vbv_buffer_size_in_bit; 471 unsigned int target_bit_rate_in_kbs; 472 unsigned int max_bit_rate_in_kbs; 473 unsigned int min_bit_rate_in_kbs; 474 unsigned int gop_size; 475 unsigned int gop_ref_dist; 476 unsigned int crf_quality_factor; 477 unsigned int num_b_in_gop[3]; 478 double brc_init_current_target_buf_full_in_bits; 479 double brc_init_reset_input_bits_per_frame; 480 unsigned int brc_init_reset_buf_size_in_bits; 481 unsigned int num_skip_frames; 482 unsigned int size_skip_frames; 483 unsigned int frame_number; 484 unsigned int parallel_brc; 485 486 unsigned int num_roi; 487 unsigned int roi_value_is_qp_delta; 488 unsigned int max_delta_qp; 489 unsigned int min_delta_qp; 490 struct intel_roi roi[MAX_HEVC_MAX_NUM_ROI]; 491 492 unsigned int video_surveillance_flag; 493 494 unsigned int lcu_brc_enabled : 1; 495 unsigned int low_delay : 1; 496 unsigned int arbitrary_num_mb_in_slice : 1; 497 unsigned int rolling_intra_refresh : 1; 498 unsigned int walking_pattern_26 : 1; 499 unsigned int use_hw_scoreboard : 1; 500 unsigned int use_hw_non_stalling_scoreborad : 1; 501 unsigned int power_saving : 1; 502 unsigned int reserverd : 24; 503 504 unsigned int fixed_point_lambda_for_luma; 505 unsigned int fixed_point_lambda_for_chroma; 506 507 int num_regions_in_slice; 508 509 unsigned int widi_first_intra_refresh; 510 unsigned int widi_frame_num_in_gob; 511 unsigned int widi_frame_num_without_intra_refresh; 512 unsigned int widi_intra_insertion_location; 513 unsigned int widi_intra_insertion_size; 514 unsigned int widi_intra_refresh_qp_delta; 515 516 unsigned int ctu_max_bitsize_allowed; 517 }; 518 519 struct gen9_hevc_encoder_context { 520 struct gen9_hevc_scaling_context scaling_context; 521 struct gen9_hevc_me_context me_context; 522 struct gen9_hevc_mbenc_context mbenc_context; 523 struct gen9_hevc_brc_context brc_context; 524 VADriverContextP ctx; 525 526 struct gen9_hevc_surface_parameter gpe_surfaces[HEVC_ENC_SURFACE_TYPE_NUM]; 527 528 double lambda_md_table[3][52]; 529 double lambda_me_table[3][52]; 530 unsigned int lambda_table_inited; 531 unsigned int lambda_intra_trans_type; 532 533 VASurfaceID scaled_2x_surface_id; 534 struct object_surface *scaled_2x_surface_obj; 535 536 unsigned int mocs; 537 538 // PAK internal pipe buffers 539 struct i965_gpe_resource deblocking_filter_line_buffer; 540 struct i965_gpe_resource deblocking_filter_tile_line_buffer; 541 struct i965_gpe_resource deblocking_filter_tile_column_buffer; 542 struct i965_gpe_resource metadata_line_buffer; 543 struct i965_gpe_resource metadata_tile_line_buffer; 544 struct i965_gpe_resource metadata_tile_column_buffer; 545 struct i965_gpe_resource sao_line_buffer; 546 struct i965_gpe_resource sao_tile_line_buffer; 547 struct i965_gpe_resource sao_tile_column_buffer; 548 549 struct { 550 dri_bo *bo; 551 int offset; 552 int end_offset; 553 int status_offset; 554 } indirect_pak_bse_object; 555 556 struct { 557 struct object_surface *obj_surface; 558 VASurfaceID surface_id; 559 dri_bo *obj_surface_bo; 560 } uncompressed_picture_source; 561 562 struct { 563 struct object_surface *obj_surface; 564 VASurfaceID surface_id; 565 dri_bo *obj_surface_bo; 566 } reconstructed_object; 567 568 struct { 569 struct object_surface *obj_surface; 570 VASurfaceID surface_id; 571 dri_bo *obj_surface_bo; 572 } reference_surfaces[GEN9_MAX_REF_SURFACES]; 573 574 struct { 575 dri_bo *bo; 576 } mv_temporal_buffer[GEN9_MAX_MV_TEMPORAL_BUFFERS]; 577 578 int res_inited; 579 struct intel_batchbuffer *res_pak_slice_batch_buffer; 580 struct i965_gpe_resource res_mb_code_surface; 581 struct i965_gpe_resource res_brc_pic_states_write_buffer; 582 struct i965_gpe_resource res_brc_pic_states_read_buffer; 583 struct i965_gpe_resource res_brc_history_buffer; 584 struct i965_gpe_resource res_brc_intra_dist_buffer; 585 struct i965_gpe_resource res_brc_me_dist_buffer; 586 struct i965_gpe_resource res_brc_input_buffer_for_enc_kernels; 587 struct i965_gpe_resource res_brc_pak_statistic_buffer; 588 struct i965_gpe_resource res_brc_constant_data_buffer; 589 struct i965_gpe_resource res_brc_mb_qp_buffer; 590 struct i965_gpe_resource res_flatness_check_surface; 591 struct i965_gpe_resource s4x_memv_distortion_buffer; 592 struct i965_gpe_resource s4x_memv_data_buffer; 593 struct i965_gpe_resource s16x_memv_data_buffer; 594 struct i965_gpe_resource s32x_memv_data_buffer; 595 struct i965_gpe_resource res_32x32_pu_output_buffer; 596 struct i965_gpe_resource res_slice_map_buffer; 597 struct i965_gpe_resource res_simplest_intra_buffer; 598 struct i965_gpe_resource res_kernel_debug; 599 struct i965_gpe_resource res_sad_16x16_pu_buffer; 600 struct i965_gpe_resource res_vme_8x8_mode_buffer; 601 struct i965_gpe_resource res_intra_mode_buffer; 602 struct i965_gpe_resource res_intra_distortion_buffer; 603 struct i965_gpe_resource res_min_distortion_buffer; 604 struct i965_gpe_resource res_vme_uni_sic_buffer; 605 struct i965_gpe_resource res_con_corrent_thread_buffer; 606 struct i965_gpe_resource res_mv_index_buffer; 607 struct i965_gpe_resource res_mvp_index_buffer; 608 struct i965_gpe_resource res_roi_buffer; 609 struct i965_gpe_resource res_mb_statistics_buffer; 610 }; 611 612 #endif 613