1 /** @file 2 3 Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 4 Copyright (c) 2020, ARM Limited. All rights reserved. 5 Copyright (c) 2020 Andrey Warkentin <andrey.warkentin@gmail.com> 6 7 SPDX-License-Identifier: BSD-2-Clause-Patent 8 9 **/ 10 11 #ifndef BCM_GENET_DXE_H__ 12 #define BCM_GENET_DXE_H__ 13 14 #include <Uefi.h> 15 #include <Library/UefiLib.h> 16 #include <Protocol/BcmGenetPlatformDevice.h> 17 #include <Protocol/AdapterInformation.h> 18 #include <Protocol/ComponentName.h> 19 #include <Protocol/ComponentName2.h> 20 #include <Protocol/SimpleNetwork.h> 21 22 #include "GenericPhy.h" 23 24 #define LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 25 #define SHIFTOUT(__x, __mask) (((__x) & (__mask)) / LOWEST_SET_BIT (__mask)) 26 #define SHIFTIN(__x, __mask) ((__x) * LOWEST_SET_BIT (__mask)) 27 28 /* 29 * Aux control shadow register, bits 0-2 select function (0x00 to 30 * 0x07). 31 */ 32 #define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 33 #define BRGPHY_AUXCTL_SHADOW_MISC 0x07 34 #define BRGPHY_AUXCTL_MISC_DATA_MASK 0x7ff8 35 #define BRGPHY_AUXCTL_MISC_READ_SHIFT 12 36 #define BRGPHY_AUXCTL_MISC_WRITE_EN 0x8000 37 #define BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN 0x0200 38 39 /* 40 * Shadow register 0x1C, bit 15 is write enable, 41 * bits 14-10 select function (0x00 to 0x1F). 42 */ 43 #define BRGPHY_MII_SHADOW_1C 0x1C 44 #define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 45 #define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 46 #define BRGPHY_SHADOW_1C_DATA_MASK 0x03FF 47 48 /* Shadow 0x1C Clock Alignment Control Register (select value 0x03) */ 49 #define BRGPHY_SHADOW_1C_CLK_CTRL (0x03 << 10) 50 #define BRGPHY_SHADOW_1C_GTXCLK_EN 0x0200 51 52 #define MAX_ETHERNET_PKT_SIZE 1500 53 54 #define GENET_VERSION 0x0a 55 #define GENET_MAX_PACKET_SIZE 1536 56 57 #define GENET_SYS_REV_CTRL 0x000 58 #define SYS_REV_MAJOR (BIT27|BIT26|BIT25|BIT24) 59 #define SYS_REV_MINOR (BIT19|BIT18|BIT17|BIT16) 60 #define GENET_SYS_PORT_CTRL 0x004 61 #define GENET_SYS_PORT_MODE_EXT_GPHY 3 62 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008 63 #define GENET_SYS_RBUF_FLUSH_RESET BIT1 64 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c 65 #define GENET_EXT_RGMII_OOB_CTRL 0x08c 66 #define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE BIT16 67 #define GENET_EXT_RGMII_OOB_RGMII_MODE_EN BIT6 68 #define GENET_EXT_RGMII_OOB_OOB_DISABLE BIT5 69 #define GENET_EXT_RGMII_OOB_RGMII_LINK BIT4 70 #define GENET_INTRL2_CPU_STAT 0x200 71 #define GENET_INTRL2_CPU_CLEAR 0x208 72 #define GENET_INTRL2_CPU_STAT_MASK 0x20c 73 #define GENET_INTRL2_CPU_SET_MASK 0x210 74 #define GENET_INTRL2_CPU_CLEAR_MASK 0x214 75 #define GENET_IRQ_MDIO_ERROR BIT24 76 #define GENET_IRQ_MDIO_DONE BIT23 77 #define GENET_IRQ_TXDMA_DONE BIT16 78 #define GENET_IRQ_RXDMA_DONE BIT13 79 #define GENET_RBUF_CTRL 0x300 80 #define GENET_RBUF_BAD_DIS BIT2 81 #define GENET_RBUF_ALIGN_2B BIT1 82 #define GENET_RBUF_64B_EN BIT0 83 #define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4 84 #define GENET_UMAC_CMD 0x808 85 #define GENET_UMAC_CMD_LCL_LOOP_EN BIT15 86 #define GENET_UMAC_CMD_SW_RESET BIT13 87 #define GENET_UMAC_CMD_HD_EN BIT10 88 #define GENET_UMAC_CMD_PROMISC BIT4 89 #define GENET_UMAC_CMD_SPEED (BIT3|BIT2) 90 #define GENET_UMAC_CMD_SPEED_10 0 91 #define GENET_UMAC_CMD_SPEED_100 1 92 #define GENET_UMAC_CMD_SPEED_1000 2 93 #define GENET_UMAC_CMD_RXEN BIT1 94 #define GENET_UMAC_CMD_TXEN BIT0 95 #define GENET_UMAC_MAC0 0x80c 96 #define GENET_UMAC_MAC1 0x810 97 #define GENET_UMAC_MAX_FRAME_LEN 0x814 98 #define GENET_UMAC_TX_FLUSH 0xb34 99 #define GENET_UMAC_MIB_CTRL 0xd80 100 #define GENET_UMAC_MIB_RESET_TX BIT2 101 #define GENET_UMAC_MIB_RESET_RUNT BIT1 102 #define GENET_UMAC_MIB_RESET_RX BIT0 103 #define GENET_MDIO_CMD 0xe14 104 #define GENET_MDIO_START_BUSY BIT29 105 #define GENET_MDIO_READ BIT27 106 #define GENET_MDIO_WRITE BIT26 107 #define GENET_MDIO_PMD (BIT25|BIT24|BIT23|BIT22|BIT21) 108 #define GENET_MDIO_REG (BIT20|BIT19|BIT18|BIT17|BIT16) 109 #define GENET_UMAC_MDF_CTRL 0xe50 110 #define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8) 111 #define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8) 112 #define GENET_MAX_MDF_FILTER 17 113 114 #define GENET_DMA_DESC_COUNT 256 115 #define GENET_DMA_DESC_SIZE 12 116 #define GENET_DMA_DEFAULT_QUEUE 16 117 118 #define GENET_DMA_RING_SIZE 0x40 119 #define GENET_DMA_RINGS_SIZE (GENET_DMA_RING_SIZE * (GENET_DMA_DEFAULT_QUEUE + 1)) 120 121 #define GENET_RX_BASE 0x2000 122 #define GENET_TX_BASE 0x4000 123 124 #define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 125 #define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00) 126 #define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04) 127 #define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08) 128 #define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c) 129 #define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10) 130 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT 0xffff0000 131 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH 0x0000ffff 132 #define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14) 133 #define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18) 134 #define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c) 135 #define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20) 136 #define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28) 137 #define GENET_RX_DMA_XON_XOFF_THRES_LO 0xffff0000 138 #define GENET_RX_DMA_XON_XOFF_THRES_HI 0x0000ffff 139 #define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c) 140 #define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30) 141 142 #define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 143 #define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00) 144 #define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04) 145 #define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08) 146 #define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c) 147 #define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10) 148 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT 0xffff0000 149 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH 0x0000ffff 150 #define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14) 151 #define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18) 152 #define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c) 153 #define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20) 154 #define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24) 155 #define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28) 156 #define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c) 157 #define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30) 158 159 #define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 160 #define GENET_RX_DESC_STATUS_BUFLEN (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16) 161 #define GENET_RX_DESC_STATUS_OWN BIT15 162 #define GENET_RX_DESC_STATUS_EOP BIT14 163 #define GENET_RX_DESC_STATUS_SOP BIT13 164 #define GENET_RX_DESC_STATUS_RX_ERROR BIT2 165 #define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 166 #define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 167 168 #define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 169 #define GENET_TX_DESC_STATUS_BUFLEN (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16) 170 #define GENET_TX_DESC_STATUS_OWN BIT15 171 #define GENET_TX_DESC_STATUS_EOP BIT14 172 #define GENET_TX_DESC_STATUS_SOP BIT13 173 #define GENET_TX_DESC_STATUS_QTAG (BIT12|BIT11|BIT10|BIT9|BIT8|BIT7) 174 #define GENET_TX_DESC_STATUS_CRC BIT6 175 #define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 176 #define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 177 178 #define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00) 179 #define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04) 180 #define GENET_RX_DMA_CTRL_RBUF_EN(qid) (BIT1 << (qid)) 181 #define GENET_RX_DMA_CTRL_EN BIT0 182 #define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c) 183 184 #define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00) 185 #define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04) 186 #define GENET_TX_DMA_CTRL_RBUF_EN(qid) (BIT1 << (qid)) 187 #define GENET_TX_DMA_CTRL_EN BIT0 188 #define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c) 189 190 typedef struct { 191 EFI_PHYSICAL_ADDRESS PhysAddress; 192 VOID * Mapping; 193 } GENET_MAP_INFO; 194 195 typedef enum { 196 GENET_PHY_MODE_MII, 197 GENET_PHY_MODE_RGMII, 198 GENET_PHY_MODE_RGMII_RXID, 199 GENET_PHY_MODE_RGMII_TXID, 200 GENET_PHY_MODE_RGMII_ID, 201 } GENET_PHY_MODE; 202 203 typedef struct { 204 UINT32 Signature; 205 EFI_HANDLE ControllerHandle; 206 207 EFI_LOCK Lock; 208 EFI_EVENT ExitBootServicesEvent; 209 210 EFI_SIMPLE_NETWORK_PROTOCOL Snp; 211 EFI_SIMPLE_NETWORK_MODE SnpMode; 212 213 EFI_ADAPTER_INFORMATION_PROTOCOL Aip; 214 215 BCM_GENET_PLATFORM_DEVICE_PROTOCOL *Dev; 216 217 GENERIC_PHY_PRIVATE_DATA Phy; 218 219 UINT8 *TxBuffer[GENET_DMA_DESC_COUNT]; 220 VOID *TxBufferMap[GENET_DMA_DESC_COUNT]; 221 UINT8 TxQueued; 222 UINT16 TxNext; 223 UINT16 TxConsIndex; 224 UINT16 TxProdIndex; 225 226 EFI_PHYSICAL_ADDRESS RxBuffer; 227 GENET_MAP_INFO RxBufferMap[GENET_DMA_DESC_COUNT]; 228 UINT16 RxConsIndex; 229 UINT16 RxProdIndex; 230 231 GENET_PHY_MODE PhyMode; 232 233 UINTN RegBase; 234 } GENET_PRIVATE_DATA; 235 236 extern EFI_COMPONENT_NAME_PROTOCOL gGenetComponentName; 237 extern EFI_COMPONENT_NAME2_PROTOCOL gGenetComponentName2; 238 extern EFI_DRIVER_BINDING_PROTOCOL mGenetDriverBinding; 239 240 extern CONST EFI_SIMPLE_NETWORK_PROTOCOL gGenetSimpleNetworkTemplate; 241 extern CONST EFI_ADAPTER_INFORMATION_PROTOCOL gGenetAdapterInfoTemplate; 242 243 #define GENET_DRIVER_SIGNATURE SIGNATURE_32('G', 'N', 'E', 'T') 244 #define GENET_PRIVATE_DATA_FROM_SNP_THIS(a) CR(a, GENET_PRIVATE_DATA, Snp, GENET_DRIVER_SIGNATURE) 245 #define GENET_PRIVATE_DATA_FROM_AIP_THIS(a) CR(a, GENET_PRIVATE_DATA, Aip, GENET_DRIVER_SIGNATURE) 246 247 #define GENET_RX_BUFFER(g, idx) ((UINT8 *)(UINTN)(g)->RxBuffer + GENET_MAX_PACKET_SIZE * (idx)) 248 249 EFI_STATUS 250 EFIAPI 251 GenetPhyRead ( 252 IN VOID *Priv, 253 IN UINT8 PhyAddr, 254 IN UINT8 Reg, 255 OUT UINT16 *Data 256 ); 257 258 EFI_STATUS 259 EFIAPI 260 GenetPhyWrite ( 261 IN VOID *Priv, 262 IN UINT8 PhyAddr, 263 IN UINT8 Reg, 264 IN UINT16 Data 265 ); 266 267 EFI_STATUS 268 EFIAPI 269 GenetPhyResetAction ( 270 IN VOID *Priv 271 ); 272 273 VOID 274 EFIAPI 275 GenetPhyConfigure ( 276 IN VOID *Priv, 277 IN GENERIC_PHY_SPEED Speed, 278 IN GENERIC_PHY_DUPLEX Duplex 279 ); 280 281 VOID 282 GenetReset ( 283 IN GENET_PRIVATE_DATA *Genet 284 ); 285 286 VOID 287 EFIAPI 288 GenetSetMacAddress ( 289 IN GENET_PRIVATE_DATA *Genet, 290 IN EFI_MAC_ADDRESS *MacAddr 291 ); 292 293 VOID 294 GenetSetPhyMode ( 295 IN GENET_PRIVATE_DATA *Genet, 296 IN GENET_PHY_MODE PhyMode 297 ); 298 299 VOID 300 GenetEnableTxRx ( 301 IN GENET_PRIVATE_DATA *Genet 302 ); 303 304 VOID 305 GenetDisableTxRx ( 306 IN GENET_PRIVATE_DATA *Genet 307 ); 308 309 VOID 310 GenetSetPromisc ( 311 IN GENET_PRIVATE_DATA *Genet, 312 IN BOOLEAN Enable 313 ); 314 315 VOID 316 GenetEnableBroadcastFilter ( 317 IN GENET_PRIVATE_DATA *Genet, 318 IN BOOLEAN Enable 319 ); 320 321 VOID 322 GenetDmaInitRings ( 323 IN GENET_PRIVATE_DATA *Genet 324 ); 325 326 EFI_STATUS 327 GenetDmaAlloc ( 328 IN GENET_PRIVATE_DATA *Genet 329 ); 330 331 VOID 332 GenetDmaFree ( 333 IN GENET_PRIVATE_DATA *Genet 334 ); 335 336 VOID 337 GenetDmaTriggerTx ( 338 IN GENET_PRIVATE_DATA *Genet, 339 IN UINT8 DescIndex, 340 IN EFI_PHYSICAL_ADDRESS PhysAddr, 341 IN UINTN NumberOfBytes 342 ); 343 344 EFI_STATUS 345 GenetDmaMapRxDescriptor ( 346 IN GENET_PRIVATE_DATA *Genet, 347 IN UINT8 DescIndex 348 ); 349 350 VOID 351 GenetDmaUnmapRxDescriptor ( 352 IN GENET_PRIVATE_DATA *Genet, 353 IN UINT8 DescIndex 354 ); 355 356 VOID 357 GenetTxIntr ( 358 IN GENET_PRIVATE_DATA *Genet, 359 OUT VOID **TxBuf 360 ); 361 362 UINT32 363 GenetRxPending ( 364 IN GENET_PRIVATE_DATA *Genet 365 ); 366 367 UINT32 368 GenetTxPending ( 369 IN GENET_PRIVATE_DATA *Genet 370 ); 371 372 EFI_STATUS 373 GenetRxIntr ( 374 IN GENET_PRIVATE_DATA *Genet, 375 OUT UINT8 *DescIndex, 376 OUT UINTN *FrameLength 377 ); 378 379 VOID 380 GenetRxComplete ( 381 IN GENET_PRIVATE_DATA *Genet 382 ); 383 384 #endif /* GENET_UTIL_H__ */ 385