1 /* $NetBSD: qatreg.h,v 1.3 2022/04/08 10:27:04 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright(c) 2007-2019 Intel Corporation. All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name of Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #ifndef _DEV_PCI_QATREG_H_ 60 #define _DEV_PCI_QATREG_H_ 61 62 /* Limits */ 63 #define MAX_NUM_AE 0x10 64 #define MAX_NUM_ACCEL 6 /* XXX DH89XXCL? */ 65 #define MAX_AE 0x18 66 #define MAX_AE_CTX 8 67 #define MAX_ARB 4 68 69 #define MAX_USTORE_PER_SEG 0x8000 /* 16k * 2 */ 70 #define MAX_USTORE MAX_USTORE_PER_SEG 71 72 #define MAX_AE_PER_ACCEL 4 /* XXX */ 73 #define MAX_BANK_PER_ACCEL 16 /* XXX */ 74 #define MAX_RING_PER_BANK 16 75 76 #define MAX_XFER_REG 128 77 #define MAX_GPR_REG 128 78 #define MAX_NN_REG 128 79 #define MAX_LMEM_REG 1024 80 #define MAX_INP_STATE 16 81 #define MAX_CAM_REG 16 82 #define MAX_FIFO_QWADDR 160 83 84 #define MAX_EXEC_INST 100 85 #define UWORD_CPYBUF_SIZE 1024 /* micro-store copy buffer (bytes) */ 86 #define INVLD_UWORD 0xffffffffffull /* invalid micro-instruction */ 87 #define AEV2_PACKED_UWORD_BYTES 6 /* version 2 packed uword size */ 88 #define UWORD_MASK 0xbffffffffffull /* micro-word mask without parity */ 89 90 #define AE_ALL_CTX 0xff 91 92 /* PCIe configuration space parameter */ 93 #define NO_PCI_REG (-1) 94 #define NO_REG_OFFSET 0 95 96 #define MAX_BARS 3 97 98 /* Fuse Control */ 99 #define FUSECTL_REG 0x40 100 #define FUSECTL_MASK __BIT(31) 101 102 #define LEGFUSE_REG 0x4c 103 #define LEGFUSE_ACCEL_MASK_CIPHER_SLICE __BIT(0) 104 #define LEGFUSE_ACCEL_MASK_AUTH_SLICE __BIT(1) 105 #define LEGFUSE_ACCEL_MASK_PKE_SLICE __BIT(2) 106 #define LEGFUSE_ACCEL_MASK_COMPRESS_SLICE __BIT(3) 107 #define LEGFUSE_ACCEL_MASK_LZS_SLICE __BIT(4) 108 #define LEGFUSE_ACCEL_MASK_EIA3_SLICE __BIT(5) 109 #define LEGFUSE_ACCEL_MASK_SHA3_SLICE __BIT(6) 110 111 /* -------------------------------------------------------------------------- */ 112 /* PETRINGCSR region */ 113 114 /* ETR parameters */ 115 #define ETR_MAX_RINGS_PER_BANK 16 116 117 /* ETR registers */ 118 #define ETR_RING_CONFIG 0x0000 119 #define ETR_RING_LBASE 0x0040 120 #define ETR_RING_UBASE 0x0080 121 #define ETR_RING_HEAD_OFFSET 0x00C0 122 #define ETR_RING_TAIL_OFFSET 0x0100 123 #define ETR_RING_STAT 0x0140 124 #define ETR_UO_STAT 0x0148 125 #define ETR_E_STAT 0x014C 126 #define ETR_NE_STAT 0x0150 127 #define ETR_NF_STAT 0x0154 128 #define ETR_F_STAT 0x0158 129 #define ETR_C_STAT 0x015C 130 #define ETR_INT_EN 0x016C 131 #define ETR_INT_REG 0x0170 132 #define ETR_INT_SRCSEL 0x0174 133 #define ETR_INT_SRCSEL_2 0x0178 134 #define ETR_INT_COL_EN 0x017C 135 #define ETR_INT_COL_CTL 0x0180 136 #define ETR_AP_NF_MASK 0x2000 137 #define ETR_AP_NF_DEST 0x2020 138 #define ETR_AP_NE_MASK 0x2040 139 #define ETR_AP_NE_DEST 0x2060 140 #define ETR_AP_DELAY 0x2080 141 142 /* ARB registers */ 143 #define ARB_OFFSET 0x30000 144 #define ARB_REG_SIZE 0x4 145 #define ARB_WTR_SIZE 0x20 146 #define ARB_REG_SLOT 0x1000 147 #define ARB_WTR_OFFSET 0x010 148 #define ARB_RO_EN_OFFSET 0x090 149 #define ARB_WRK_2_SER_MAP_OFFSET 0x180 150 #define ARB_RINGSRVARBEN_OFFSET 0x19c 151 152 /* Ring Config */ 153 #define ETR_RING_CONFIG_LATE_HEAD_POINTER_MODE __BIT(31) 154 #define ETR_RING_CONFIG_NEAR_FULL_WM __BITS(14, 10) 155 #define ETR_RING_CONFIG_NEAR_EMPTY_WM __BITS(9, 5) 156 #define ETR_RING_CONFIG_RING_SIZE __BITS(4, 0) 157 158 #define ETR_RING_CONFIG_NEAR_WM_0 0x00 159 #define ETR_RING_CONFIG_NEAR_WM_4 0x01 160 #define ETR_RING_CONFIG_NEAR_WM_8 0x02 161 #define ETR_RING_CONFIG_NEAR_WM_16 0x03 162 #define ETR_RING_CONFIG_NEAR_WM_32 0x04 163 #define ETR_RING_CONFIG_NEAR_WM_64 0x05 164 #define ETR_RING_CONFIG_NEAR_WM_128 0x06 165 #define ETR_RING_CONFIG_NEAR_WM_256 0x07 166 #define ETR_RING_CONFIG_NEAR_WM_512 0x08 167 #define ETR_RING_CONFIG_NEAR_WM_1K 0x09 168 #define ETR_RING_CONFIG_NEAR_WM_2K 0x0A 169 #define ETR_RING_CONFIG_NEAR_WM_4K 0x0B 170 #define ETR_RING_CONFIG_NEAR_WM_8K 0x0C 171 #define ETR_RING_CONFIG_NEAR_WM_16K 0x0D 172 #define ETR_RING_CONFIG_NEAR_WM_32K 0x0E 173 #define ETR_RING_CONFIG_NEAR_WM_64K 0x0F 174 #define ETR_RING_CONFIG_NEAR_WM_128K 0x10 175 #define ETR_RING_CONFIG_NEAR_WM_256K 0x11 176 #define ETR_RING_CONFIG_NEAR_WM_512K 0x12 177 #define ETR_RING_CONFIG_NEAR_WM_1M 0x13 178 #define ETR_RING_CONFIG_NEAR_WM_2M 0x14 179 #define ETR_RING_CONFIG_NEAR_WM_4M 0x15 180 181 #define ETR_RING_CONFIG_SIZE_64 0x00 182 #define ETR_RING_CONFIG_SIZE_128 0x01 183 #define ETR_RING_CONFIG_SIZE_256 0x02 184 #define ETR_RING_CONFIG_SIZE_512 0x03 185 #define ETR_RING_CONFIG_SIZE_1K 0x04 186 #define ETR_RING_CONFIG_SIZE_2K 0x05 187 #define ETR_RING_CONFIG_SIZE_4K 0x06 188 #define ETR_RING_CONFIG_SIZE_8K 0x07 189 #define ETR_RING_CONFIG_SIZE_16K 0x08 190 #define ETR_RING_CONFIG_SIZE_32K 0x09 191 #define ETR_RING_CONFIG_SIZE_64K 0x0A 192 #define ETR_RING_CONFIG_SIZE_128K 0x0B 193 #define ETR_RING_CONFIG_SIZE_256K 0x0C 194 #define ETR_RING_CONFIG_SIZE_512K 0x0D 195 #define ETR_RING_CONFIG_SIZE_1M 0x0E 196 #define ETR_RING_CONFIG_SIZE_2M 0x0F 197 #define ETR_RING_CONFIG_SIZE_4M 0x10 198 199 /* Default Ring Config is Nearly Full = Full and Nearly Empty = Empty */ 200 #define ETR_RING_CONFIG_BUILD(size) \ 201 (__SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \ 202 ETR_RING_CONFIG_NEAR_FULL_WM) | \ 203 __SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \ 204 ETR_RING_CONFIG_NEAR_EMPTY_WM) | \ 205 __SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE)) 206 207 /* Response Ring Configuration */ 208 #define ETR_RING_CONFIG_BUILD_RESP(size, wm_nf, wm_ne) \ 209 (__SHIFTIN((wm_nf), ETR_RING_CONFIG_NEAR_FULL_WM) | \ 210 __SHIFTIN((wm_ne), ETR_RING_CONFIG_NEAR_EMPTY_WM) | \ 211 __SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE)) 212 213 /* Ring Base */ 214 #define ETR_RING_BASE_BUILD(addr, size) \ 215 (((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) 216 217 #define ETR_INT_REG_CLEAR_MASK 0xffff 218 219 /* Initial bank Interrupt Source mask */ 220 #define ETR_INT_SRCSEL_MASK 0x44444444UL 221 222 #define ETR_INT_SRCSEL_NEXT_OFFSET 4 223 224 #define ETR_RINGS_PER_INT_SRCSEL 8 225 226 #define ETR_INT_COL_CTL_ENABLE __BIT(31) 227 228 #define ETR_AP_NF_MASK_INIT 0xAAAAAAAA 229 #define ETR_AP_NE_MASK_INIT 0x55555555 230 231 /* Autopush destination AE bit */ 232 #define ETR_AP_DEST_ENABLE __BIT(7) 233 #define ETR_AP_DEST_AE __BITS(6, 2) 234 #define ETR_AP_DEST_MAILBOX __BITS(1, 0) 235 236 /* Autopush destination enable bit */ 237 238 /* Autopush CSR Offset */ 239 #define ETR_AP_BANK_OFFSET 4 240 241 /* Autopush maximum rings per bank */ 242 #define ETR_MAX_RINGS_PER_AP_BANK 32 243 244 /* Maximum mailbox per acclerator */ 245 #define ETR_MAX_MAILBOX_PER_ACCELERATOR 4 246 247 /* Maximum AEs per mailbox */ 248 #define ETR_MAX_AE_PER_MAILBOX 4 249 250 /* Macro to get the ring's autopush bank number */ 251 #define ETR_RING_AP_BANK_NUMBER(ring) ((ring) >> 5) 252 253 /* Macro to get the ring's autopush mailbox number */ 254 #define ETR_RING_AP_MAILBOX_NUMBER(ring) \ 255 (ETR_RING_AP_BANK_NUMBER(ring) % ETR_MAX_MAILBOX_PER_ACCELERATOR) 256 257 /* Macro to get the ring number in the autopush bank */ 258 #define ETR_RING_NUMBER_IN_AP_BANK(ring) \ 259 ((ring) % ETR_MAX_RINGS_PER_AP_BANK) 260 261 #define ETR_RING_EMPTY_ENTRY_SIG (0x7F7F7F7F) 262 263 /* -------------------------------------------------------------------------- */ 264 /* CAP_GLOBAL_CTL region */ 265 266 #define FCU_CTRL 0x8c0 267 #define FCU_CTRL_CMD_NOOP 0 268 #define FCU_CTRL_CMD_AUTH 1 269 #define FCU_CTRL_CMD_LOAD 2 270 #define FCU_CTRL_CMD_START 3 271 #define FCU_CTRL_AE __BITS(8, 31) 272 273 #define FCU_STATUS 0x8c4 274 #define FCU_STATUS_STS __BITS(0, 2) 275 #define FCU_STATUS_STS_NO 0 276 #define FCU_STATUS_STS_VERI_DONE 1 277 #define FCU_STATUS_STS_LOAD_DONE 2 278 #define FCU_STATUS_STS_VERI_FAIL 3 279 #define FCU_STATUS_STS_LOAD_FAIL 4 280 #define FCU_STATUS_STS_BUSY 5 281 #define FCU_STATUS_AUTHFWLD __BIT(8) 282 #define FCU_STATUS_DONE __BIT(9) 283 #define FCU_STATUS_LOADED_AE __BITS(22, 31) 284 285 #define FCU_STATUS1 0x8c8 286 287 #define FCU_DRAM_ADDR_LO 0x8cc 288 #define FCU_DRAM_ADDR_HI 0x8d0 289 #define FCU_RAMBASE_ADDR_HI 0x8d4 290 #define FCU_RAMBASE_ADDR_LO 0x8d8 291 292 #define FW_AUTH_WAIT_PERIOD 10 293 #define FW_AUTH_MAX_RETRY 300 294 295 #define CAP_GLOBAL_CTL_BASE 0xa00 296 #define CAP_GLOBAL_CTL_MISC CAP_GLOBAL_CTL_BASE + 0x04 297 #define CAP_GLOBAL_CTL_MISC_TIMESTAMP_EN __BIT(7) 298 #define CAP_GLOBAL_CTL_RESET CAP_GLOBAL_CTL_BASE + 0x0c 299 #define CAP_GLOBAL_CTL_RESET_MASK __BITS(31, 26) 300 #define CAP_GLOBAL_CTL_RESET_ACCEL_MASK __BITS(25, 20) 301 #define CAP_GLOBAL_CTL_RESET_AE_MASK __BITS(19, 0) 302 #define CAP_GLOBAL_CTL_CLK_EN CAP_GLOBAL_CTL_BASE + 0x50 303 #define CAP_GLOBAL_CTL_CLK_EN_ACCEL_MASK __BITS(25, 20) 304 #define CAP_GLOBAL_CTL_CLK_EN_AE_MASK __BITS(19, 0) 305 306 /* -------------------------------------------------------------------------- */ 307 /* AE region */ 308 #define UPC_MASK 0x1ffff 309 #define USTORE_SIZE QAT_16K 310 311 #define AE_LOCAL_AE_MASK __BITS(31, 12) 312 #define AE_LOCAL_CSR_MASK __BITS(9, 0) 313 314 /* AE_LOCAL registers */ 315 /* Control Store Address Register */ 316 #define USTORE_ADDRESS 0x000 317 #define USTORE_ADDRESS_ECS __BIT(31) 318 319 #define USTORE_ECC_BIT_0 44 320 #define USTORE_ECC_BIT_1 45 321 #define USTORE_ECC_BIT_2 46 322 #define USTORE_ECC_BIT_3 47 323 #define USTORE_ECC_BIT_4 48 324 #define USTORE_ECC_BIT_5 49 325 #define USTORE_ECC_BIT_6 50 326 327 /* Control Store Data Lower Register */ 328 #define USTORE_DATA_LOWER 0x004 329 /* Control Store Data Upper Register */ 330 #define USTORE_DATA_UPPER 0x008 331 /* Control Store Error Status Register */ 332 #define USTORE_ERROR_STATUS 0x00c 333 /* Arithmetic Logic Unit Output Register */ 334 #define ALU_OUT 0x010 335 /* Context Arbiter Control Register */ 336 #define CTX_ARB_CNTL 0x014 337 #define CTX_ARB_CNTL_INIT 0x00000000 338 /* Context Enables Register */ 339 #define CTX_ENABLES 0x018 340 #define CTX_ENABLES_INIT 0 341 #define CTX_ENABLES_INUSE_CONTEXTS __BIT(31) 342 #define CTX_ENABLES_CNTL_STORE_PARITY_ERROR __BIT(29) 343 #define CTX_ENABLES_CNTL_STORE_PARITY_ENABLE __BIT(28) 344 #define CTX_ENABLES_BREAKPOINT __BIT(27) 345 #define CTX_ENABLES_PAR_ERR __BIT(25) 346 #define CTX_ENABLES_NN_MODE __BIT(20) 347 #define CTX_ENABLES_NN_RING_EMPTY __BIT(18) 348 #define CTX_ENABLES_LMADDR_1_GLOBAL __BIT(17) 349 #define CTX_ENABLES_LMADDR_0_GLOBAL __BIT(16) 350 #define CTX_ENABLES_ENABLE __BITS(15,8) 351 352 #define CTX_ENABLES_IGNORE_W1C_MASK \ 353 (~(CTX_ENABLES_PAR_ERR | \ 354 CTX_ENABLES_BREAKPOINT | \ 355 CTX_ENABLES_CNTL_STORE_PARITY_ERROR)) 356 357 /* cycles from CTX_ENABLE high to CTX entering executing state */ 358 #define CYCLES_FROM_READY2EXE 8 359 360 /* Condition Code Enable Register */ 361 #define CC_ENABLE 0x01c 362 #define CC_ENABLE_INIT 0x2000 363 364 /* CSR Context Pointer Register */ 365 #define CSR_CTX_POINTER 0x020 366 #define CSR_CTX_POINTER_CONTEXT __BITS(2,0) 367 /* Register Error Status Register */ 368 #define REG_ERROR_STATUS 0x030 369 /* Indirect Context Status Register */ 370 #define CTX_STS_INDIRECT 0x040 371 #define CTX_STS_INDIRECT_UPC_INIT 0x00000000 372 373 /* Active Context Status Register */ 374 #define ACTIVE_CTX_STATUS 0x044 375 #define ACTIVE_CTX_STATUS_ABO __BIT(31) 376 #define ACTIVE_CTX_STATUS_ACNO __BITS(0, 2) 377 /* Indirect Context Signal Events Register */ 378 #define CTX_SIG_EVENTS_INDIRECT 0x048 379 #define CTX_SIG_EVENTS_INDIRECT_INIT 0x00000001 380 /* Active Context Signal Events Register */ 381 #define CTX_SIG_EVENTS_ACTIVE 0x04c 382 /* Indirect Context Wakeup Events Register */ 383 #define CTX_WAKEUP_EVENTS_INDIRECT 0x050 384 #define CTX_WAKEUP_EVENTS_INDIRECT_VOLUNTARY 0x00000001 385 #define CTX_WAKEUP_EVENTS_INDIRECT_SLEEP 0x00010000 386 387 #define CTX_WAKEUP_EVENTS_INDIRECT_INIT 0x00000001 388 389 /* Active Context Wakeup Events Register */ 390 #define CTX_WAKEUP_EVENTS_ACTIVE 0x054 391 /* Indirect Context Future Count Register */ 392 #define CTX_FUTURE_COUNT_INDIRECT 0x058 393 /* Active Context Future Count Register */ 394 #define CTX_FUTURE_COUNT_ACTIVE 0x05c 395 /* Indirect Local Memory Address 0 Register */ 396 #define LM_ADDR_0_INDIRECT 0x060 397 /* Active Local Memory Address 0 Register */ 398 #define LM_ADDR_0_ACTIVE 0x064 399 /* Indirect Local Memory Address 1 Register */ 400 #define LM_ADDR_1_INDIRECT 0x068 401 /* Active Local Memory Address 1 Register */ 402 #define LM_ADDR_1_ACTIVE 0x06c 403 /* Byte Index Register */ 404 #define BYTE_INDEX 0x070 405 /* Indirect Local Memory Address 0 Byte Index Register */ 406 #define INDIRECT_LM_ADDR_0_BYTE_INDEX 0x0e0 407 /* Active Local Memory Address 0 Byte Index Register */ 408 #define ACTIVE_LM_ADDR_0_BYTE_INDEX 0x0e4 409 /* Indirect Local Memory Address 1 Byte Index Register */ 410 #define INDIRECT_LM_ADDR_1_BYTE_INDEX 0x0e8 411 /* Active Local Memory Address 1 Byte Index Register */ 412 #define ACTIVE_LM_ADDR_1_BYTE_INDEX 0x0ec 413 /* Transfer Index Concatenated with Byte Index Register */ 414 #define T_INDEX_BYTE_INDEX 0x0f4 415 /* Transfer Index Register */ 416 #define T_INDEX 0x074 417 /* Indirect Future Count Signal Signal Register */ 418 #define FUTURE_COUNT_SIGNAL_INDIRECT 0x078 419 /* Active Context Future Count Register */ 420 #define FUTURE_COUNT_SIGNAL_ACTIVE 0x07c 421 /* Next Neighbor Put Register */ 422 #define NN_PUT 0x080 423 /* Next Neighbor Get Register */ 424 #define NN_GET 0x084 425 /* Timestamp Low Register */ 426 #define TIMESTAMP_LOW 0x0c0 427 /* Timestamp High Register */ 428 #define TIMESTAMP_HIGH 0x0c4 429 /* Next Neighbor Signal Register */ 430 #define NEXT_NEIGHBOR_SIGNAL 0x100 431 /* Previous Neighbor Signal Register */ 432 #define PREV_NEIGHBOR_SIGNAL 0x104 433 /* Same AccelEngine Signal Register */ 434 #define SAME_AE_SIGNAL 0x108 435 /* Cyclic Redundancy Check Remainder Register */ 436 #define CRC_REMAINDER 0x140 437 /* Profile Count Register */ 438 #define PROFILE_COUNT 0x144 439 /* Pseudorandom Number Register */ 440 #define PSEUDO_RANDOM_NUMBER 0x148 441 /* Signature Enable Register */ 442 #define SIGNATURE_ENABLE 0x150 443 /* Miscellaneous Control Register */ 444 #define AE_MISC_CONTROL 0x160 445 #define AE_MISC_CONTROL_PARITY_ENABLE __BIT(24) 446 #define AE_MISC_CONTROL_FORCE_BAD_PARITY __BIT(23) 447 #define AE_MISC_CONTROL_ONE_CTX_RELOAD __BIT(22) 448 #define AE_MISC_CONTROL_CS_RELOAD __BITS(21, 20) 449 #define AE_MISC_CONTROL_SHARE_CS __BIT(2) 450 /* Control Store Address 1 Register */ 451 #define USTORE_ADDRESS1 0x158 452 /* Local CSR Status Register */ 453 #define LOCAL_CSR_STATUS 0x180 454 #define LOCAL_CSR_STATUS_STATUS 0x1 455 /* NULL Register */ 456 #define NULL_CSR 0x3fc 457 458 /* AE_XFER macros */ 459 #define AE_XFER_AE_MASK __BITS(31, 12) 460 #define AE_XFER_CSR_MASK __BITS(9, 2) 461 462 #define AEREG_BAD_REGADDR 0xffff /* bad register address */ 463 464 /* -------------------------------------------------------------------------- */ 465 466 #define SSMWDT(i) ((i) * 0x4000 + 0x54) 467 #define SSMWDTPKE(i) ((i) * 0x4000 + 0x58) 468 #define INTSTATSSM(i) ((i) * 0x4000 + 0x04) 469 #define INTSTATSSM_SHANGERR __BIT(13) 470 #define PPERR(i) ((i) * 0x4000 + 0x08) 471 #define PPERRID(i) ((i) * 0x4000 + 0x0C) 472 #define CERRSSMSH(i) ((i) * 0x4000 + 0x10) 473 #define UERRSSMSH(i) ((i) * 0x4000 + 0x18) 474 #define UERRSSMSHAD(i) ((i) * 0x4000 + 0x1C) 475 #define SLICEHANGSTATUS(i) ((i) * 0x4000 + 0x4C) 476 #define SLICE_HANG_AUTH0_MASK __BIT(0) 477 #define SLICE_HANG_AUTH1_MASK __BIT(1) 478 #define SLICE_HANG_CPHR0_MASK __BIT(4) 479 #define SLICE_HANG_CPHR1_MASK __BIT(5) 480 #define SLICE_HANG_CMP0_MASK __BIT(8) 481 #define SLICE_HANG_CMP1_MASK __BIT(9) 482 #define SLICE_HANG_XLT0_MASK __BIT(12) 483 #define SLICE_HANG_XLT1_MASK __BIT(13) 484 #define SLICE_HANG_MMP0_MASK __BIT(16) 485 #define SLICE_HANG_MMP1_MASK __BIT(17) 486 #define SLICE_HANG_MMP2_MASK __BIT(18) 487 #define SLICE_HANG_MMP3_MASK __BIT(19) 488 #define SLICE_HANG_MMP4_MASK __BIT(20) 489 490 #define SHINTMASKSSM(i) ((i) * 0x4000 + 0x1018) 491 #define ENABLE_SLICE_HANG 0x000000 492 #define MAX_MMP (5) 493 #define MMP_BASE(i) ((i) * 0x1000 % 0x3800) 494 #define CERRSSMMMP(i, n) ((i) * 0x4000 + MMP_BASE(n) + 0x380) 495 #define UERRSSMMMP(i, n) ((i) * 0x4000 + MMP_BASE(n) + 0x388) 496 #define UERRSSMMMPAD(i, n) ((i) * 0x4000 + MMP_BASE(n) + 0x38C) 497 498 #define CPP_CFC_ERR_STATUS (0x30000 + 0xC04) 499 #define CPP_CFC_ERR_PPID (0x30000 + 0xC08) 500 501 #define ERRSOU0 (0x3A000 + 0x00) 502 #define ERRSOU1 (0x3A000 + 0x04) 503 #define ERRSOU2 (0x3A000 + 0x08) 504 #define ERRSOU3 (0x3A000 + 0x0C) 505 #define ERRSOU4 (0x3A000 + 0xD0) 506 #define ERRSOU5 (0x3A000 + 0xD8) 507 #define ERRMSK0 (0x3A000 + 0x10) 508 #define ERRMSK1 (0x3A000 + 0x14) 509 #define ERRMSK2 (0x3A000 + 0x18) 510 #define ERRMSK3 (0x3A000 + 0x1C) 511 #define ERRMSK4 (0x3A000 + 0xD4) 512 #define ERRMSK5 (0x3A000 + 0xDC) 513 #define EMSK3_CPM0_MASK __BIT(2) 514 #define EMSK3_CPM1_MASK __BIT(3) 515 #define EMSK5_CPM2_MASK __BIT(16) 516 #define EMSK5_CPM3_MASK __BIT(17) 517 #define EMSK5_CPM4_MASK __BIT(18) 518 #define RICPPINTSTS (0x3A000 + 0x114) 519 #define RIERRPUSHID (0x3A000 + 0x118) 520 #define RIERRPULLID (0x3A000 + 0x11C) 521 522 #define TICPPINTSTS (0x3A400 + 0x13C) 523 #define TIERRPUSHID (0x3A400 + 0x140) 524 #define TIERRPULLID (0x3A400 + 0x144) 525 #define SECRAMUERR (0x3AC00 + 0x04) 526 #define SECRAMUERRAD (0x3AC00 + 0x0C) 527 #define CPPMEMTGTERR (0x3AC00 + 0x10) 528 #define ERRPPID (0x3AC00 + 0x14) 529 530 #define ADMINMSGUR 0x3a574 531 #define ADMINMSGLR 0x3a578 532 #define MAILBOX_BASE 0x20970 533 #define MAILBOX_STRIDE 0x1000 534 #define ADMINMSG_LEN 32 535 536 /* -------------------------------------------------------------------------- */ 537 static const uint8_t mailbox_const_tab[1024] __aligned(1024) = { 538 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 539 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 540 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 541 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 542 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 543 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 544 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 545 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 546 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 547 0x00, 0x00, 0x00, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 548 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 549 0x00, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 550 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 551 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 552 0x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 553 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 554 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 562 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 563 0x54, 0x32, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 564 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab, 565 0x89, 0x98, 0xba, 0xdc, 0xfe, 0x10, 0x32, 0x54, 0x76, 0xc3, 0xd2, 0xe1, 0xf0, 566 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 567 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 568 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x05, 0x9e, 569 0xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd, 0x17, 0xf7, 0x0e, 0x59, 0x39, 570 0xff, 0xc0, 0x0b, 0x31, 0x68, 0x58, 0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 571 0xfa, 0x4f, 0xa4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 572 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0x09, 0xe6, 0x67, 0xbb, 0x67, 0xae, 573 0x85, 0x3c, 0x6e, 0xf3, 0x72, 0xa5, 0x4f, 0xf5, 0x3a, 0x51, 0x0e, 0x52, 0x7f, 574 0x9b, 0x05, 0x68, 0x8c, 0x1f, 0x83, 0xd9, 0xab, 0x5b, 0xe0, 0xcd, 0x19, 0x05, 575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 576 0x00, 0x00, 0xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8, 0x62, 0x9a, 0x29, 577 0x2a, 0x36, 0x7c, 0xd5, 0x07, 0x91, 0x59, 0x01, 0x5a, 0x30, 0x70, 0xdd, 0x17, 578 0x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39, 0x67, 0x33, 0x26, 0x67, 0xff, 579 0xc0, 0x0b, 0x31, 0x8e, 0xb4, 0x4a, 0x87, 0x68, 0x58, 0x15, 0x11, 0xdb, 0x0c, 580 0x2e, 0x0d, 0x64, 0xf9, 0x8f, 0xa7, 0x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 581 0xa4, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 582 0x00, 0x00, 0x00, 0x00, 0x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08, 0xbb, 583 0x67, 0xae, 0x85, 0x84, 0xca, 0xa7, 0x3b, 0x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94, 584 0xf8, 0x2b, 0xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1, 0x51, 0x0e, 0x52, 585 0x7f, 0xad, 0xe6, 0x82, 0xd1, 0x9b, 0x05, 0x68, 0x8c, 0x2b, 0x3e, 0x6c, 0x1f, 586 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd, 0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 587 0x7e, 0x21, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 588 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 589 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 590 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 591 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 592 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 593 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 594 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 596 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 597 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 598 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 599 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 600 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 601 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 602 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 603 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 604 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 606 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 607 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 608 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 609 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 611 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 612 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 613 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 614 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 617 618 /* -------------------------------------------------------------------------- */ 619 /* Microcode */ 620 621 /* Clear GPR of AE */ 622 static const uint64_t ae_clear_gprs_inst[] = { 623 0x0F0000C0000ull, /* .0 l0000!val = 0 ; immed[l0000!val, 0x0] */ 624 0x0F000000380ull, /* .1 l0000!count = 128 ; immed[l0000!count, 0x80] */ 625 0x0D805000011ull, /* .2 br!=ctx[0, ctx_init#] */ 626 0x0FC082C0300ull, /* .3 local_csr_wr[nn_put, 0] */ 627 0x0F0000C0300ull, /* .4 nop */ 628 0x0F0000C0300ull, /* .5 nop */ 629 0x0F0000C0300ull, /* .6 nop */ 630 0x0F0000C0300ull, /* .7 nop */ 631 0x0A0643C0000ull, /* .8 init_nn#:alu[*n$index++, --, b, l0000!val] */ 632 0x0BAC0000301ull, /* .9 alu[l0000!count, l0000!count, -, 1] */ 633 0x0D802000101ull, /* .10 bne[init_nn#] */ 634 0x0F0000C0001ull, /* .11 l0000!indx = 0 ; immed[l0000!indx, 0x0] */ 635 0x0FC066C0001ull, /* .12 local_csr_wr[active_lm_addr_0, l0000!indx]; 636 * put indx to lm_addr */ 637 0x0F0000C0300ull, /* .13 nop */ 638 0x0F0000C0300ull, /* .14 nop */ 639 0x0F0000C0300ull, /* .15 nop */ 640 0x0F000400300ull, /* .16 l0000!count = 1024 ; immed[l0000!count, 0x400] */ 641 0x0A0610C0000ull, /* .17 init_lm#:alu[*l$index0++, --, b, l0000!val] */ 642 0x0BAC0000301ull, /* .18 alu[l0000!count, l0000!count, -, 1] */ 643 0x0D804400101ull, /* .19 bne[init_lm#] */ 644 0x0A0580C0000ull, /* .20 ctx_init#:alu[$l0000!xfers[0], --, b, l0000!val] */ 645 0x0A0581C0000ull, /* .21 alu[$l0000!xfers[1], --, b, l0000!val] */ 646 0x0A0582C0000ull, /* .22 alu[$l0000!xfers[2], --, b, l0000!val] */ 647 0x0A0583C0000ull, /* .23 alu[$l0000!xfers[3], --, b, l0000!val] */ 648 0x0A0584C0000ull, /* .24 alu[$l0000!xfers[4], --, b, l0000!val] */ 649 0x0A0585C0000ull, /* .25 alu[$l0000!xfers[5], --, b, l0000!val] */ 650 0x0A0586C0000ull, /* .26 alu[$l0000!xfers[6], --, b, l0000!val] */ 651 0x0A0587C0000ull, /* .27 alu[$l0000!xfers[7], --, b, l0000!val] */ 652 0x0A0588C0000ull, /* .28 alu[$l0000!xfers[8], --, b, l0000!val] */ 653 0x0A0589C0000ull, /* .29 alu[$l0000!xfers[9], --, b, l0000!val] */ 654 0x0A058AC0000ull, /* .30 alu[$l0000!xfers[10], --, b, l0000!val] */ 655 0x0A058BC0000ull, /* .31 alu[$l0000!xfers[11], --, b, l0000!val] */ 656 0x0A058CC0000ull, /* .32 alu[$l0000!xfers[12], --, b, l0000!val] */ 657 0x0A058DC0000ull, /* .33 alu[$l0000!xfers[13], --, b, l0000!val] */ 658 0x0A058EC0000ull, /* .34 alu[$l0000!xfers[14], --, b, l0000!val] */ 659 0x0A058FC0000ull, /* .35 alu[$l0000!xfers[15], --, b, l0000!val] */ 660 0x0A05C0C0000ull, /* .36 alu[$l0000!xfers[16], --, b, l0000!val] */ 661 0x0A05C1C0000ull, /* .37 alu[$l0000!xfers[17], --, b, l0000!val] */ 662 0x0A05C2C0000ull, /* .38 alu[$l0000!xfers[18], --, b, l0000!val] */ 663 0x0A05C3C0000ull, /* .39 alu[$l0000!xfers[19], --, b, l0000!val] */ 664 0x0A05C4C0000ull, /* .40 alu[$l0000!xfers[20], --, b, l0000!val] */ 665 0x0A05C5C0000ull, /* .41 alu[$l0000!xfers[21], --, b, l0000!val] */ 666 0x0A05C6C0000ull, /* .42 alu[$l0000!xfers[22], --, b, l0000!val] */ 667 0x0A05C7C0000ull, /* .43 alu[$l0000!xfers[23], --, b, l0000!val] */ 668 0x0A05C8C0000ull, /* .44 alu[$l0000!xfers[24], --, b, l0000!val] */ 669 0x0A05C9C0000ull, /* .45 alu[$l0000!xfers[25], --, b, l0000!val] */ 670 0x0A05CAC0000ull, /* .46 alu[$l0000!xfers[26], --, b, l0000!val] */ 671 0x0A05CBC0000ull, /* .47 alu[$l0000!xfers[27], --, b, l0000!val] */ 672 0x0A05CCC0000ull, /* .48 alu[$l0000!xfers[28], --, b, l0000!val] */ 673 0x0A05CDC0000ull, /* .49 alu[$l0000!xfers[29], --, b, l0000!val] */ 674 0x0A05CEC0000ull, /* .50 alu[$l0000!xfers[30], --, b, l0000!val] */ 675 0x0A05CFC0000ull, /* .51 alu[$l0000!xfers[31], --, b, l0000!val] */ 676 0x0A0400C0000ull, /* .52 alu[l0000!gprega[0], --, b, l0000!val] */ 677 0x0B0400C0000ull, /* .53 alu[l0000!gpregb[0], --, b, l0000!val] */ 678 0x0A0401C0000ull, /* .54 alu[l0000!gprega[1], --, b, l0000!val] */ 679 0x0B0401C0000ull, /* .55 alu[l0000!gpregb[1], --, b, l0000!val] */ 680 0x0A0402C0000ull, /* .56 alu[l0000!gprega[2], --, b, l0000!val] */ 681 0x0B0402C0000ull, /* .57 alu[l0000!gpregb[2], --, b, l0000!val] */ 682 0x0A0403C0000ull, /* .58 alu[l0000!gprega[3], --, b, l0000!val] */ 683 0x0B0403C0000ull, /* .59 alu[l0000!gpregb[3], --, b, l0000!val] */ 684 0x0A0404C0000ull, /* .60 alu[l0000!gprega[4], --, b, l0000!val] */ 685 0x0B0404C0000ull, /* .61 alu[l0000!gpregb[4], --, b, l0000!val] */ 686 0x0A0405C0000ull, /* .62 alu[l0000!gprega[5], --, b, l0000!val] */ 687 0x0B0405C0000ull, /* .63 alu[l0000!gpregb[5], --, b, l0000!val] */ 688 0x0A0406C0000ull, /* .64 alu[l0000!gprega[6], --, b, l0000!val] */ 689 0x0B0406C0000ull, /* .65 alu[l0000!gpregb[6], --, b, l0000!val] */ 690 0x0A0407C0000ull, /* .66 alu[l0000!gprega[7], --, b, l0000!val] */ 691 0x0B0407C0000ull, /* .67 alu[l0000!gpregb[7], --, b, l0000!val] */ 692 0x0A0408C0000ull, /* .68 alu[l0000!gprega[8], --, b, l0000!val] */ 693 0x0B0408C0000ull, /* .69 alu[l0000!gpregb[8], --, b, l0000!val] */ 694 0x0A0409C0000ull, /* .70 alu[l0000!gprega[9], --, b, l0000!val] */ 695 0x0B0409C0000ull, /* .71 alu[l0000!gpregb[9], --, b, l0000!val] */ 696 0x0A040AC0000ull, /* .72 alu[l0000!gprega[10], --, b, l0000!val] */ 697 0x0B040AC0000ull, /* .73 alu[l0000!gpregb[10], --, b, l0000!val] */ 698 0x0A040BC0000ull, /* .74 alu[l0000!gprega[11], --, b, l0000!val] */ 699 0x0B040BC0000ull, /* .75 alu[l0000!gpregb[11], --, b, l0000!val] */ 700 0x0A040CC0000ull, /* .76 alu[l0000!gprega[12], --, b, l0000!val] */ 701 0x0B040CC0000ull, /* .77 alu[l0000!gpregb[12], --, b, l0000!val] */ 702 0x0A040DC0000ull, /* .78 alu[l0000!gprega[13], --, b, l0000!val] */ 703 0x0B040DC0000ull, /* .79 alu[l0000!gpregb[13], --, b, l0000!val] */ 704 0x0A040EC0000ull, /* .80 alu[l0000!gprega[14], --, b, l0000!val] */ 705 0x0B040EC0000ull, /* .81 alu[l0000!gpregb[14], --, b, l0000!val] */ 706 0x0A040FC0000ull, /* .82 alu[l0000!gprega[15], --, b, l0000!val] */ 707 0x0B040FC0000ull, /* .83 alu[l0000!gpregb[15], --, b, l0000!val] */ 708 0x0D81581C010ull, /* .84 br=ctx[7, exit#] */ 709 0x0E000010000ull, /* .85 ctx_arb[kill], any */ 710 0x0E000010000ull, /* .86 exit#:ctx_arb[kill], any */ 711 }; 712 713 static const uint64_t ae_inst_4b[] = { 714 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 715 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 716 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 717 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 718 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 719 l0000!indx]; put indx to lm_addr */ 720 0x0F0000C0300ull, /* .5 nop */ 721 0x0F0000C0300ull, /* .6 nop */ 722 0x0F0000C0300ull, /* .7 nop */ 723 0x0A021000000ull, /* .8 alu[*l$index0++, --, b, l0000!myvalue] */ 724 }; 725 726 static const uint64_t ae_inst_1b[] = { 727 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 728 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 729 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 730 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 731 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 732 l0000!indx]; put indx to lm_addr */ 733 0x0F0000C0300ull, /* .5 nop */ 734 0x0F0000C0300ull, /* .6 nop */ 735 0x0F0000C0300ull, /* .7 nop */ 736 0x0A000180000ull, /* .8 alu[l0000!val, --, b, *l$index0] */ 737 0x09080000200ull, /* .9 alu_shf[l0000!myvalue, --, b, 738 l0000!myvalue, <<24 ] */ 739 0x08180280201ull, /* .10 alu_shf[l0000!val1, --, b, l0000!val, <<8 ] */ 740 0x08080280102ull, /* .11 alu_shf[l0000!val1, --, b, l0000!val1 , >>8 ] */ 741 0x0BA00100002ull, /* .12 alu[l0000!val2, l0000!val1, or, l0000!myvalue] */ 742 743 }; 744 745 static const uint64_t ae_inst_2b[] = { 746 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 747 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 748 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 749 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 750 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 751 l0000!indx]; put indx to lm_addr */ 752 0x0F0000C0300ull, /* .5 nop */ 753 0x0F0000C0300ull, /* .6 nop */ 754 0x0F0000C0300ull, /* .7 nop */ 755 0x0A000180000ull, /* .8 alu[l0000!val, --, b, *l$index0] */ 756 0x09100000200ull, /* .9 alu_shf[l0000!myvalue, --, b, 757 l0000!myvalue, <<16 ] */ 758 0x08100280201ull, /* .10 alu_shf[l0000!val1, --, b, l0000!val, <<16 ] */ 759 0x08100280102ull, /* .11 alu_shf[l0000!val1, --, b, l0000!val1 , >>16 ] */ 760 0x0BA00100002ull, /* .12 alu[l0000!val2, l0000!val1, or, l0000!myvalue] */ 761 }; 762 763 static const uint64_t ae_inst_3b[] = { 764 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 765 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 766 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 767 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 768 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 769 l0000!indx]; put indx to lm_addr */ 770 0x0F0000C0300ull, /* .5 nop */ 771 0x0F0000C0300ull, /* .6 nop */ 772 0x0F0000C0300ull, /* .7 nop */ 773 0x0A000180000ull, /* .8 alu[l0000!val, --, b, *l$index0] */ 774 0x09180000200ull, /* .9 alu_shf[l0000!myvalue, --, 775 b, l0000!myvalue, <<8 ] */ 776 0x08080280201ull, /* .10 alu_shf[l0000!val1, --, b, l0000!val, <<24 ] */ 777 0x08180280102ull, /* .11 alu_shf[l0000!val1, --, b, l0000!val1 , >>24 ] */ 778 0x0BA00100002ull, /* .12 alu[l0000!val2, l0000!val1, or, l0000!myvalue] */ 779 }; 780 781 /* micro-instr fixup */ 782 #define INSERT_IMMED_GPRA_CONST(inst, const_val) \ 783 inst = (inst & 0xFFFF00C03FFull) | \ 784 ((((const_val) << 12) & 0x0FF00000ull) | \ 785 (((const_val) << 10) & 0x0003FC00ull)) 786 #define INSERT_IMMED_GPRB_CONST(inst, const_val) \ 787 inst = (inst & 0xFFFF00FFF00ull) | \ 788 ((((const_val) << 12) & 0x0FF00000ull) | \ 789 (((const_val) << 0) & 0x000000FFull)) 790 791 enum aereg_type { 792 AEREG_NO_DEST, /* no destination */ 793 AEREG_GPA_REL, /* general-purpose A register under relative mode */ 794 AEREG_GPA_ABS, /* general-purpose A register under absolute mode */ 795 AEREG_GPB_REL, /* general-purpose B register under relative mode */ 796 AEREG_GPB_ABS, /* general-purpose B register under absolute mode */ 797 AEREG_SR_REL, /* sram register under relative mode */ 798 AEREG_SR_RD_REL, /* sram read register under relative mode */ 799 AEREG_SR_WR_REL, /* sram write register under relative mode */ 800 AEREG_SR_ABS, /* sram register under absolute mode */ 801 AEREG_SR_RD_ABS, /* sram read register under absolute mode */ 802 AEREG_SR_WR_ABS, /* sram write register under absolute mode */ 803 AEREG_SR0_SPILL, /* sram0 spill register */ 804 AEREG_SR1_SPILL, /* sram1 spill register */ 805 AEREG_SR2_SPILL, /* sram2 spill register */ 806 AEREG_SR3_SPILL, /* sram3 spill register */ 807 AEREG_SR0_MEM_ADDR, /* sram0 memory address register */ 808 AEREG_SR1_MEM_ADDR, /* sram1 memory address register */ 809 AEREG_SR2_MEM_ADDR, /* sram2 memory address register */ 810 AEREG_SR3_MEM_ADDR, /* sram3 memory address register */ 811 AEREG_DR_REL, /* dram register under relative mode */ 812 AEREG_DR_RD_REL, /* dram read register under relative mode */ 813 AEREG_DR_WR_REL, /* dram write register under relative mode */ 814 AEREG_DR_ABS, /* dram register under absolute mode */ 815 AEREG_DR_RD_ABS, /* dram read register under absolute mode */ 816 AEREG_DR_WR_ABS, /* dram write register under absolute mode */ 817 AEREG_DR_MEM_ADDR, /* dram memory address register */ 818 AEREG_LMEM, /* local memory */ 819 AEREG_LMEM0, /* local memory bank0 */ 820 AEREG_LMEM1, /* local memory bank1 */ 821 AEREG_LMEM_SPILL, /* local memory spill */ 822 AEREG_LMEM_ADDR, /* local memory address */ 823 AEREG_NEIGH_REL, /* next neighbour register under relative mode */ 824 AEREG_NEIGH_INDX, /* next neighbour register under index mode */ 825 AEREG_SIG_REL, /* signal register under relative mode */ 826 AEREG_SIG_INDX, /* signal register under index mode */ 827 AEREG_SIG_DOUBLE, /* signal register */ 828 AEREG_SIG_SINGLE, /* signal register */ 829 AEREG_SCRATCH_MEM_ADDR, /* scratch memory address */ 830 AEREG_UMEM0, /* ustore memory bank0 */ 831 AEREG_UMEM1, /* ustore memory bank1 */ 832 AEREG_UMEM_SPILL, /* ustore memory spill */ 833 AEREG_UMEM_ADDR, /* ustore memory address */ 834 AEREG_DR1_MEM_ADDR, /* dram segment1 address */ 835 AEREG_SR0_IMPORTED, /* sram segment0 imported data */ 836 AEREG_SR1_IMPORTED, /* sram segment1 imported data */ 837 AEREG_SR2_IMPORTED, /* sram segment2 imported data */ 838 AEREG_SR3_IMPORTED, /* sram segment3 imported data */ 839 AEREG_DR_IMPORTED, /* dram segment0 imported data */ 840 AEREG_DR1_IMPORTED, /* dram segment1 imported data */ 841 AEREG_SCRATCH_IMPORTED, /* scratch imported data */ 842 AEREG_XFER_RD_ABS, /* transfer read register under absolute mode */ 843 AEREG_XFER_WR_ABS, /* transfer write register under absolute mode */ 844 AEREG_CONST_VALUE, /* const alue */ 845 AEREG_ADDR_TAKEN, /* address taken */ 846 AEREG_OPTIMIZED_AWAY, /* optimized away */ 847 AEREG_SHRAM_ADDR, /* shared ram0 address */ 848 AEREG_SHRAM1_ADDR, /* shared ram1 address */ 849 AEREG_SHRAM2_ADDR, /* shared ram2 address */ 850 AEREG_SHRAM3_ADDR, /* shared ram3 address */ 851 AEREG_SHRAM4_ADDR, /* shared ram4 address */ 852 AEREG_SHRAM5_ADDR, /* shared ram5 address */ 853 AEREG_ANY = 0xffff /* any register */ 854 }; 855 #define AEREG_SR_INDX AEREG_SR_ABS 856 /* sram transfer register under index mode */ 857 #define AEREG_DR_INDX AEREG_DR_ABS 858 /* dram transfer register under index mode */ 859 #define AEREG_NEIGH_ABS AEREG_NEIGH_INDX 860 /* next neighbor register under absolute mode */ 861 862 863 #define QAT_2K 0x0800 864 #define QAT_4K 0x1000 865 #define QAT_6K 0x1800 866 #define QAT_8K 0x2000 867 #define QAT_16K 0x4000 868 869 #define MOF_OBJ_ID_LEN 8 870 #define MOF_FID 0x00666f6d 871 #define MOF_MIN_VER 0x1 872 #define MOF_MAJ_VER 0x0 873 #define SYM_OBJS "SYM_OBJS" /* symbol object string */ 874 #define UOF_OBJS "UOF_OBJS" /* uof object string */ 875 #define SUOF_OBJS "SUF_OBJS" /* suof object string */ 876 #define SUOF_IMAG "SUF_IMAG" /* suof chunk ID string */ 877 878 #define UOF_STRT "UOF_STRT" /* string table section ID */ 879 #define UOF_GTID "UOF_GTID" /* GTID section ID */ 880 #define UOF_IMAG "UOF_IMAG" /* image section ID */ 881 #define UOF_IMEM "UOF_IMEM" /* import section ID */ 882 #define UOF_MSEG "UOF_MSEG" /* memory section ID */ 883 884 #define CRC_POLY 0x1021 885 #define CRC_WIDTH 16 886 #define CRC_BITMASK(x) (1L << (x)) 887 #define CRC_WIDTHMASK(width) ((((1L<<(width-1))-1L)<<1)|1L) 888 889 struct mof_file_hdr { 890 u_int mfh_fid; 891 u_int mfh_csum; 892 char mfh_min_ver; 893 char mfh_maj_ver; 894 u_short mfh_reserved; 895 u_short mfh_max_chunks; 896 u_short mfh_num_chunks; 897 }; 898 899 struct mof_file_chunk_hdr { 900 char mfch_id[MOF_OBJ_ID_LEN]; 901 uint64_t mfch_offset; 902 uint64_t mfch_size; 903 }; 904 905 struct mof_uof_hdr { 906 u_short muh_max_chunks; 907 u_short muh_num_chunks; 908 u_int muh_reserved; 909 }; 910 911 struct mof_uof_chunk_hdr { 912 char much_id[MOF_OBJ_ID_LEN]; /* should be UOF_IMAG */ 913 uint64_t much_offset; /* uof image */ 914 uint64_t much_size; /* uof image size */ 915 u_int much_name; /* uof name string-table offset */ 916 u_int much_reserved; 917 }; 918 919 #define UOF_MAX_NUM_OF_AE 16 /* maximum number of AE */ 920 921 #define UOF_OBJ_ID_LEN 8 /* length of object ID */ 922 #define UOF_FIELD_POS_SIZE 12 /* field position size */ 923 #define MIN_UOF_SIZE 24 /* minimum .uof file size */ 924 #define UOF_FID 0xc6c2 /* uof magic number */ 925 #define UOF_MIN_VER 0x11 926 #define UOF_MAJ_VER 0x4 927 928 struct uof_file_hdr { 929 u_short ufh_id; /* file id and endian indicator */ 930 u_short ufh_reserved1; /* reserved for future use */ 931 char ufh_min_ver; /* file format minor version */ 932 char ufh_maj_ver; /* file format major version */ 933 u_short ufh_reserved2; /* reserved for future use */ 934 u_short ufh_max_chunks; /* max chunks in file */ 935 u_short ufh_num_chunks; /* num of actual chunks */ 936 }; 937 938 struct uof_file_chunk_hdr { 939 char ufch_id[UOF_OBJ_ID_LEN]; /* chunk identifier */ 940 u_int ufch_csum; /* chunk checksum */ 941 u_int ufch_offset; /* offset of the chunk in the file */ 942 u_int ufch_size; /* size of the chunk */ 943 }; 944 945 struct uof_obj_hdr { 946 u_int uoh_cpu_type; /* CPU type */ 947 u_short uoh_min_cpu_ver; /* starting CPU version */ 948 u_short uoh_max_cpu_ver; /* ending CPU version */ 949 short uoh_max_chunks; /* max chunks in chunk obj */ 950 short uoh_num_chunks; /* num of actual chunks */ 951 u_int uoh_reserved1; 952 u_int uoh_reserved2; 953 }; 954 955 struct uof_chunk_hdr { 956 char uch_id[UOF_OBJ_ID_LEN]; 957 u_int uch_offset; 958 u_int uch_size; 959 }; 960 961 struct uof_str_tab { 962 u_int ust_table_len; /* length of table */ 963 u_int ust_reserved; /* reserved for future use */ 964 uint64_t ust_strings; /* pointer to string table. 965 * NULL terminated strings */ 966 }; 967 968 #define AE_MODE_RELOAD_CTX_SHARED __BIT(12) 969 #define AE_MODE_SHARED_USTORE __BIT(11) 970 #define AE_MODE_LMEM1 __BIT(9) 971 #define AE_MODE_LMEM0 __BIT(8) 972 #define AE_MODE_NN_MODE __BITS(7, 4) 973 #define AE_MODE_CTX_MODE __BITS(3, 0) 974 975 #define AE_MODE_NN_MODE_NEIGH 0 976 #define AE_MODE_NN_MODE_SELF 1 977 #define AE_MODE_NN_MODE_DONTCARE 0xff 978 979 struct uof_image { 980 u_int ui_name; /* image name */ 981 u_int ui_ae_assigned; /* AccelEngines assigned */ 982 u_int ui_ctx_assigned; /* AccelEngine contexts assigned */ 983 u_int ui_cpu_type; /* cpu type */ 984 u_int ui_entry_address; /* entry uaddress */ 985 u_int ui_fill_pattern[2]; /* uword fill value */ 986 u_int ui_reloadable_size; /* size of reloadable ustore section */ 987 988 u_char ui_sensitivity; /* 989 * case sensitivity: 0 = insensitive, 990 * 1 = sensitive 991 */ 992 u_char ui_reserved; /* reserved for future use */ 993 u_short ui_ae_mode; /* 994 * unused<15:14>, legacyMode<13>, 995 * reloadCtxShared<12>, sharedUstore<11>, 996 * ecc<10>, locMem1<9>, locMem0<8>, 997 * nnMode<7:4>, ctx<3:0> 998 */ 999 1000 u_short ui_max_ver; /* max cpu ver on which the image can run */ 1001 u_short ui_min_ver; /* min cpu ver on which the image can run */ 1002 1003 u_short ui_image_attrib; /* image attributes */ 1004 u_short ui_reserved2; /* reserved for future use */ 1005 1006 u_short ui_num_page_regions; /* number of page regions */ 1007 u_short ui_num_pages; /* number of pages */ 1008 1009 u_int ui_reg_tab; /* offset to register table */ 1010 u_int ui_init_reg_sym_tab; /* reg/sym init table */ 1011 u_int ui_sbreak_tab; /* offset to sbreak table */ 1012 1013 u_int ui_app_metadata; /* application meta-data */ 1014 /* ui_npages of code page follows this header */ 1015 }; 1016 1017 struct uof_obj_table { 1018 u_int uot_nentries; /* number of table entries */ 1019 /* uot_nentries of object follows */ 1020 }; 1021 1022 struct uof_ae_reg { 1023 u_int uar_name; /* reg name string-table offset */ 1024 u_int uar_vis_name; /* reg visible name string-table offset */ 1025 u_short uar_type; /* reg type */ 1026 u_short uar_addr; /* reg address */ 1027 u_short uar_access_mode; /* uof_RegAccessMode_T: read/write/both/undef */ 1028 u_char uar_visible; /* register visibility */ 1029 u_char uar_reserved1; /* reserved for future use */ 1030 u_short uar_ref_count; /* number of contiguous registers allocated */ 1031 u_short uar_reserved2; /* reserved for future use */ 1032 u_int uar_xoid; /* xfer order ID */ 1033 }; 1034 1035 enum uof_value_kind { 1036 UNDEF_VAL, /* undefined value */ 1037 CHAR_VAL, /* character value */ 1038 SHORT_VAL, /* short value */ 1039 INT_VAL, /* integer value */ 1040 STR_VAL, /* string value */ 1041 STRTAB_VAL, /* string table value */ 1042 NUM_VAL, /* number value */ 1043 EXPR_VAL /* expression value */ 1044 }; 1045 1046 enum uof_init_type { 1047 INIT_EXPR, 1048 INIT_REG, 1049 INIT_REG_CTX, 1050 INIT_EXPR_ENDIAN_SWAP 1051 }; 1052 1053 struct uof_init_reg_sym { 1054 u_int uirs_name; /* symbol name */ 1055 char uirs_init_type; /* 0=expr, 1=register, 2=ctxReg, 1056 * 3=expr_endian_swap */ 1057 char uirs_value_type; /* EXPR_VAL, STRTAB_VAL */ 1058 char uirs_reg_type; /* register type: ae_reg_type */ 1059 u_char uirs_ctx; /* AE context when initType=2 */ 1060 u_int uirs_addr_offset; /* reg address, or sym-value offset */ 1061 u_int uirs_value; /* integer value, or expression */ 1062 }; 1063 1064 struct uof_sbreak { 1065 u_int us_page_num; /* page number */ 1066 u_int us_virt_uaddr; /* virt uaddress */ 1067 u_char us_sbreak_type; /* sbreak type */ 1068 u_char us_reg_type; /* register type: ae_reg_type */ 1069 u_short us_reserved1; /* reserved for future use */ 1070 u_int us_addr_offset; /* branch target address or offset 1071 * to be used with the reg value to 1072 * calculate the target address */ 1073 u_int us_reg_rddr; /* register address */ 1074 }; 1075 struct uof_code_page { 1076 u_int ucp_page_region; /* page associated region */ 1077 u_int ucp_page_num; /* code-page number */ 1078 u_char ucp_def_page; /* default page indicator */ 1079 u_char ucp_reserved2; /* reserved for future use */ 1080 u_short ucp_reserved1; /* reserved for future use */ 1081 u_int ucp_beg_vaddr; /* starting virtual uaddr */ 1082 u_int ucp_beg_paddr; /* starting physical uaddr */ 1083 u_int ucp_neigh_reg_tab; /* offset to neighbour-reg table */ 1084 u_int ucp_uc_var_tab; /* offset to uC var table */ 1085 u_int ucp_imp_var_tab; /* offset to import var table */ 1086 u_int ucp_imp_expr_tab; /* offset to import expression table */ 1087 u_int ucp_code_area; /* offset to code area */ 1088 }; 1089 1090 struct uof_code_area { 1091 u_int uca_num_micro_words; /* number of micro words */ 1092 u_int uca_uword_block_tab; /* offset to ublock table */ 1093 }; 1094 1095 struct uof_uword_block { 1096 u_int uub_start_addr; /* start address */ 1097 u_int uub_num_words; /* number of microwords */ 1098 u_int uub_uword_offset; /* offset to the uwords */ 1099 u_int uub_reserved; /* reserved for future use */ 1100 }; 1101 1102 struct uof_uword_fixup { 1103 u_int uuf_name; /* offset to string table */ 1104 u_int uuf_uword_address; /* micro word address */ 1105 u_int uuf_expr_value; /* string table offset of expr string, or value */ 1106 u_char uuf_val_type; /* VALUE_UNDEF, VALUE_NUM, VALUE_EXPR */ 1107 u_char uuf_value_attrs; /* bit<0> (Scope: 0=global, 1=local), 1108 * bit<1> (init: 0=no, 1=yes) */ 1109 u_short uuf_reserved1; /* reserved for future use */ 1110 char uuf_field_attrs[UOF_FIELD_POS_SIZE]; 1111 /* field pos, size, and right shift value */ 1112 }; 1113 1114 struct uof_import_var { 1115 u_int uiv_name; /* import var name string-table offset */ 1116 u_char uiv_value_attrs; /* bit<0> (Scope: 0=global), 1117 * bit<1> (init: 0=no, 1=yes) */ 1118 u_char uiv_reserved1; /* reserved for future use */ 1119 u_short uiv_reserved2; /* reserved for future use */ 1120 uint64_t uiv_value; /* 64-bit imported value */ 1121 }; 1122 1123 struct uof_mem_val_attr { 1124 u_int umva_byte_offset; /* byte-offset from the allocated memory */ 1125 u_int umva_value; /* memory value */ 1126 }; 1127 1128 enum uof_mem_region { 1129 SRAM_REGION, /* SRAM region */ 1130 DRAM_REGION, /* DRAM0 region */ 1131 DRAM1_REGION, /* DRAM1 region */ 1132 LMEM_REGION, /* local memory region */ 1133 SCRATCH_REGION, /* SCRATCH region */ 1134 UMEM_REGION, /* micro-store region */ 1135 RAM_REGION, /* RAM region */ 1136 SHRAM_REGION, /* shared memory-0 region */ 1137 SHRAM1_REGION, /* shared memory-1 region */ 1138 SHRAM2_REGION, /* shared memory-2 region */ 1139 SHRAM3_REGION, /* shared memory-3 region */ 1140 SHRAM4_REGION, /* shared memory-4 region */ 1141 SHRAM5_REGION /* shared memory-5 region */ 1142 }; 1143 1144 #define UOF_SCOPE_GLOBAL 0 1145 #define UOF_SCOPE_LOCAL 1 1146 1147 struct uof_init_mem { 1148 u_int uim_sym_name; /* symbol name */ 1149 char uim_region; /* memory region -- uof_mem_region */ 1150 char uim_scope; /* visibility scope */ 1151 u_short uim_reserved1; /* reserved for future use */ 1152 u_int uim_addr; /* memory address */ 1153 u_int uim_num_bytes; /* number of bytes */ 1154 u_int uim_num_val_attr; /* number of values attributes */ 1155 1156 /* uim_num_val_attr of uof_mem_val_attr follows this header */ 1157 }; 1158 1159 struct uof_var_mem_seg { 1160 u_int uvms_sram_base; /* SRAM memory segment base addr */ 1161 u_int uvms_sram_size; /* SRAM segment size bytes */ 1162 u_int uvms_sram_alignment; /* SRAM segment alignment bytes */ 1163 u_int uvms_sdram_base; /* DRAM0 memory segment base addr */ 1164 u_int uvms_sdram_size; /* DRAM0 segment size bytes */ 1165 u_int uvms_sdram_alignment; /* DRAM0 segment alignment bytes */ 1166 u_int uvms_sdram1_base; /* DRAM1 memory segment base addr */ 1167 u_int uvms_sdram1_size; /* DRAM1 segment size bytes */ 1168 u_int uvms_sdram1_alignment; /* DRAM1 segment alignment bytes */ 1169 u_int uvms_scratch_base; /* SCRATCH memory segment base addr */ 1170 u_int uvms_scratch_size; /* SCRATCH segment size bytes */ 1171 u_int uvms_scratch_alignment; /* SCRATCH segment alignment bytes */ 1172 }; 1173 1174 #define SUOF_OBJ_ID_LEN 8 1175 #define SUOF_FID 0x53554f46 1176 #define SUOF_MAJ_VER 0x0 1177 #define SUOF_MIN_VER 0x1 1178 #define SIMG_AE_INIT_SEQ_LEN (50 * sizeof(unsigned long long)) 1179 #define SIMG_AE_INSTS_LEN (0x4000 * sizeof(unsigned long long)) 1180 #define CSS_FWSK_MODULUS_LEN 256 1181 #define CSS_FWSK_EXPONENT_LEN 4 1182 #define CSS_FWSK_PAD_LEN 252 1183 #define CSS_FWSK_PUB_LEN (CSS_FWSK_MODULUS_LEN + \ 1184 CSS_FWSK_EXPONENT_LEN + \ 1185 CSS_FWSK_PAD_LEN) 1186 #define CSS_SIGNATURE_LEN 256 1187 #define CSS_AE_IMG_LEN (sizeof(struct simg_ae_mode) + \ 1188 SIMG_AE_INIT_SEQ_LEN + \ 1189 SIMG_AE_INSTS_LEN) 1190 #define CSS_AE_SIMG_LEN (sizeof(struct css_hdr) + \ 1191 CSS_FWSK_PUB_LEN + \ 1192 CSS_SIGNATURE_LEN + \ 1193 CSS_AE_IMG_LEN) 1194 #define AE_IMG_OFFSET (sizeof(struct css_hdr) + \ 1195 CSS_FWSK_MODULUS_LEN + \ 1196 CSS_FWSK_EXPONENT_LEN + \ 1197 CSS_SIGNATURE_LEN) 1198 #define CSS_MAX_IMAGE_LEN 0x40000 1199 1200 struct fw_auth_desc { 1201 u_int fad_img_len; 1202 u_int fad_reserved; 1203 u_int fad_css_hdr_high; 1204 u_int fad_css_hdr_low; 1205 u_int fad_img_high; 1206 u_int fad_img_low; 1207 u_int fad_signature_high; 1208 u_int fad_signature_low; 1209 u_int fad_fwsk_pub_high; 1210 u_int fad_fwsk_pub_low; 1211 u_int fad_img_ae_mode_data_high; 1212 u_int fad_img_ae_mode_data_low; 1213 u_int fad_img_ae_init_data_high; 1214 u_int fad_img_ae_init_data_low; 1215 u_int fad_img_ae_insts_high; 1216 u_int fad_img_ae_insts_low; 1217 }; 1218 1219 struct auth_chunk { 1220 struct fw_auth_desc ac_fw_auth_desc; 1221 uint64_t ac_chunk_size; 1222 uint64_t ac_chunk_bus_addr; 1223 }; 1224 1225 enum css_fwtype { 1226 CSS_AE_FIRMWARE = 0, 1227 CSS_MMP_FIRMWARE = 1 1228 }; 1229 1230 struct css_hdr { 1231 u_int css_module_type; 1232 u_int css_header_len; 1233 u_int css_header_ver; 1234 u_int css_module_id; 1235 u_int css_module_vendor; 1236 u_int css_date; 1237 u_int css_size; 1238 u_int css_key_size; 1239 u_int css_module_size; 1240 u_int css_exponent_size; 1241 u_int css_fw_type; 1242 u_int css_reserved[21]; 1243 }; 1244 1245 struct simg_ae_mode { 1246 u_int sam_file_id; 1247 u_short sam_maj_ver; 1248 u_short sam_min_ver; 1249 u_int sam_dev_type; 1250 u_short sam_devmax_ver; 1251 u_short sam_devmin_ver; 1252 u_int sam_ae_mask; 1253 u_int sam_ctx_enables; 1254 char sam_fw_type; 1255 char sam_ctx_mode; 1256 char sam_nn_mode; 1257 char sam_lm0_mode; 1258 char sam_lm1_mode; 1259 char sam_scs_mode; 1260 char sam_lm2_mode; 1261 char sam_lm3_mode; 1262 char sam_tindex_mode; 1263 u_char sam_reserved[7]; 1264 char sam_simg_name[256]; 1265 char sam_appmeta_data[256]; 1266 }; 1267 1268 struct suof_file_hdr { 1269 u_int sfh_file_id; 1270 u_int sfh_check_sum; 1271 char sfh_min_ver; 1272 char sfh_maj_ver; 1273 char sfh_fw_type; 1274 char sfh_reserved; 1275 u_short sfh_max_chunks; 1276 u_short sfh_num_chunks; 1277 }; 1278 1279 struct suof_chunk_hdr { 1280 char sch_chunk_id[SUOF_OBJ_ID_LEN]; 1281 uint64_t sch_offset; 1282 uint64_t sch_size; 1283 }; 1284 1285 struct suof_str_tab { 1286 u_int sst_tab_length; 1287 u_int sst_strings; 1288 }; 1289 1290 struct suof_obj_hdr { 1291 u_int soh_img_length; 1292 u_int soh_reserved; 1293 }; 1294 1295 /* -------------------------------------------------------------------------- */ 1296 /* accel */ 1297 1298 enum fw_slice { 1299 FW_SLICE_NULL = 0, /* NULL slice type */ 1300 FW_SLICE_CIPHER = 1, /* CIPHER slice type */ 1301 FW_SLICE_AUTH = 2, /* AUTH slice type */ 1302 FW_SLICE_DRAM_RD = 3, /* DRAM_RD Logical slice type */ 1303 FW_SLICE_DRAM_WR = 4, /* DRAM_WR Logical slice type */ 1304 FW_SLICE_COMP = 5, /* Compression slice type */ 1305 FW_SLICE_XLAT = 6, /* Translator slice type */ 1306 FW_SLICE_DELIMITER /* End delimiter */ 1307 }; 1308 #define MAX_FW_SLICE FW_SLICE_DELIMITER 1309 1310 #define QAT_OPTIMAL_ALIGN_SHIFT 6 1311 #define QAT_OPTIMAL_ALIGN (1 << QAT_OPTIMAL_ALIGN_SHIFT) 1312 1313 enum hw_auth_algo { 1314 HW_AUTH_ALGO_NULL = 0, /* Null hashing */ 1315 HW_AUTH_ALGO_SHA1 = 1, /* SHA1 hashing */ 1316 HW_AUTH_ALGO_MD5 = 2, /* MD5 hashing */ 1317 HW_AUTH_ALGO_SHA224 = 3, /* SHA-224 hashing */ 1318 HW_AUTH_ALGO_SHA256 = 4, /* SHA-256 hashing */ 1319 HW_AUTH_ALGO_SHA384 = 5, /* SHA-384 hashing */ 1320 HW_AUTH_ALGO_SHA512 = 6, /* SHA-512 hashing */ 1321 HW_AUTH_ALGO_AES_XCBC_MAC = 7, /* AES-XCBC-MAC hashing */ 1322 HW_AUTH_ALGO_AES_CBC_MAC = 8, /* AES-CBC-MAC hashing */ 1323 HW_AUTH_ALGO_AES_F9 = 9, /* AES F9 hashing */ 1324 HW_AUTH_ALGO_GALOIS_128 = 10, /* Galois 128 bit hashing */ 1325 HW_AUTH_ALGO_GALOIS_64 = 11, /* Galois 64 hashing */ 1326 HW_AUTH_ALGO_KASUMI_F9 = 12, /* Kasumi F9 hashing */ 1327 HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, /* UIA2/SNOW_3H F9 hashing */ 1328 HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, 1329 HW_AUTH_RESERVED_1 = 15, 1330 HW_AUTH_RESERVED_2 = 16, 1331 HW_AUTH_ALGO_SHA3_256 = 17, 1332 HW_AUTH_RESERVED_3 = 18, 1333 HW_AUTH_ALGO_SHA3_512 = 19, 1334 HW_AUTH_ALGO_DELIMITER = 20 1335 }; 1336 1337 enum hw_auth_mode { 1338 HW_AUTH_MODE0, 1339 HW_AUTH_MODE1, 1340 HW_AUTH_MODE2, 1341 HW_AUTH_MODE_DELIMITER 1342 }; 1343 1344 struct hw_auth_config { 1345 uint32_t config; 1346 /* Configuration used for setting up the slice */ 1347 uint32_t reserved; 1348 /* Reserved */ 1349 }; 1350 1351 #define HW_AUTH_CONFIG_SHA3_ALGO __BITS(22, 23) 1352 #define HW_AUTH_CONFIG_SHA3_PADDING __BIT(16) 1353 #define HW_AUTH_CONFIG_CMPLEN __BITS(14, 8) 1354 /* The length of the digest if the QAT is to the check*/ 1355 #define HW_AUTH_CONFIG_MODE __BITS(7, 4) 1356 #define HW_AUTH_CONFIG_ALGO __BITS(3, 0) 1357 1358 #define HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 1359 __SHIFTIN(mode, HW_AUTH_CONFIG_MODE) | \ 1360 __SHIFTIN(algo, HW_AUTH_CONFIG_ALGO) | \ 1361 __SHIFTIN(cmp_len, HW_AUTH_CONFIG_CMPLEN) 1362 1363 struct hw_auth_counter { 1364 uint32_t counter; /* Counter value */ 1365 uint32_t reserved; /* Reserved */ 1366 }; 1367 1368 struct hw_auth_setup { 1369 struct hw_auth_config auth_config; 1370 /* Configuration word for the auth slice */ 1371 struct hw_auth_counter auth_counter; 1372 /* Auth counter value for this request */ 1373 }; 1374 1375 #define HW_NULL_STATE1_SZ 32 1376 #define HW_MD5_STATE1_SZ 16 1377 #define HW_SHA1_STATE1_SZ 20 1378 #define HW_SHA224_STATE1_SZ 32 1379 #define HW_SHA256_STATE1_SZ 32 1380 #define HW_SHA3_256_STATE1_SZ 32 1381 #define HW_SHA384_STATE1_SZ 64 1382 #define HW_SHA512_STATE1_SZ 64 1383 #define HW_SHA3_512_STATE1_SZ 64 1384 #define HW_SHA3_224_STATE1_SZ 28 1385 #define HW_SHA3_384_STATE1_SZ 48 1386 #define HW_AES_XCBC_MAC_STATE1_SZ 16 1387 #define HW_AES_CBC_MAC_STATE1_SZ 16 1388 #define HW_AES_F9_STATE1_SZ 32 1389 #define HW_KASUMI_F9_STATE1_SZ 16 1390 #define HW_GALOIS_128_STATE1_SZ 16 1391 #define HW_SNOW_3G_UIA2_STATE1_SZ 8 1392 #define HW_ZUC_3G_EIA3_STATE1_SZ 8 1393 #define HW_NULL_STATE2_SZ 32 1394 #define HW_MD5_STATE2_SZ 16 1395 #define HW_SHA1_STATE2_SZ 20 1396 #define HW_SHA224_STATE2_SZ 32 1397 #define HW_SHA256_STATE2_SZ 32 1398 #define HW_SHA3_256_STATE2_SZ 0 1399 #define HW_SHA384_STATE2_SZ 64 1400 #define HW_SHA512_STATE2_SZ 64 1401 #define HW_SHA3_512_STATE2_SZ 0 1402 #define HW_SHA3_224_STATE2_SZ 0 1403 #define HW_SHA3_384_STATE2_SZ 0 1404 #define HW_AES_XCBC_MAC_KEY_SZ 16 1405 #define HW_AES_CBC_MAC_KEY_SZ 16 1406 #define HW_AES_CCM_CBC_E_CTR0_SZ 16 1407 #define HW_F9_IK_SZ 16 1408 #define HW_F9_FK_SZ 16 1409 #define HW_KASUMI_F9_STATE2_SZ (HW_F9_IK_SZ + HW_F9_FK_SZ) 1410 #define HW_AES_F9_STATE2_SZ HW_KASUMI_F9_STATE2_SZ 1411 #define HW_SNOW_3G_UIA2_STATE2_SZ 24 1412 #define HW_ZUC_3G_EIA3_STATE2_SZ 32 1413 #define HW_GALOIS_H_SZ 16 1414 #define HW_GALOIS_LEN_A_SZ 8 1415 #define HW_GALOIS_E_CTR0_SZ 16 1416 1417 struct hw_auth_sha512 { 1418 struct hw_auth_setup inner_setup; 1419 /* Inner loop configuration word for the slice */ 1420 uint8_t state1[HW_SHA512_STATE1_SZ]; 1421 /* Slice state1 variable */ 1422 struct hw_auth_setup outer_setup; 1423 /* Outer configuration word for the slice */ 1424 uint8_t state2[HW_SHA512_STATE2_SZ]; 1425 /* Slice state2 variable */ 1426 }; 1427 1428 union hw_auth_algo_blk { 1429 struct hw_auth_sha512 max; 1430 /* This is the largest possible auth setup block size */ 1431 }; 1432 1433 enum hw_cipher_algo { 1434 HW_CIPHER_ALGO_NULL = 0, /* Null ciphering */ 1435 HW_CIPHER_ALGO_DES = 1, /* DES ciphering */ 1436 HW_CIPHER_ALGO_3DES = 2, /* 3DES ciphering */ 1437 HW_CIPHER_ALGO_AES128 = 3, /* AES-128 ciphering */ 1438 HW_CIPHER_ALGO_AES192 = 4, /* AES-192 ciphering */ 1439 HW_CIPHER_ALGO_AES256 = 5, /* AES-256 ciphering */ 1440 HW_CIPHER_ALGO_ARC4 = 6, /* ARC4 ciphering */ 1441 HW_CIPHER_ALGO_KASUMI = 7, /* Kasumi */ 1442 HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, /* Snow_3G */ 1443 HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, 1444 HW_CIPHER_DELIMITER = 10 /* Delimiter type */ 1445 }; 1446 1447 enum hw_cipher_mode { 1448 HW_CIPHER_ECB_MODE = 0, /* ECB mode */ 1449 HW_CIPHER_CBC_MODE = 1, /* CBC more */ 1450 HW_CIPHER_CTR_MODE = 2, /* CTR mode */ 1451 HW_CIPHER_F8_MODE = 3, /* F8 mode */ 1452 HW_CIPHER_XTS_MODE = 6, 1453 HW_CIPHER_MODE_DELIMITER = 7 /* Delimiter type */ 1454 }; 1455 1456 struct hw_cipher_config { 1457 uint32_t val; /* Cipher slice configuration */ 1458 uint32_t reserved; /* Reserved */ 1459 }; 1460 1461 #define CIPHER_CONFIG_CONVERT __BIT(9) 1462 #define CIPHER_CONFIG_DIR __BIT(8) 1463 #define CIPHER_CONFIG_MODE __BITS(7, 4) 1464 #define CIPHER_CONFIG_ALGO __BITS(3, 0) 1465 #define HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ 1466 __SHIFTIN(mode, CIPHER_CONFIG_MODE) | \ 1467 __SHIFTIN(algo, CIPHER_CONFIG_ALGO) | \ 1468 __SHIFTIN(convert, CIPHER_CONFIG_CONVERT) | \ 1469 __SHIFTIN(dir, CIPHER_CONFIG_DIR) 1470 1471 enum hw_cipher_dir { 1472 HW_CIPHER_ENCRYPT = 0, /* encryption is required */ 1473 HW_CIPHER_DECRYPT = 1, /* decryption is required */ 1474 }; 1475 1476 enum hw_cipher_convert { 1477 HW_CIPHER_NO_CONVERT = 0, /* no key convert is required*/ 1478 HW_CIPHER_KEY_CONVERT = 1, /* key conversion is required*/ 1479 }; 1480 1481 #define CIPHER_MODE_F8_KEY_SZ_MULT 2 1482 #define CIPHER_MODE_XTS_KEY_SZ_MULT 2 1483 1484 #define HW_DES_BLK_SZ 8 1485 #define HW_3DES_BLK_SZ 8 1486 #define HW_NULL_BLK_SZ 8 1487 #define HW_AES_BLK_SZ 16 1488 #define HW_KASUMI_BLK_SZ 8 1489 #define HW_SNOW_3G_BLK_SZ 8 1490 #define HW_ZUC_3G_BLK_SZ 8 1491 #define HW_NULL_KEY_SZ 256 1492 #define HW_DES_KEY_SZ 8 1493 #define HW_3DES_KEY_SZ 24 1494 #define HW_AES_128_KEY_SZ 16 1495 #define HW_AES_192_KEY_SZ 24 1496 #define HW_AES_256_KEY_SZ 32 1497 #define HW_AES_128_F8_KEY_SZ (HW_AES_128_KEY_SZ * \ 1498 CIPHER_MODE_F8_KEY_SZ_MULT) 1499 #define HW_AES_192_F8_KEY_SZ (HW_AES_192_KEY_SZ * \ 1500 CIPHER_MODE_F8_KEY_SZ_MULT) 1501 #define HW_AES_256_F8_KEY_SZ (HW_AES_256_KEY_SZ * \ 1502 CIPHER_MODE_F8_KEY_SZ_MULT) 1503 #define HW_AES_128_XTS_KEY_SZ (HW_AES_128_KEY_SZ * \ 1504 CIPHER_MODE_XTS_KEY_SZ_MULT) 1505 #define HW_AES_256_XTS_KEY_SZ (HW_AES_256_KEY_SZ * \ 1506 CIPHER_MODE_XTS_KEY_SZ_MULT) 1507 #define HW_KASUMI_KEY_SZ 16 1508 #define HW_KASUMI_F8_KEY_SZ (HW_KASUMI_KEY_SZ * \ 1509 CIPHER_MODE_F8_KEY_SZ_MULT) 1510 #define HW_AES_128_XTS_KEY_SZ (HW_AES_128_KEY_SZ * \ 1511 CIPHER_MODE_XTS_KEY_SZ_MULT) 1512 #define HW_AES_256_XTS_KEY_SZ (HW_AES_256_KEY_SZ * \ 1513 CIPHER_MODE_XTS_KEY_SZ_MULT) 1514 #define HW_ARC4_KEY_SZ 256 1515 #define HW_SNOW_3G_UEA2_KEY_SZ 16 1516 #define HW_SNOW_3G_UEA2_IV_SZ 16 1517 #define HW_ZUC_3G_EEA3_KEY_SZ 16 1518 #define HW_ZUC_3G_EEA3_IV_SZ 16 1519 #define HW_MODE_F8_NUM_REG_TO_CLEAR 2 1520 1521 struct hw_cipher_aes256_f8 { 1522 struct hw_cipher_config cipher_config; 1523 /* Cipher configuration word for the slice set to 1524 * AES-256 and the F8 mode */ 1525 uint8_t key[HW_AES_256_F8_KEY_SZ]; 1526 /* Cipher key */ 1527 }; 1528 1529 union hw_cipher_algo_blk { 1530 struct hw_cipher_aes256_f8 max; /* AES-256 F8 Cipher */ 1531 /* This is the largest possible cipher setup block size */ 1532 }; 1533 1534 struct flat_buffer_desc { 1535 uint32_t data_len_in_bytes; 1536 uint32_t reserved; 1537 uint64_t phy_buffer; 1538 }; 1539 1540 struct buffer_list_desc { 1541 uint64_t resrvd; 1542 uint32_t num_buffers; 1543 uint32_t reserved; 1544 struct flat_buffer_desc phy_buffers[]; 1545 }; 1546 1547 /* -------------------------------------------------------------------------- */ 1548 /* look aside */ 1549 1550 enum fw_la_cmd_id { 1551 FW_LA_CMD_CIPHER, /* Cipher Request */ 1552 FW_LA_CMD_AUTH, /* Auth Request */ 1553 FW_LA_CMD_CIPHER_HASH, /* Cipher-Hash Request */ 1554 FW_LA_CMD_HASH_CIPHER, /* Hash-Cipher Request */ 1555 FW_LA_CMD_TRNG_GET_RANDOM, /* TRNG Get Random Request */ 1556 FW_LA_CMD_TRNG_TEST, /* TRNG Test Request */ 1557 FW_LA_CMD_SSL3_KEY_DERIVE, /* SSL3 Key Derivation Request */ 1558 FW_LA_CMD_TLS_V1_1_KEY_DERIVE, /* TLS Key Derivation Request */ 1559 FW_LA_CMD_TLS_V1_2_KEY_DERIVE, /* TLS Key Derivation Request */ 1560 FW_LA_CMD_MGF1, /* MGF1 Request */ 1561 FW_LA_CMD_AUTH_PRE_COMP, /* Auth Pre-Compute Request */ 1562 #if 0 /* incompatible between qat 1.5 and 1.7 */ 1563 FW_LA_CMD_CIPHER_CIPHER, /* Cipher-Cipher Request */ 1564 FW_LA_CMD_HASH_HASH, /* Hash-Hash Request */ 1565 FW_LA_CMD_CIPHER_PRE_COMP, /* Auth Pre-Compute Request */ 1566 #endif 1567 FW_LA_CMD_DELIMITER, /* Delimiter type */ 1568 }; 1569 1570 #endif 1571