xref: /qemu/include/hw/i2c/pnv_i2c_regs.h (revision 4d2cd2d8) 
1 /*
2  * PowerNV I2C Controller Register Definitions
3  *
4  * Copyright (c) 2024, IBM Corporation.
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #ifndef PNV_I2C_REGS_H
10 #define PNV_I2C_REGS_H
11 
12 /* I2C FIFO register */
13 #define I2C_FIFO_REG                    0x4
14 #define I2C_FIFO                        PPC_BITMASK(0, 7)
15 
16 /* I2C command register */
17 #define I2C_CMD_REG                     0x5
18 #define I2C_CMD_WITH_START              PPC_BIT(0)
19 #define I2C_CMD_WITH_ADDR               PPC_BIT(1)
20 #define I2C_CMD_READ_CONT               PPC_BIT(2)
21 #define I2C_CMD_WITH_STOP               PPC_BIT(3)
22 #define I2C_CMD_INTR_STEERING           PPC_BITMASK(6, 7) /* P9 */
23 #define   I2C_CMD_INTR_STEER_HOST       1
24 #define   I2C_CMD_INTR_STEER_OCC        2
25 #define I2C_CMD_DEV_ADDR                PPC_BITMASK(8, 14)
26 #define I2C_CMD_READ_NOT_WRITE          PPC_BIT(15)
27 #define I2C_CMD_LEN_BYTES               PPC_BITMASK(16, 31)
28 #define I2C_MAX_TFR_LEN                 0xfff0ull
29 
30 /* I2C mode register */
31 #define I2C_MODE_REG                    0x6
32 #define I2C_MODE_BIT_RATE_DIV           PPC_BITMASK(0, 15)
33 #define I2C_MODE_PORT_NUM               PPC_BITMASK(16, 21)
34 #define I2C_MODE_ENHANCED               PPC_BIT(28)
35 #define I2C_MODE_DIAGNOSTIC             PPC_BIT(29)
36 #define I2C_MODE_PACING_ALLOW           PPC_BIT(30)
37 #define I2C_MODE_WRAP                   PPC_BIT(31)
38 
39 /* I2C watermark register */
40 #define I2C_WATERMARK_REG               0x7
41 #define I2C_WATERMARK_HIGH              PPC_BITMASK(16, 19)
42 #define I2C_WATERMARK_LOW               PPC_BITMASK(24, 27)
43 
44 /*
45  * I2C interrupt mask and condition registers
46  *
47  * NB: The function of 0x9 and 0xa changes depending on whether you're reading
48  *     or writing to them. When read they return the interrupt condition bits
49  *     and on writes they update the interrupt mask register.
50  *
51  *  The bit definitions are the same for all the interrupt registers.
52  */
53 #define I2C_INTR_MASK_REG               0x8
54 
55 #define I2C_INTR_RAW_COND_REG           0x9 /* read */
56 #define I2C_INTR_MASK_OR_REG            0x9 /* write*/
57 
58 #define I2C_INTR_COND_REG               0xa /* read */
59 #define I2C_INTR_MASK_AND_REG           0xa /* write */
60 
61 #define I2C_INTR_ALL                    PPC_BITMASK(16, 31)
62 #define I2C_INTR_INVALID_CMD            PPC_BIT(16)
63 #define I2C_INTR_LBUS_PARITY_ERR        PPC_BIT(17)
64 #define I2C_INTR_BKEND_OVERRUN_ERR      PPC_BIT(18)
65 #define I2C_INTR_BKEND_ACCESS_ERR       PPC_BIT(19)
66 #define I2C_INTR_ARBT_LOST_ERR          PPC_BIT(20)
67 #define I2C_INTR_NACK_RCVD_ERR          PPC_BIT(21)
68 #define I2C_INTR_DATA_REQ               PPC_BIT(22)
69 #define I2C_INTR_CMD_COMP               PPC_BIT(23)
70 #define I2C_INTR_STOP_ERR               PPC_BIT(24)
71 #define I2C_INTR_I2C_BUSY               PPC_BIT(25)
72 #define I2C_INTR_NOT_I2C_BUSY           PPC_BIT(26)
73 #define I2C_INTR_SCL_EQ_1               PPC_BIT(28)
74 #define I2C_INTR_SCL_EQ_0               PPC_BIT(29)
75 #define I2C_INTR_SDA_EQ_1               PPC_BIT(30)
76 #define I2C_INTR_SDA_EQ_0               PPC_BIT(31)
77 
78 /* I2C status register */
79 #define I2C_RESET_I2C_REG               0xb /* write */
80 #define I2C_RESET_ERRORS                0xc
81 #define I2C_STAT_REG                    0xb /* read */
82 #define I2C_STAT_INVALID_CMD            PPC_BIT(0)
83 #define I2C_STAT_LBUS_PARITY_ERR        PPC_BIT(1)
84 #define I2C_STAT_BKEND_OVERRUN_ERR      PPC_BIT(2)
85 #define I2C_STAT_BKEND_ACCESS_ERR       PPC_BIT(3)
86 #define I2C_STAT_ARBT_LOST_ERR          PPC_BIT(4)
87 #define I2C_STAT_NACK_RCVD_ERR          PPC_BIT(5)
88 #define I2C_STAT_DATA_REQ               PPC_BIT(6)
89 #define I2C_STAT_CMD_COMP               PPC_BIT(7)
90 #define I2C_STAT_STOP_ERR               PPC_BIT(8)
91 #define I2C_STAT_UPPER_THRS             PPC_BITMASK(9, 15)
92 #define I2C_STAT_ANY_I2C_INTR           PPC_BIT(16)
93 #define I2C_STAT_PORT_HISTORY_BUSY      PPC_BIT(19)
94 #define I2C_STAT_SCL_INPUT_LEVEL        PPC_BIT(20)
95 #define I2C_STAT_SDA_INPUT_LEVEL        PPC_BIT(21)
96 #define I2C_STAT_PORT_BUSY              PPC_BIT(22)
97 #define I2C_STAT_INTERFACE_BUSY         PPC_BIT(23)
98 #define I2C_STAT_FIFO_ENTRY_COUNT       PPC_BITMASK(24, 31)
99 
100 #define I2C_STAT_ANY_ERR (I2C_STAT_INVALID_CMD | I2C_STAT_LBUS_PARITY_ERR | \
101                           I2C_STAT_BKEND_OVERRUN_ERR | \
102                           I2C_STAT_BKEND_ACCESS_ERR | I2C_STAT_ARBT_LOST_ERR | \
103                           I2C_STAT_NACK_RCVD_ERR | I2C_STAT_STOP_ERR)
104 
105 
106 #define I2C_INTR_ACTIVE \
107         ((I2C_STAT_ANY_ERR >> 16) | I2C_INTR_CMD_COMP | I2C_INTR_DATA_REQ)
108 
109 /* Pseudo-status used for timeouts */
110 #define I2C_STAT_PSEUDO_TIMEOUT         PPC_BIT(63)
111 
112 /* I2C extended status register */
113 #define I2C_EXTD_STAT_REG               0xc
114 #define I2C_EXTD_STAT_FIFO_SIZE         PPC_BITMASK(0, 7)
115 #define I2C_EXTD_STAT_MSM_CURSTATE      PPC_BITMASK(11, 15)
116 #define I2C_EXTD_STAT_SCL_IN_SYNC       PPC_BIT(16)
117 #define I2C_EXTD_STAT_SDA_IN_SYNC       PPC_BIT(17)
118 #define I2C_EXTD_STAT_S_SCL             PPC_BIT(18)
119 #define I2C_EXTD_STAT_S_SDA             PPC_BIT(19)
120 #define I2C_EXTD_STAT_M_SCL             PPC_BIT(20)
121 #define I2C_EXTD_STAT_M_SDA             PPC_BIT(21)
122 #define I2C_EXTD_STAT_HIGH_WATER        PPC_BIT(22)
123 #define I2C_EXTD_STAT_LOW_WATER         PPC_BIT(23)
124 #define I2C_EXTD_STAT_I2C_BUSY          PPC_BIT(24)
125 #define I2C_EXTD_STAT_SELF_BUSY         PPC_BIT(25)
126 #define I2C_EXTD_STAT_I2C_VERSION       PPC_BITMASK(27, 31)
127 
128 /* I2C residual front end/back end length */
129 #define I2C_RESIDUAL_LEN_REG            0xd
130 #define I2C_RESIDUAL_FRONT_END          PPC_BITMASK(0, 15)
131 #define I2C_RESIDUAL_BACK_END           PPC_BITMASK(16, 31)
132 
133 /* Port busy register */
134 #define I2C_PORT_BUSY_REG               0xe
135 #define I2C_SET_S_SCL_REG               0xd
136 #define I2C_RESET_S_SCL_REG             0xf
137 #define I2C_SET_S_SDA_REG               0x10
138 #define I2C_RESET_S_SDA_REG             0x11
139 
140 #define PNV_I2C_FIFO_SIZE 8
141 #define PNV_I2C_MAX_BUSSES 64
142 
143 #endif /* PNV_I2C_REGS_H */
144