xref: /linux/drivers/net/ethernet/intel/ice/ice_sched.h (revision 91427e6d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_SCHED_H_
5 #define _ICE_SCHED_H_
6 
7 #include "ice_common.h"
8 
9 /**
10  * DOC: ice_sched.h
11  *
12  * This header file stores everything that is needed for broadly understood
13  * scheduler. It consists of defines related to layers, structures related to
14  * aggregator, functions declarations and others.
15  */
16 
17 #define ICE_SCHED_5_LAYERS	5
18 #define ICE_SCHED_9_LAYERS	9
19 
20 #define SCHED_NODE_NAME_MAX_LEN 32
21 
22 #define ICE_QGRP_LAYER_OFFSET	2
23 #define ICE_VSI_LAYER_OFFSET	4
24 #define ICE_AGG_LAYER_OFFSET	6
25 #define ICE_SCHED_INVAL_LAYER_NUM	0xFF
26 /* Burst size is a 12 bits register that is configured while creating the RL
27  * profile(s). MSB is a granularity bit and tells the granularity type
28  * 0 - LSB bits are in 64 bytes granularity
29  * 1 - LSB bits are in 1K bytes granularity
30  */
31 #define ICE_64_BYTE_GRANULARITY			0
32 #define ICE_KBYTE_GRANULARITY			BIT(11)
33 #define ICE_MIN_BURST_SIZE_ALLOWED		64 /* In Bytes */
34 #define ICE_MAX_BURST_SIZE_ALLOWED \
35 	((BIT(11) - 1) * 1024) /* In Bytes */
36 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
37 	((BIT(11) - 1) * 64) /* In Bytes */
38 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY	ICE_MAX_BURST_SIZE_ALLOWED
39 
40 #define ICE_RL_PROF_ACCURACY_BYTES 128
41 #define ICE_RL_PROF_MULTIPLIER 10000
42 #define ICE_RL_PROF_TS_MULTIPLIER 32
43 #define ICE_RL_PROF_FRACTION 512
44 
45 #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059
46 #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667
47 #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571
48 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000
49 
50 /* BW rate limit profile parameters list entry along
51  * with bandwidth maintained per layer in port info
52  */
53 struct ice_aqc_rl_profile_info {
54 	struct ice_aqc_rl_profile_elem profile;
55 	struct list_head list_entry;
56 	u32 bw;			/* requested */
57 	u16 prof_id_ref;	/* profile ID to node association ref count */
58 };
59 
60 struct ice_sched_agg_vsi_info {
61 	struct list_head list_entry;
62 	DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
63 	u16 vsi_handle;
64 	/* save aggregator VSI TC bitmap */
65 	DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
66 };
67 
68 struct ice_sched_agg_info {
69 	struct list_head agg_vsi_list;
70 	struct list_head list_entry;
71 	DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
72 	u32 agg_id;
73 	enum ice_agg_type agg_type;
74 	/* bw_t_info saves aggregator BW information */
75 	struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
76 	/* save aggregator TC bitmap */
77 	DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
78 };
79 
80 /* FW AQ command calls */
81 int
82 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
83 			 struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
84 			 u16 *elems_ret, struct ice_sq_cd *cd);
85 
86 int
87 ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,
88 			  enum ice_rl_type rl_type, u32 bw);
89 
90 int
91 ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,
92 		      enum ice_rl_type rl_type, u32 bw, u8 layer_num);
93 
94 int
95 ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,
96 		    struct ice_sched_node *parent, u8 layer, u16 num_nodes,
97 		    u16 *num_nodes_added, u32 *first_node_teid,
98 		    struct ice_sched_node **prealloc_node);
99 
100 int
101 ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,
102 		     u16 num_items, u32 *list);
103 
104 int ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node,
105 				u16 priority);
106 int ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, u16 weight);
107 
108 int ice_sched_init_port(struct ice_port_info *pi);
109 int ice_sched_query_res_alloc(struct ice_hw *hw);
110 void ice_sched_get_psm_clk_freq(struct ice_hw *hw);
111 
112 void ice_sched_clear_port(struct ice_port_info *pi);
113 void ice_sched_cleanup_all(struct ice_hw *hw);
114 void ice_sched_clear_agg(struct ice_hw *hw);
115 
116 struct ice_sched_node *
117 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
118 int
119 ice_sched_add_node(struct ice_port_info *pi, u8 layer,
120 		   struct ice_aqc_txsched_elem_data *info,
121 		   struct ice_sched_node *prealloc_node);
122 void
123 ice_sched_update_parent(struct ice_sched_node *new_parent,
124 			struct ice_sched_node *node);
125 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
126 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
127 struct ice_sched_node *
128 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
129 			   u8 owner);
130 int
131 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
132 		  u8 owner, bool enable);
133 int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
134 int ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle);
135 
136 /* Tx scheduler rate limiter functions */
137 int
138 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,
139 	    enum ice_agg_type agg_type, u8 tc_bitmap);
140 int
141 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,
142 		    u8 tc_bitmap);
143 int
144 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
145 		 u16 q_handle, enum ice_rl_type rl_type, u32 bw);
146 int
147 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
148 		      u16 q_handle, enum ice_rl_type rl_type);
149 int
150 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
151 			  enum ice_rl_type rl_type, u32 bw);
152 int
153 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
154 			       enum ice_rl_type rl_type);
155 int ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
156 int
157 ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids,
158 			       bool suspend);
159 struct ice_sched_node *
160 ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
161 		       u32 agg_id);
162 u8 ice_sched_get_agg_layer(struct ice_hw *hw);
163 u8 ice_sched_get_vsi_layer(struct ice_hw *hw);
164 struct ice_sched_node *
165 ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node,
166 			      u16 *num_nodes);
167 int
168 ice_sched_add_nodes_to_layer(struct ice_port_info *pi,
169 			     struct ice_sched_node *tc_node,
170 			     struct ice_sched_node *parent, u8 layer,
171 			     u16 num_nodes, u32 *first_node_teid,
172 			     u16 *num_nodes_added);
173 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
174 void ice_sched_replay_agg(struct ice_hw *hw);
175 int ice_aq_move_sched_elems(struct ice_hw *hw, struct ice_aqc_move_elem *buf,
176 			    u16 buf_size, u16 *grps_movd);
177 int ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
178 int ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
179 #endif /* _ICE_SCHED_H_ */
180