1 /* $NetBSD: intel_dpll_mgr.h,v 1.3 2021/12/19 12:32:15 riastradh Exp $ */ 2 3 /* 4 * Copyright © 2012-2016 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _INTEL_DPLL_MGR_H_ 28 #define _INTEL_DPLL_MGR_H_ 29 30 #include <linux/types.h> 31 32 #include "intel_display.h" 33 #include "intel_wakeref.h" 34 35 /*FIXME: Move this to a more appropriate place. */ 36 #define abs_diff(a, b) ({ \ 37 typeof(a) __a = (a); \ 38 typeof(b) __b = (b); \ 39 (void) (&__a == &__b); \ 40 __a > __b ? (__a - __b) : (__b - __a); }) 41 42 struct drm_device; 43 struct drm_i915_private; 44 struct intel_atomic_state; 45 struct intel_crtc; 46 struct intel_crtc_state; 47 struct intel_encoder; 48 struct intel_shared_dpll; 49 50 /** 51 * enum intel_dpll_id - possible DPLL ids 52 * 53 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 54 */ 55 enum intel_dpll_id { 56 /** 57 * @DPLL_ID_PRIVATE: non-shared dpll in use 58 */ 59 DPLL_ID_PRIVATE = -1, 60 61 /** 62 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 63 */ 64 DPLL_ID_PCH_PLL_A = 0, 65 /** 66 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 67 */ 68 DPLL_ID_PCH_PLL_B = 1, 69 70 71 /** 72 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 73 */ 74 DPLL_ID_WRPLL1 = 0, 75 /** 76 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 77 */ 78 DPLL_ID_WRPLL2 = 1, 79 /** 80 * @DPLL_ID_SPLL: HSW and BDW SPLL 81 */ 82 DPLL_ID_SPLL = 2, 83 /** 84 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 85 */ 86 DPLL_ID_LCPLL_810 = 3, 87 /** 88 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 89 */ 90 DPLL_ID_LCPLL_1350 = 4, 91 /** 92 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 93 */ 94 DPLL_ID_LCPLL_2700 = 5, 95 96 97 /** 98 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 99 */ 100 DPLL_ID_SKL_DPLL0 = 0, 101 /** 102 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 103 */ 104 DPLL_ID_SKL_DPLL1 = 1, 105 /** 106 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 107 */ 108 DPLL_ID_SKL_DPLL2 = 2, 109 /** 110 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 111 */ 112 DPLL_ID_SKL_DPLL3 = 3, 113 114 115 /** 116 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 117 */ 118 DPLL_ID_ICL_DPLL0 = 0, 119 /** 120 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 121 */ 122 DPLL_ID_ICL_DPLL1 = 1, 123 /** 124 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 125 */ 126 DPLL_ID_EHL_DPLL4 = 2, 127 /** 128 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 129 */ 130 DPLL_ID_ICL_TBTPLL = 2, 131 /** 132 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), 133 * TGL TC PLL 1 port 1 (TC1) 134 */ 135 DPLL_ID_ICL_MGPLL1 = 3, 136 /** 137 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 138 * TGL TC PLL 1 port 2 (TC2) 139 */ 140 DPLL_ID_ICL_MGPLL2 = 4, 141 /** 142 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 143 * TGL TC PLL 1 port 3 (TC3) 144 */ 145 DPLL_ID_ICL_MGPLL3 = 5, 146 /** 147 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 148 * TGL TC PLL 1 port 4 (TC4) 149 */ 150 DPLL_ID_ICL_MGPLL4 = 6, 151 /** 152 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 153 */ 154 DPLL_ID_TGL_MGPLL5 = 7, 155 /** 156 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 157 */ 158 DPLL_ID_TGL_MGPLL6 = 8, 159 }; 160 161 #define I915_NUM_PLLS 9 162 163 enum icl_port_dpll_id { 164 ICL_PORT_DPLL_DEFAULT, 165 ICL_PORT_DPLL_MG_PHY, 166 167 ICL_PORT_DPLL_COUNT, 168 }; 169 170 struct intel_dpll_hw_state { 171 /* i9xx, pch plls */ 172 u32 dpll; 173 u32 dpll_md; 174 u32 fp0; 175 u32 fp1; 176 177 /* hsw, bdw */ 178 u32 wrpll; 179 u32 spll; 180 181 /* skl */ 182 /* 183 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 184 * lower part of ctrl1 and they get shifted into position when writing 185 * the register. This allows us to easily compare the state to share 186 * the DPLL. 187 */ 188 u32 ctrl1; 189 /* HDMI only, 0 when used for DP */ 190 u32 cfgcr1, cfgcr2; 191 192 /* cnl */ 193 u32 cfgcr0; 194 /* CNL also uses cfgcr1 */ 195 196 /* bxt */ 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; 198 199 /* 200 * ICL uses the following, already defined: 201 * u32 cfgcr0, cfgcr1; 202 */ 203 u32 mg_refclkin_ctl; 204 u32 mg_clktop2_coreclkctl1; 205 u32 mg_clktop2_hsclkctl; 206 u32 mg_pll_div0; 207 u32 mg_pll_div1; 208 u32 mg_pll_lf; 209 u32 mg_pll_frac_lock; 210 u32 mg_pll_ssc; 211 u32 mg_pll_bias; 212 u32 mg_pll_tdc_coldst_bias; 213 u32 mg_pll_bias_mask; 214 u32 mg_pll_tdc_coldst_bias_mask; 215 }; 216 217 /** 218 * struct intel_shared_dpll_state - hold the DPLL atomic state 219 * 220 * This structure holds an atomic state for the DPLL, that can represent 221 * either its current state (in struct &intel_shared_dpll) or a desired 222 * future state which would be applied by an atomic mode set (stored in 223 * a struct &intel_atomic_state). 224 * 225 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). 226 */ 227 struct intel_shared_dpll_state { 228 /** 229 * @crtc_mask: mask of CRTC using this DPLL, active or not 230 */ 231 unsigned crtc_mask; 232 233 /** 234 * @hw_state: hardware configuration for the DPLL stored in 235 * struct &intel_dpll_hw_state. 236 */ 237 struct intel_dpll_hw_state hw_state; 238 }; 239 240 /** 241 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs 242 */ 243 struct intel_shared_dpll_funcs { 244 /** 245 * @prepare: 246 * 247 * Optional hook to perform operations prior to enabling the PLL. 248 * Called from intel_prepare_shared_dpll() function unless the PLL 249 * is already enabled. 250 */ 251 void (*prepare)(struct drm_i915_private *dev_priv, 252 struct intel_shared_dpll *pll); 253 254 /** 255 * @enable: 256 * 257 * Hook for enabling the pll, called from intel_enable_shared_dpll() 258 * if the pll is not already enabled. 259 */ 260 void (*enable)(struct drm_i915_private *dev_priv, 261 struct intel_shared_dpll *pll); 262 263 /** 264 * @disable: 265 * 266 * Hook for disabling the pll, called from intel_disable_shared_dpll() 267 * only when it is safe to disable the pll, i.e., there are no more 268 * tracked users for it. 269 */ 270 void (*disable)(struct drm_i915_private *dev_priv, 271 struct intel_shared_dpll *pll); 272 273 /** 274 * @get_hw_state: 275 * 276 * Hook for reading the values currently programmed to the DPLL 277 * registers. This is used for initial hw state readout and state 278 * verification after a mode set. 279 */ 280 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 281 struct intel_shared_dpll *pll, 282 struct intel_dpll_hw_state *hw_state); 283 }; 284 285 /** 286 * struct dpll_info - display PLL platform specific info 287 */ 288 struct dpll_info { 289 /** 290 * @name: DPLL name; used for logging 291 */ 292 const char *name; 293 294 /** 295 * @funcs: platform specific hooks 296 */ 297 const struct intel_shared_dpll_funcs *funcs; 298 299 /** 300 * @id: unique indentifier for this DPLL; should match the index in the 301 * dev_priv->shared_dplls array 302 */ 303 enum intel_dpll_id id; 304 305 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 306 /** 307 * @flags: 308 * 309 * INTEL_DPLL_ALWAYS_ON 310 * Inform the state checker that the DPLL is kept enabled even if 311 * not in use by any CRTC. 312 */ 313 u32 flags; 314 }; 315 316 /** 317 * struct intel_shared_dpll - display PLL with tracked state and users 318 */ 319 struct intel_shared_dpll { 320 /** 321 * @state: 322 * 323 * Store the state for the pll, including its hw state 324 * and CRTCs using it. 325 */ 326 struct intel_shared_dpll_state state; 327 328 /** 329 * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL 330 */ 331 unsigned active_mask; 332 333 /** 334 * @on: is the PLL actually active? Disabled during modeset 335 */ 336 bool on; 337 338 /** 339 * @info: platform specific info 340 */ 341 const struct dpll_info *info; 342 343 /** 344 * @wakeref: In some platforms a device-level runtime pm reference may 345 * need to be grabbed to disable DC states while this DPLL is enabled 346 */ 347 intel_wakeref_t wakeref; 348 }; 349 350 #define SKL_DPLL0 0 351 #define SKL_DPLL1 1 352 #define SKL_DPLL2 2 353 #define SKL_DPLL3 3 354 355 /* shared dpll functions */ 356 struct intel_shared_dpll * 357 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 358 enum intel_dpll_id id); 359 enum intel_dpll_id 360 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 361 struct intel_shared_dpll *pll); 362 void assert_shared_dpll(struct drm_i915_private *dev_priv, 363 struct intel_shared_dpll *pll, 364 bool state); 365 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 366 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 367 bool intel_reserve_shared_dplls(struct intel_atomic_state *state, 368 struct intel_crtc *crtc, 369 struct intel_encoder *encoder); 370 void intel_release_shared_dplls(struct intel_atomic_state *state, 371 struct intel_crtc *crtc); 372 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, 373 enum icl_port_dpll_id port_dpll_id); 374 void intel_update_active_dpll(struct intel_atomic_state *state, 375 struct intel_crtc *crtc, 376 struct intel_encoder *encoder); 377 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state); 378 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); 379 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); 380 void intel_shared_dpll_swap_state(struct intel_atomic_state *state); 381 void intel_shared_dpll_init(struct drm_device *dev); 382 void intel_shared_dpll_cleanup(struct drm_device *dev); 383 384 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, 385 const struct intel_dpll_hw_state *hw_state); 386 int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv); 387 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 388 bool intel_dpll_is_combophy(enum intel_dpll_id id); 389 390 #endif /* _INTEL_DPLL_MGR_H_ */ 391