1 //! \file 2 /* 3 ** Copyright (C) - Triton 4 ** 5 ** This program is under the terms of the Apache License 2.0. 6 */ 7 8 #ifndef TRITON_ARCHENUMS_HPP 9 #define TRITON_ARCHENUMS_HPP 10 11 #include <cstdint> 12 #include <functional> 13 14 15 16 //! The Triton namespace 17 namespace triton { 18 /*! 19 * \addtogroup triton 20 * @{ 21 */ 22 23 //! The Triton namespace 24 namespace arch { 25 /*! 26 * \ingroup triton 27 * \addtogroup arch 28 * @{ 29 */ 30 31 /*! Types of architecture */ 32 enum architecture_e { 33 ARCH_INVALID = 0, /*!< Invalid architecture. */ 34 ARCH_AARCH64, /*!< AArch64 architecture. */ 35 ARCH_ARM32, /*!< ARM32 architecture. */ 36 ARCH_X86, /*!< X86 architecture. */ 37 ARCH_X86_64, /*!< X86_64 architecture. */ 38 }; 39 40 /*! Types of endianness */ 41 enum endianness_e { 42 LE_ENDIANNESS, /*!< Little endian. */ 43 BE_ENDIANNESS, /*!< Big endian. */ 44 }; 45 46 /*! Types of operand */ 47 enum operand_e { 48 OP_INVALID = 0, //!< invalid operand 49 OP_IMM, //!< immediate operand 50 OP_MEM, //!< memory operand 51 OP_REG //!< register operand 52 }; 53 54 //! Types of register. 55 enum register_e { 56 ID_REG_INVALID = 0, //!< invalid = 0 57 58 #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5, _6, _7, _8) \ 59 ID_REG_X86_##UPPER_NAME, 60 #define REG_SPEC_NO_CAPSTONE REG_SPEC 61 #include "triton/x86.spec" 62 63 #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) \ 64 ID_REG_AARCH64_##UPPER_NAME, 65 #define REG_SPEC_NO_CAPSTONE REG_SPEC 66 #include "triton/aarch64.spec" 67 68 #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) \ 69 ID_REG_ARM32_##UPPER_NAME, 70 #define REG_SPEC_NO_CAPSTONE REG_SPEC 71 #include "triton/arm32.spec" 72 73 /* Must be the last item */ 74 ID_REG_LAST_ITEM //!< must be the last item 75 }; 76 77 //! The x86 namespace 78 namespace x86 { 79 /*! 80 * \ingroup arch 81 * \addtogroup x86 82 * @{ 83 */ 84 85 /*! \brief Types of prefix. 86 * 87 * \details 88 * Note that `REP` and `REPE` have the some opcode. The `REP` 89 * prefix becomes a `REPE` if the instruction modifies `ZF`. 90 */ 91 enum prefix_e { 92 ID_PREFIX_INVALID = 0, //!< invalid 93 ID_PREFIX_LOCK, //!< LOCK 94 ID_PREFIX_REP, //!< REP 95 ID_PREFIX_REPE, //!< REPE 96 ID_PREFIX_REPNE, //!< REPNE 97 98 /* Must be the last item */ 99 ID_PREFIX_LAST_ITEM //!< must be the last item 100 }; 101 102 /*! @} End of x86 namespace */ 103 }; 104 105 //! The Arm namespace 106 namespace arm { 107 /*! 108 * \ingroup arch 109 * \addtogroup arm 110 * @{ 111 */ 112 113 //! Types of shift 114 enum shift_e { 115 ID_SHIFT_INVALID = 0, //!< invalid 116 ID_SHIFT_ASR, //!< Arithmetic Shift Right (immediate) 117 ID_SHIFT_LSL, //!< Logical Shift Left (immediate) 118 ID_SHIFT_LSR, //!< Logical Shift Right (immediate) 119 ID_SHIFT_ROR, //!< Rotate Right (immediate) 120 ID_SHIFT_RRX, //!< Rotate Right with Extend (immediate) 121 ID_SHIFT_ASR_REG, //!< Arithmetic Shift Right (register) 122 ID_SHIFT_LSL_REG, //!< Logical Shift Left (register) 123 ID_SHIFT_LSR_REG, //!< Logical Shift Right (register) 124 ID_SHIFT_ROR_REG, //!< Rotate Right (register) 125 ID_SHIFT_RRX_REG, //!< Rotate Right with Extend (register) 126 ID_SHIFT_LAST_ITEM, //!< Must be the last item 127 }; 128 129 //! Types of extend 130 enum extend_e { 131 ID_EXTEND_INVALID = 0, //!< invalid 132 ID_EXTEND_UXTB, //!< Extracts a byte (8-bit) value from a register and zero extends it to the size of the register 133 ID_EXTEND_UXTH, //!< Extracts a halfword (16-bit) value from a register and zero extends it to the size of the register 134 ID_EXTEND_UXTW, //!< Extracts a word (32-bit) value from a register and zero extends it to the size of the register 135 ID_EXTEND_UXTX, //!< Use the whole 64-bit register 136 ID_EXTEND_SXTB, //!< Extracts a byte (8-bit) value from a register and zero extends it to the size of the register 137 ID_EXTEND_SXTH, //!< Extracts a halfword (16-bit) value from a register and zero extends it to the size of the register 138 ID_EXTEND_SXTW, //!< Extracts a word (32-bit) value from a register and zero extends it to the size of the register 139 ID_EXTEND_SXTX, //!< Use the whole 64-bit register 140 ID_EXTEND_LAST_ITEM, //!< Must be the last item 141 }; 142 143 //! Types of condition 144 enum condition_e { 145 ID_CONDITION_INVALID = 0, //!< invalid 146 ID_CONDITION_AL, //!< Always. Any flags. This suffix is normally omitted. 147 ID_CONDITION_EQ, //!< Equal. Z set. 148 ID_CONDITION_GE, //!< Signed >=. N and V the same. 149 ID_CONDITION_GT, //!< Signed >. Z clear, N and V the same. 150 ID_CONDITION_HI, //!< Higher (unsigned >). C set and Z clear. 151 ID_CONDITION_HS, //!< Higher or same (unsigned >=). C set. 152 ID_CONDITION_LE, //!< Signed <=. Z set, N and V differ. 153 ID_CONDITION_LO, //!< Lower (unsigned <). C clear. 154 ID_CONDITION_LS, //!< Lower or same (unsigned <=). C clear or Z set. 155 ID_CONDITION_LT, //!< Signed <. N and V differ. 156 ID_CONDITION_MI, //!< Negative. N set. 157 ID_CONDITION_NE, //!< Not equal. Z clear. 158 ID_CONDITION_PL, //!< Positive or zero. N clear. 159 ID_CONDITION_VC, //!< No overflow. V clear. 160 ID_CONDITION_VS, //!< Overflow. V set. 161 ID_CONDITION_LAST_ITEM, //!< must be the last item. 162 }; 163 164 /*! @} End of arm namespace */ 165 }; 166 /*! @} End of arch namespace */ 167 }; 168 /*! @} End of triton namespace */ 169 }; 170 171 namespace std { 172 //! Define the hash function for register_e to be use in stl containers like unordered_map 173 template <> struct hash<triton::arch::register_e> : public hash<uint64_t> { 174 }; 175 }; 176 177 #endif /* TRITON_ARCHENUMS_HPP */ 178