1 /* $OpenBSD: igc_hw.h,v 1.3 2024/05/13 01:22:47 jsg Exp $ */ 2 /*- 3 * Copyright 2021 Intel Corp 4 * Copyright 2021 Rubicon Communications, LLC (Netgate) 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * $FreeBSD$ 8 */ 9 10 #ifndef _IGC_HW_H_ 11 #define _IGC_HW_H_ 12 13 #include "bpfilter.h" 14 #include "vlan.h" 15 16 #include <sys/param.h> 17 #include <sys/systm.h> 18 #include <sys/sockio.h> 19 #include <sys/mbuf.h> 20 #include <sys/malloc.h> 21 #include <sys/kernel.h> 22 #include <sys/socket.h> 23 #include <sys/device.h> 24 #include <sys/endian.h> 25 #include <sys/intrmap.h> 26 27 #include <net/if.h> 28 #include <net/if_media.h> 29 #include <net/toeplitz.h> 30 31 #include <netinet/in.h> 32 #include <netinet/if_ether.h> 33 34 #if NBPFILTER > 0 35 #include <net/bpf.h> 36 #endif 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/pci/igc_base.h> 46 #include <dev/pci/igc_defines.h> 47 #include <dev/pci/igc_i225.h> 48 #include <dev/pci/igc_mac.h> 49 #include <dev/pci/igc_nvm.h> 50 #include <dev/pci/igc_phy.h> 51 #include <dev/pci/igc_regs.h> 52 53 struct igc_hw; 54 55 #define IGC_FUNC_1 1 56 57 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0 58 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3 59 60 enum igc_mac_type { 61 igc_undefined = 0, 62 igc_i225, 63 igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 64 }; 65 66 enum igc_media_type { 67 igc_media_type_unknown = 0, 68 igc_media_type_copper = 1, 69 igc_num_media_types 70 }; 71 72 enum igc_nvm_type { 73 igc_nvm_unknown = 0, 74 igc_nvm_eeprom_spi, 75 igc_nvm_flash_hw, 76 igc_nvm_invm 77 }; 78 79 enum igc_phy_type { 80 igc_phy_unknown = 0, 81 igc_phy_none, 82 igc_phy_i225 83 }; 84 85 enum igc_bus_type { 86 igc_bus_type_unknown = 0, 87 igc_bus_type_pci, 88 igc_bus_type_pcix, 89 igc_bus_type_pci_express, 90 igc_bus_type_reserved 91 }; 92 93 enum igc_bus_speed { 94 igc_bus_speed_unknown = 0, 95 igc_bus_speed_33, 96 igc_bus_speed_66, 97 igc_bus_speed_100, 98 igc_bus_speed_120, 99 igc_bus_speed_133, 100 igc_bus_speed_2500, 101 igc_bus_speed_5000, 102 igc_bus_speed_reserved 103 }; 104 105 enum igc_bus_width { 106 igc_bus_width_unknown = 0, 107 igc_bus_width_pcie_x1, 108 igc_bus_width_pcie_x2, 109 igc_bus_width_pcie_x4 = 4, 110 igc_bus_width_pcie_x8 = 8, 111 igc_bus_width_32, 112 igc_bus_width_64, 113 igc_bus_width_reserved 114 }; 115 116 enum igc_fc_mode { 117 igc_fc_none = 0, 118 igc_fc_rx_pause, 119 igc_fc_tx_pause, 120 igc_fc_full, 121 igc_fc_default = 0xFF 122 }; 123 124 enum igc_ms_type { 125 igc_ms_hw_default = 0, 126 igc_ms_force_master, 127 igc_ms_force_slave, 128 igc_ms_auto 129 }; 130 131 enum igc_smart_speed { 132 igc_smart_speed_default = 0, 133 igc_smart_speed_on, 134 igc_smart_speed_off 135 }; 136 137 /* Receive Descriptor */ 138 struct igc_rx_desc { 139 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 140 uint64_t length; /* Length of data DMAed into data buffer */ 141 uint16_t csum; /* Packet checksum */ 142 uint8_t status; /* Descriptor status */ 143 uint8_t errors; /* Descriptor errors */ 144 uint16_t special; 145 }; 146 147 /* Receive Descriptor - Extended */ 148 union igc_rx_desc_extended { 149 struct { 150 uint64_t buffer_addr; 151 uint64_t reserved; 152 } read; 153 struct { 154 struct { 155 uint32_t mrq; /* Multiple Rx queues */ 156 union { 157 uint32_t rss; /* RSS hash */ 158 struct { 159 uint16_t ip_id; /* IP id */ 160 uint16_t csum; /* Packet checksum */ 161 } csum_ip; 162 } hi_dword; 163 } lower; 164 struct { 165 uint32_t status_error; /* ext status/error */ 166 uint16_t length; 167 uint16_t vlan; /* VLAN tag */ 168 } upper; 169 } wb; /* writeback */ 170 }; 171 172 /* Transmit Descriptor */ 173 struct igc_tx_desc { 174 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 175 union { 176 uint32_t data; 177 struct { 178 uint16_t length; /* Data buffer length */ 179 uint8_t cso; /* Checksum offset */ 180 uint8_t cmd; /* Descriptor control */ 181 } flags; 182 } lower; 183 union { 184 uint32_t data; 185 struct { 186 uint8_t status; /* Descriptor status */ 187 uint8_t css; /* Checksum start */ 188 uint16_t special; 189 } fields; 190 } upper; 191 }; 192 193 /* Function pointers for the MAC. */ 194 struct igc_mac_operations { 195 int (*init_params)(struct igc_hw *); 196 int (*check_for_link)(struct igc_hw *); 197 void (*clear_hw_cntrs)(struct igc_hw *); 198 void (*clear_vfta)(struct igc_hw *); 199 int (*get_bus_info)(struct igc_hw *); 200 void (*set_lan_id)(struct igc_hw *); 201 int (*get_link_up_info)(struct igc_hw *, uint16_t *, uint16_t *); 202 void (*update_mc_addr_list)(struct igc_hw *, uint8_t *, uint32_t); 203 int (*reset_hw)(struct igc_hw *); 204 int (*init_hw)(struct igc_hw *); 205 int (*setup_link)(struct igc_hw *); 206 int (*setup_physical_interface)(struct igc_hw *); 207 void (*write_vfta)(struct igc_hw *, uint32_t, uint32_t); 208 void (*config_collision_dist)(struct igc_hw *); 209 int (*rar_set)(struct igc_hw *, uint8_t *, uint32_t); 210 int (*read_mac_addr)(struct igc_hw *); 211 int (*validate_mdi_setting)(struct igc_hw *); 212 int (*acquire_swfw_sync)(struct igc_hw *, uint16_t); 213 void (*release_swfw_sync)(struct igc_hw *, uint16_t); 214 }; 215 216 /* When to use various PHY register access functions: 217 * 218 * Func Caller 219 * Function Does Does When to use 220 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 221 * X_reg L,P,A n/a for simple PHY reg accesses 222 * X_reg_locked P,A L for multiple accesses of different regs 223 * on different pages 224 * X_reg_page A L,P for multiple accesses of different regs 225 * on the same page 226 * 227 * Where X=[read|write], L=locking, P=sets page, A=register access 228 * 229 */ 230 struct igc_phy_operations { 231 int (*init_params)(struct igc_hw *); 232 int (*acquire)(struct igc_hw *); 233 int (*check_reset_block)(struct igc_hw *); 234 int (*force_speed_duplex)(struct igc_hw *); 235 int (*get_info)(struct igc_hw *); 236 int (*set_page)(struct igc_hw *, uint16_t); 237 int (*read_reg)(struct igc_hw *, uint32_t, uint16_t *); 238 int (*read_reg_locked)(struct igc_hw *, uint32_t, uint16_t *); 239 int (*read_reg_page)(struct igc_hw *, uint32_t, uint16_t *); 240 void (*release)(struct igc_hw *); 241 int (*reset)(struct igc_hw *); 242 int (*set_d0_lplu_state)(struct igc_hw *, bool); 243 int (*set_d3_lplu_state)(struct igc_hw *, bool); 244 int (*write_reg)(struct igc_hw *, uint32_t, uint16_t); 245 int (*write_reg_locked)(struct igc_hw *, uint32_t, uint16_t); 246 int (*write_reg_page)(struct igc_hw *, uint32_t, uint16_t); 247 void (*power_up)(struct igc_hw *); 248 void (*power_down)(struct igc_hw *); 249 }; 250 251 /* Function pointers for the NVM. */ 252 struct igc_nvm_operations { 253 int (*init_params)(struct igc_hw *); 254 int (*acquire)(struct igc_hw *); 255 int (*read)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 256 void (*release)(struct igc_hw *); 257 void (*reload)(struct igc_hw *); 258 int (*update)(struct igc_hw *); 259 int (*validate)(struct igc_hw *); 260 int (*write)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 261 }; 262 263 struct igc_mac_info { 264 struct igc_mac_operations ops; 265 uint8_t addr[ETHER_ADDR_LEN]; 266 uint8_t perm_addr[ETHER_ADDR_LEN]; 267 268 enum igc_mac_type type; 269 270 uint32_t mc_filter_type; 271 272 uint16_t current_ifs_val; 273 uint16_t ifs_max_val; 274 uint16_t ifs_min_val; 275 uint16_t ifs_ratio; 276 uint16_t ifs_step_size; 277 uint16_t mta_reg_count; 278 uint16_t uta_reg_count; 279 280 /* Maximum size of the MTA register table in all supported adapters */ 281 #define MAX_MTA_REG 128 282 uint32_t mta_shadow[MAX_MTA_REG]; 283 uint16_t rar_entry_count; 284 285 uint8_t forced_speed_duplex; 286 287 bool asf_firmware_present; 288 bool autoneg; 289 bool get_link_status; 290 uint32_t max_frame_size; 291 }; 292 293 struct igc_phy_info { 294 struct igc_phy_operations ops; 295 enum igc_phy_type type; 296 297 enum igc_smart_speed smart_speed; 298 299 uint32_t addr; 300 uint32_t id; 301 uint32_t reset_delay_us; /* in usec */ 302 uint32_t revision; 303 304 enum igc_media_type media_type; 305 306 uint16_t autoneg_advertised; 307 uint16_t autoneg_mask; 308 309 uint8_t mdix; 310 311 bool polarity_correction; 312 bool speed_downgraded; 313 bool autoneg_wait_to_complete; 314 }; 315 316 struct igc_nvm_info { 317 struct igc_nvm_operations ops; 318 enum igc_nvm_type type; 319 320 uint16_t word_size; 321 uint16_t delay_usec; 322 uint16_t address_bits; 323 uint16_t opcode_bits; 324 uint16_t page_size; 325 }; 326 327 struct igc_bus_info { 328 enum igc_bus_type type; 329 enum igc_bus_speed speed; 330 enum igc_bus_width width; 331 332 uint16_t func; 333 uint16_t pci_cmd_word; 334 }; 335 336 struct igc_fc_info { 337 uint32_t high_water; 338 uint32_t low_water; 339 uint16_t pause_time; 340 uint16_t refresh_time; 341 bool send_xon; 342 bool strict_ieee; 343 enum igc_fc_mode current_mode; 344 enum igc_fc_mode requested_mode; 345 }; 346 347 struct igc_dev_spec_i225 { 348 bool eee_disable; 349 bool clear_semaphore_once; 350 uint32_t mtu; 351 }; 352 353 struct igc_hw { 354 void *back; 355 356 uint8_t *hw_addr; 357 358 struct igc_mac_info mac; 359 struct igc_fc_info fc; 360 struct igc_phy_info phy; 361 struct igc_nvm_info nvm; 362 struct igc_bus_info bus; 363 364 union { 365 struct igc_dev_spec_i225 _i225; 366 } dev_spec; 367 368 uint16_t device_id; 369 }; 370 371 #endif /* _IGC_HW_H_ */ 372