1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <asm/processor.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_helper.h>
37
38 /**
39 * _wait_for - magic (register) wait macro
40 *
41 * Does the right thing for modeset paths when run under kdgb or similar atomic
42 * contexts. Note that it's important that we check the condition again after
43 * having timed out, since the timeout could be due to preemption or similar and
44 * we've never had a chance to check the condition before the timeout.
45 */
46 #ifdef __NetBSD__
47 #define _wait_for(COND, MS, W) ({ \
48 int ret__ = 0; \
49 if (cold) { \
50 int ms = (MS); \
51 while (!(COND)) { \
52 if (--ms < 0) { \
53 DELAY(1000); \
54 if (!(COND)) \
55 ret__ = -ETIMEDOUT; \
56 break; \
57 } \
58 DELAY(1000); \
59 } \
60 } else { \
61 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
62 while (!(COND)) { \
63 if (time_after(jiffies, timeout__)) { \
64 if (!(COND)) \
65 ret__ = -ETIMEDOUT; \
66 break; \
67 } \
68 if ((W) && drm_can_sleep()) { \
69 msleep(W); \
70 } else { \
71 DELAY(1000); \
72 } \
73 } \
74 } \
75 ret__; \
76 })
77 #else /* !NetBSD */
78 #define _wait_for(COND, MS, W) ({ \
79 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
80 int ret__ = 0; \
81 while (!(COND)) { \
82 if (time_after(jiffies, timeout__)) { \
83 if (!(COND)) \
84 ret__ = -ETIMEDOUT; \
85 break; \
86 } \
87 if (W && drm_can_sleep()) { \
88 msleep(W); \
89 } else { \
90 cpu_relax(); \
91 } \
92 } \
93 ret__; \
94 })
95 #endif /* NetBSD */
96
97 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
98 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
99 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
100 DIV_ROUND_UP((US), 1000), 0)
101
102 #define KHz(x) (1000 * (x))
103 #define MHz(x) KHz(1000 * (x))
104
105 /*
106 * Display related stuff
107 */
108
109 /* store information about an Ixxx DVO */
110 /* The i830->i865 use multiple DVOs with multiple i2cs */
111 /* the i915, i945 have a single sDVO i2c bus - which is different */
112 #define MAX_OUTPUTS 6
113 /* maximum connectors per crtcs in the mode set */
114
115 /* Maximum cursor sizes */
116 #define GEN2_CURSOR_WIDTH 64
117 #define GEN2_CURSOR_HEIGHT 64
118 #define CURSOR_WIDTH 256
119 #define CURSOR_HEIGHT 256
120
121 #define INTEL_I2C_BUS_DVO 1
122 #define INTEL_I2C_BUS_SDVO 2
123
124 /* these are outputs from the chip - integrated only
125 external chips are via DVO or SDVO output */
126 #define INTEL_OUTPUT_UNUSED 0
127 #define INTEL_OUTPUT_ANALOG 1
128 #define INTEL_OUTPUT_DVO 2
129 #define INTEL_OUTPUT_SDVO 3
130 #define INTEL_OUTPUT_LVDS 4
131 #define INTEL_OUTPUT_TVOUT 5
132 #define INTEL_OUTPUT_HDMI 6
133 #define INTEL_OUTPUT_DISPLAYPORT 7
134 #define INTEL_OUTPUT_EDP 8
135 #define INTEL_OUTPUT_DSI 9
136 #define INTEL_OUTPUT_UNKNOWN 10
137
138 #define INTEL_DVO_CHIP_NONE 0
139 #define INTEL_DVO_CHIP_LVDS 1
140 #define INTEL_DVO_CHIP_TMDS 2
141 #define INTEL_DVO_CHIP_TVOUT 4
142
143 #define INTEL_DSI_COMMAND_MODE 0
144 #define INTEL_DSI_VIDEO_MODE 1
145
146 struct intel_framebuffer {
147 struct drm_framebuffer base;
148 struct drm_i915_gem_object *obj;
149 };
150
151 struct intel_fbdev {
152 struct drm_fb_helper helper;
153 struct intel_framebuffer *fb;
154 struct list_head fbdev_list;
155 struct drm_display_mode *our_mode;
156 int preferred_bpp;
157 };
158
159 struct intel_encoder {
160 struct drm_encoder base;
161 /*
162 * The new crtc this encoder will be driven from. Only differs from
163 * base->crtc while a modeset is in progress.
164 */
165 struct intel_crtc *new_crtc;
166
167 int type;
168 unsigned int cloneable;
169 bool connectors_active;
170 void (*hot_plug)(struct intel_encoder *);
171 bool (*compute_config)(struct intel_encoder *,
172 struct intel_crtc_config *);
173 void (*pre_pll_enable)(struct intel_encoder *);
174 void (*pre_enable)(struct intel_encoder *);
175 void (*enable)(struct intel_encoder *);
176 void (*mode_set)(struct intel_encoder *intel_encoder);
177 void (*disable)(struct intel_encoder *);
178 void (*post_disable)(struct intel_encoder *);
179 /* Read out the current hw state of this connector, returning true if
180 * the encoder is active. If the encoder is enabled it also set the pipe
181 * it is connected to in the pipe parameter. */
182 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe);
183 /* Reconstructs the equivalent mode flags for the current hardware
184 * state. This must be called _after_ display->get_pipe_config has
185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
186 * be set correctly before calling this function. */
187 void (*get_config)(struct intel_encoder *,
188 struct intel_crtc_config *pipe_config);
189 int crtc_mask;
190 enum hpd_pin hpd_pin;
191 };
192
193 struct intel_panel {
194 struct drm_display_mode *fixed_mode;
195 struct drm_display_mode *downclock_mode;
196 int fitting_mode;
197
198 /* backlight */
199 struct {
200 bool present;
201 u32 level;
202 u32 max;
203 bool enabled;
204 bool combination_mode; /* gen 2/4 only */
205 bool active_low_pwm;
206 struct backlight_device *device;
207 } backlight;
208 };
209
210 struct intel_connector {
211 struct drm_connector base;
212 /*
213 * The fixed encoder this connector is connected to.
214 */
215 struct intel_encoder *encoder;
216
217 /*
218 * The new encoder this connector will be driven. Only differs from
219 * encoder while a modeset is in progress.
220 */
221 struct intel_encoder *new_encoder;
222
223 /* Reads out the current hw, returning true if the connector is enabled
224 * and active (i.e. dpms ON state). */
225 bool (*get_hw_state)(struct intel_connector *);
226
227 /*
228 * Removes all interfaces through which the connector is accessible
229 * - like sysfs, debugfs entries -, so that no new operations can be
230 * started on the connector. Also makes sure all currently pending
231 * operations finish before returing.
232 */
233 void (*unregister)(struct intel_connector *);
234
235 /* Panel info for eDP and LVDS */
236 struct intel_panel panel;
237
238 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
239 struct edid *edid;
240
241 /* since POLL and HPD connectors may use the same HPD line keep the native
242 state of connector->polled in case hotplug storm detection changes it */
243 u8 polled;
244 };
245
246 typedef struct dpll {
247 /* given values */
248 int n;
249 int m1, m2;
250 int p1, p2;
251 /* derived values */
252 int dot;
253 int vco;
254 int m;
255 int p;
256 } intel_clock_t;
257
258 struct intel_plane_config {
259 bool tiled;
260 int size;
261 u32 base;
262 };
263
264 struct intel_crtc_config {
265 /**
266 * quirks - bitfield with hw state readout quirks
267 *
268 * For various reasons the hw state readout code might not be able to
269 * completely faithfully read out the current state. These cases are
270 * tracked with quirk flags so that fastboot and state checker can act
271 * accordingly.
272 */
273 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
274 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
275 unsigned long quirks;
276
277 /* User requested mode, only valid as a starting point to
278 * compute adjusted_mode, except in the case of (S)DVO where
279 * it's also for the output timings of the (S)DVO chip.
280 * adjusted_mode will then correspond to the S(DVO) chip's
281 * preferred input timings. */
282 struct drm_display_mode requested_mode;
283 /* Actual pipe timings ie. what we program into the pipe timing
284 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
285 struct drm_display_mode adjusted_mode;
286
287 /* Pipe source size (ie. panel fitter input size)
288 * All planes will be positioned inside this space,
289 * and get clipped at the edges. */
290 int pipe_src_w, pipe_src_h;
291
292 /* Whether to set up the PCH/FDI. Note that we never allow sharing
293 * between pch encoders and cpu encoders. */
294 bool has_pch_encoder;
295
296 /* CPU Transcoder for the pipe. Currently this can only differ from the
297 * pipe on Haswell (where we have a special eDP transcoder). */
298 enum transcoder cpu_transcoder;
299
300 /*
301 * Use reduced/limited/broadcast rbg range, compressing from the full
302 * range fed into the crtcs.
303 */
304 bool limited_color_range;
305
306 /* DP has a bunch of special case unfortunately, so mark the pipe
307 * accordingly. */
308 bool has_dp_encoder;
309
310 /*
311 * Enable dithering, used when the selected pipe bpp doesn't match the
312 * plane bpp.
313 */
314 bool dither;
315
316 /* Controls for the clock computation, to override various stages. */
317 bool clock_set;
318
319 /* SDVO TV has a bunch of special case. To make multifunction encoders
320 * work correctly, we need to track this at runtime.*/
321 bool sdvo_tv_clock;
322
323 /*
324 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
325 * required. This is set in the 2nd loop of calling encoder's
326 * ->compute_config if the first pick doesn't work out.
327 */
328 bool bw_constrained;
329
330 /* Settings for the intel dpll used on pretty much everything but
331 * haswell. */
332 struct dpll dpll;
333
334 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
335 enum intel_dpll_id shared_dpll;
336
337 /* Actual register state of the dpll, for shared dpll cross-checking. */
338 struct intel_dpll_hw_state dpll_hw_state;
339
340 int pipe_bpp;
341 struct intel_link_m_n dp_m_n;
342
343 /*
344 * Frequence the dpll for the port should run at. Differs from the
345 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
346 * already multiplied by pixel_multiplier.
347 */
348 int port_clock;
349
350 /* Used by SDVO (and if we ever fix it, HDMI). */
351 unsigned pixel_multiplier;
352
353 /* Panel fitter controls for gen2-gen4 + VLV */
354 struct {
355 u32 control;
356 u32 pgm_ratios;
357 u32 lvds_border_bits;
358 } gmch_pfit;
359
360 /* Panel fitter placement and size for Ironlake+ */
361 struct {
362 u32 pos;
363 u32 size;
364 bool enabled;
365 } pch_pfit;
366
367 /* FDI configuration, only valid if has_pch_encoder is set. */
368 int fdi_lanes;
369 struct intel_link_m_n fdi_m_n;
370
371 bool ips_enabled;
372
373 bool double_wide;
374 };
375
376 struct intel_pipe_wm {
377 struct intel_wm_level wm[5];
378 uint32_t linetime;
379 bool fbc_wm_enabled;
380 };
381
382 struct intel_crtc {
383 struct drm_crtc base;
384 enum i915_pipe pipe;
385 enum plane plane;
386 u8 lut_r[256], lut_g[256], lut_b[256];
387 /*
388 * Whether the crtc and the connected output pipeline is active. Implies
389 * that crtc->enabled is set, i.e. the current mode configuration has
390 * some outputs connected to this crtc.
391 */
392 bool active;
393 unsigned long enabled_power_domains;
394 bool eld_vld;
395 bool primary_enabled; /* is the primary plane (partially) visible? */
396 bool lowfreq_avail;
397 struct intel_overlay *overlay;
398 struct intel_unpin_work *unpin_work;
399
400 atomic_t unpin_work_count;
401
402 /* Display surface base address adjustement for pageflips. Note that on
403 * gen4+ this only adjusts up to a tile, offsets within a tile are
404 * handled in the hw itself (with the TILEOFF register). */
405 unsigned long dspaddr_offset;
406
407 struct drm_i915_gem_object *cursor_bo;
408 uint32_t cursor_addr;
409 int16_t cursor_x, cursor_y;
410 int16_t cursor_width, cursor_height;
411 int16_t max_cursor_width, max_cursor_height;
412 bool cursor_visible;
413
414 struct intel_plane_config plane_config;
415 struct intel_crtc_config config;
416 struct intel_crtc_config *new_config;
417 bool new_enabled;
418
419 uint32_t ddi_pll_sel;
420
421 /* reset counter value when the last flip was submitted */
422 unsigned int reset_counter;
423
424 /* Access to these should be protected by dev_priv->irq_lock. */
425 bool cpu_fifo_underrun_disabled;
426 bool pch_fifo_underrun_disabled;
427
428 /* per-pipe watermark state */
429 struct {
430 /* watermarks currently being used */
431 struct intel_pipe_wm active;
432 } wm;
433 };
434
435 struct intel_plane_wm_parameters {
436 uint32_t horiz_pixels;
437 uint8_t bytes_per_pixel;
438 bool enabled;
439 bool scaled;
440 };
441
442 struct intel_plane {
443 struct drm_plane base;
444 int plane;
445 enum i915_pipe pipe;
446 struct drm_i915_gem_object *obj;
447 bool can_scale;
448 int max_downscale;
449 u32 lut_r[1024], lut_g[1024], lut_b[1024];
450 int crtc_x, crtc_y;
451 unsigned int crtc_w, crtc_h;
452 uint32_t src_x, src_y;
453 uint32_t src_w, src_h;
454
455 /* Since we need to change the watermarks before/after
456 * enabling/disabling the planes, we need to store the parameters here
457 * as the other pieces of the struct may not reflect the values we want
458 * for the watermark calculations. Currently only Haswell uses this.
459 */
460 struct intel_plane_wm_parameters wm;
461
462 void (*update_plane)(struct drm_plane *plane,
463 struct drm_crtc *crtc,
464 struct drm_framebuffer *fb,
465 struct drm_i915_gem_object *obj,
466 int crtc_x, int crtc_y,
467 unsigned int crtc_w, unsigned int crtc_h,
468 uint32_t x, uint32_t y,
469 uint32_t src_w, uint32_t src_h);
470 void (*disable_plane)(struct drm_plane *plane,
471 struct drm_crtc *crtc);
472 int (*update_colorkey)(struct drm_plane *plane,
473 struct drm_intel_sprite_colorkey *key);
474 void (*get_colorkey)(struct drm_plane *plane,
475 struct drm_intel_sprite_colorkey *key);
476 };
477
478 struct intel_watermark_params {
479 unsigned long fifo_size;
480 unsigned long max_wm;
481 unsigned long default_wm;
482 unsigned long guard_size;
483 unsigned long cacheline_size;
484 };
485
486 struct cxsr_latency {
487 int is_desktop;
488 int is_ddr3;
489 unsigned long fsb_freq;
490 unsigned long mem_freq;
491 unsigned long display_sr;
492 unsigned long display_hpll_disable;
493 unsigned long cursor_sr;
494 unsigned long cursor_hpll_disable;
495 };
496
497 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
498 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
499 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
500 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
501 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
502
503 struct intel_hdmi {
504 u32 hdmi_reg;
505 int ddc_bus;
506 uint32_t color_range;
507 bool color_range_auto;
508 bool has_hdmi_sink;
509 bool has_audio;
510 enum hdmi_force_audio force_audio;
511 bool rgb_quant_range_selectable;
512 void (*write_infoframe)(struct drm_encoder *encoder,
513 enum hdmi_infoframe_type type,
514 const void *frame, ssize_t len);
515 void (*set_infoframes)(struct drm_encoder *encoder,
516 struct drm_display_mode *adjusted_mode);
517 };
518
519 #define DP_MAX_DOWNSTREAM_PORTS 0x10
520
521 struct intel_dp {
522 uint32_t output_reg;
523 uint32_t aux_ch_ctl_reg;
524 uint32_t DP;
525 bool has_audio;
526 enum hdmi_force_audio force_audio;
527 uint32_t color_range;
528 bool color_range_auto;
529 uint8_t link_bw;
530 uint8_t lane_count;
531 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
532 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
533 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
534 struct drm_dp_aux aux;
535 uint8_t train_set[4];
536 int panel_power_up_delay;
537 int panel_power_down_delay;
538 int panel_power_cycle_delay;
539 int backlight_on_delay;
540 int backlight_off_delay;
541 struct delayed_work panel_vdd_work;
542 bool want_panel_vdd;
543 unsigned long last_power_cycle;
544 unsigned long last_power_on;
545 unsigned long last_backlight_off;
546 bool psr_setup_done;
547 bool use_tps3;
548 struct intel_connector *attached_connector;
549
550 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
551 /*
552 * This function returns the value we have to program the AUX_CTL
553 * register with to kick off an AUX transaction.
554 */
555 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
556 bool has_aux_irq,
557 int send_bytes,
558 uint32_t aux_clock_divider);
559 };
560
561 struct intel_digital_port {
562 struct intel_encoder base;
563 enum port port;
564 u32 saved_port_bits;
565 struct intel_dp dp;
566 struct intel_hdmi hdmi;
567 };
568
569 static inline int
vlv_dport_to_channel(struct intel_digital_port * dport)570 vlv_dport_to_channel(struct intel_digital_port *dport)
571 {
572 switch (dport->port) {
573 case PORT_B:
574 return DPIO_CH0;
575 case PORT_C:
576 return DPIO_CH1;
577 default:
578 BUG();
579 }
580 }
581
582 static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device * dev,int pipe)583 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
584 {
585 struct drm_i915_private *dev_priv = dev->dev_private;
586 return dev_priv->pipe_to_crtc_mapping[pipe];
587 }
588
589 static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device * dev,int plane)590 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
591 {
592 struct drm_i915_private *dev_priv = dev->dev_private;
593 return dev_priv->plane_to_crtc_mapping[plane];
594 }
595
596 struct intel_unpin_work {
597 struct work_struct work;
598 struct drm_crtc *crtc;
599 struct drm_i915_gem_object *old_fb_obj;
600 struct drm_i915_gem_object *pending_flip_obj;
601 struct drm_pending_vblank_event *event;
602 atomic_t pending;
603 #define INTEL_FLIP_INACTIVE 0
604 #define INTEL_FLIP_PENDING 1
605 #define INTEL_FLIP_COMPLETE 2
606 bool enable_stall_check;
607 };
608
609 struct intel_set_config {
610 struct drm_encoder **save_connector_encoders;
611 struct drm_crtc **save_encoder_crtcs;
612 bool *save_crtc_enabled;
613
614 bool fb_changed;
615 bool mode_changed;
616 };
617
618 struct intel_load_detect_pipe {
619 struct drm_framebuffer *release_fb;
620 bool load_detect_temp;
621 int dpms_mode;
622 };
623
624 static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector * connector)625 intel_attached_encoder(struct drm_connector *connector)
626 {
627 return to_intel_connector(connector)->encoder;
628 }
629
630 static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder * encoder)631 enc_to_dig_port(struct drm_encoder *encoder)
632 {
633 return container_of(encoder, struct intel_digital_port, base.base);
634 }
635
enc_to_intel_dp(struct drm_encoder * encoder)636 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
637 {
638 return &enc_to_dig_port(encoder)->dp;
639 }
640
641 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)642 dp_to_dig_port(struct intel_dp *intel_dp)
643 {
644 return container_of(intel_dp, struct intel_digital_port, dp);
645 }
646
647 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)648 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
649 {
650 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
651 }
652
653
654 /* i915_irq.c */
655 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
656 enum i915_pipe pipe, bool enable);
657 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
658 enum i915_pipe pipe, bool enable);
659 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
660 enum transcoder pch_transcoder,
661 bool enable);
662 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
663 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
664 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
665 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
666 void hsw_runtime_pm_disable_interrupts(struct drm_device *dev);
667 void hsw_runtime_pm_restore_interrupts(struct drm_device *dev);
668
669
670 /* intel_crt.c */
671 void intel_crt_init(struct drm_device *dev);
672
673
674 /* intel_ddi.c */
675 void intel_prepare_ddi(struct drm_device *dev);
676 void hsw_fdi_link_train(struct drm_crtc *crtc);
677 void intel_ddi_init(struct drm_device *dev, enum port port);
678 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
679 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe);
680 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
681 void intel_ddi_pll_init(struct drm_device *dev);
682 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
683 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
684 enum transcoder cpu_transcoder);
685 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
686 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
687 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
688 bool intel_ddi_pll_select(struct intel_crtc *crtc);
689 void intel_ddi_pll_enable(struct intel_crtc *crtc);
690 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
691 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
692 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
693 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
694 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
695 void intel_ddi_get_config(struct intel_encoder *encoder,
696 struct intel_crtc_config *pipe_config);
697
698
699 /* intel_display.c */
700 const char *intel_output_name(int output);
701 bool intel_has_pending_fb_unpin(struct drm_device *dev);
702 int intel_pch_rawclk(struct drm_device *dev);
703 void intel_mark_busy(struct drm_device *dev);
704 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
705 struct intel_ring_buffer *ring);
706 void intel_mark_idle(struct drm_device *dev);
707 void intel_crtc_restore_mode(struct drm_crtc *crtc);
708 void intel_crtc_update_dpms(struct drm_crtc *crtc);
709 void intel_encoder_destroy(struct drm_encoder *encoder);
710 void intel_connector_dpms(struct drm_connector *, int mode);
711 bool intel_connector_get_hw_state(struct intel_connector *connector);
712 void intel_modeset_check_state(struct drm_device *dev);
713 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
714 struct intel_digital_port *port);
715 void intel_connector_attach_encoder(struct intel_connector *connector,
716 struct intel_encoder *encoder);
717 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
718 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
719 struct drm_crtc *crtc);
720 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector);
721 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
722 struct drm_file *file_priv);
723 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
724 enum i915_pipe pipe);
725 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
726 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
727 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
728 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
729 struct intel_digital_port *dport);
730 bool intel_get_load_detect_pipe(struct drm_connector *connector,
731 struct drm_display_mode *mode,
732 struct intel_load_detect_pipe *old);
733 void intel_release_load_detect_pipe(struct drm_connector *connector,
734 struct intel_load_detect_pipe *old);
735 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
736 struct drm_i915_gem_object *obj,
737 struct intel_ring_buffer *pipelined);
738 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
739 struct drm_framebuffer *
740 __intel_framebuffer_create(struct drm_device *dev,
741 struct drm_mode_fb_cmd2 *mode_cmd,
742 struct drm_i915_gem_object *obj);
743 void intel_prepare_page_flip(struct drm_device *dev, int plane);
744 void intel_finish_page_flip(struct drm_device *dev, int pipe);
745 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
746 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
747 void assert_shared_dpll(struct drm_i915_private *dev_priv,
748 struct intel_shared_dpll *pll,
749 bool state);
750 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
751 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
752 void assert_pll(struct drm_i915_private *dev_priv,
753 enum i915_pipe pipe, bool state);
754 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
755 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
756 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
757 enum i915_pipe pipe, bool state);
758 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
759 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
760 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state);
761 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
762 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
763 void intel_write_eld(struct drm_encoder *encoder,
764 struct drm_display_mode *mode);
765 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
766 unsigned int tiling_mode,
767 unsigned int bpp,
768 unsigned int pitch);
769 void intel_display_handle_reset(struct drm_device *dev);
770 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
771 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
772 void intel_dp_get_m_n(struct intel_crtc *crtc,
773 struct intel_crtc_config *pipe_config);
774 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
775 void
776 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
777 int dotclock);
778 bool intel_crtc_active(struct drm_crtc *crtc);
779 void hsw_enable_ips(struct intel_crtc *crtc);
780 void hsw_disable_ips(struct intel_crtc *crtc);
781 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
782 enum intel_display_power_domain
783 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
784 int valleyview_get_vco(struct drm_i915_private *dev_priv);
785 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
786 struct intel_crtc_config *pipe_config);
787 int intel_format_to_fourcc(int format);
788
789 /* intel_dp.c */
790 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
791 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
792 struct intel_connector *intel_connector);
793 void intel_dp_start_link_train(struct intel_dp *intel_dp);
794 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
795 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
796 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
797 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
798 void intel_dp_check_link_status(struct intel_dp *intel_dp);
799 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
800 bool intel_dp_compute_config(struct intel_encoder *encoder,
801 struct intel_crtc_config *pipe_config);
802 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
803 void intel_edp_backlight_on(struct intel_dp *intel_dp);
804 void intel_edp_backlight_off(struct intel_dp *intel_dp);
805 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
806 void intel_edp_panel_on(struct intel_dp *intel_dp);
807 void intel_edp_panel_off(struct intel_dp *intel_dp);
808 void intel_edp_psr_enable(struct intel_dp *intel_dp);
809 void intel_edp_psr_disable(struct intel_dp *intel_dp);
810 void intel_edp_psr_update(struct drm_device *dev);
811
812
813 /* intel_dsi.c */
814 bool intel_dsi_init(struct drm_device *dev);
815
816
817 /* intel_dvo.c */
818 void intel_dvo_init(struct drm_device *dev);
819
820
821 /* legacy fbdev emulation in intel_fbdev.c */
822 #ifdef CONFIG_DRM_I915_FBDEV
823 extern int intel_fbdev_init(struct drm_device *dev);
824 extern void intel_fbdev_initial_config(struct drm_device *dev);
825 extern void intel_fbdev_fini(struct drm_device *dev);
826 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
827 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
828 extern void intel_fbdev_restore_mode(struct drm_device *dev);
829 #else
intel_fbdev_init(struct drm_device * dev)830 static inline int intel_fbdev_init(struct drm_device *dev)
831 {
832 return 0;
833 }
834
intel_fbdev_initial_config(struct drm_device * dev)835 static inline void intel_fbdev_initial_config(struct drm_device *dev)
836 {
837 }
838
intel_fbdev_fini(struct drm_device * dev)839 static inline void intel_fbdev_fini(struct drm_device *dev)
840 {
841 }
842
intel_fbdev_set_suspend(struct drm_device * dev,int state)843 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
844 {
845 }
846
intel_fbdev_restore_mode(struct drm_device * dev)847 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
848 {
849 }
850 #endif
851 #ifdef __NetBSD__
852 extern int intel_genfb_attach(struct drm_device *, struct drm_fb_helper *,
853 const struct drm_fb_helper_surface_size *);
854 #endif
855
856 /* intel_hdmi.c */
857 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
858 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
859 struct intel_connector *intel_connector);
860 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
861 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
862 struct intel_crtc_config *pipe_config);
863
864
865 /* intel_lvds.c */
866 void intel_lvds_init(struct drm_device *dev);
867 bool intel_is_dual_link_lvds(struct drm_device *dev);
868
869
870 /* intel_modes.c */
871 int intel_connector_update_modes(struct drm_connector *connector,
872 struct edid *edid);
873 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
874 void intel_attach_force_audio_property(struct drm_connector *connector);
875 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
876
877
878 /* intel_overlay.c */
879 void intel_setup_overlay(struct drm_device *dev);
880 void intel_cleanup_overlay(struct drm_device *dev);
881 int intel_overlay_switch_off(struct intel_overlay *overlay);
882 int intel_overlay_put_image(struct drm_device *dev, void *data,
883 struct drm_file *file_priv);
884 int intel_overlay_attrs(struct drm_device *dev, void *data,
885 struct drm_file *file_priv);
886
887
888 /* intel_panel.c */
889 int intel_panel_init(struct intel_panel *panel,
890 struct drm_display_mode *fixed_mode,
891 struct drm_display_mode *downclock_mode);
892 void intel_panel_fini(struct intel_panel *panel);
893 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
894 struct drm_display_mode *adjusted_mode);
895 void intel_pch_panel_fitting(struct intel_crtc *crtc,
896 struct intel_crtc_config *pipe_config,
897 int fitting_mode);
898 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
899 struct intel_crtc_config *pipe_config,
900 int fitting_mode);
901 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
902 u32 max);
903 int intel_panel_setup_backlight(struct drm_connector *connector);
904 void intel_panel_enable_backlight(struct intel_connector *connector);
905 void intel_panel_disable_backlight(struct intel_connector *connector);
906 void intel_panel_destroy_backlight(struct drm_connector *connector);
907 void intel_panel_init_backlight_funcs(struct drm_device *dev);
908 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
909 extern struct drm_display_mode *intel_find_panel_downclock(
910 struct drm_device *dev,
911 struct drm_display_mode *fixed_mode,
912 struct drm_connector *connector);
913
914 /* intel_pm.c */
915 void intel_init_clock_gating(struct drm_device *dev);
916 void intel_suspend_hw(struct drm_device *dev);
917 void intel_update_watermarks(struct drm_crtc *crtc);
918 void intel_update_sprite_watermarks(struct drm_plane *plane,
919 struct drm_crtc *crtc,
920 uint32_t sprite_width, int pixel_size,
921 bool enabled, bool scaled);
922 void intel_init_pm(struct drm_device *dev);
923 void intel_pm_setup(struct drm_device *dev);
924 bool intel_fbc_enabled(struct drm_device *dev);
925 void intel_update_fbc(struct drm_device *dev);
926 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
927 void intel_gpu_ips_teardown(void);
928 int intel_power_domains_init(struct drm_i915_private *);
929 void intel_power_domains_remove(struct drm_i915_private *);
930 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
931 enum intel_display_power_domain domain);
932 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
933 enum intel_display_power_domain domain);
934 void intel_display_power_get(struct drm_i915_private *dev_priv,
935 enum intel_display_power_domain domain);
936 void intel_display_power_put(struct drm_i915_private *dev_priv,
937 enum intel_display_power_domain domain);
938 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
939 void intel_init_gt_powersave(struct drm_device *dev);
940 void intel_cleanup_gt_powersave(struct drm_device *dev);
941 void intel_enable_gt_powersave(struct drm_device *dev);
942 void intel_disable_gt_powersave(struct drm_device *dev);
943 void ironlake_teardown_rc6(struct drm_device *dev);
944 void gen6_update_ring_freq(struct drm_device *dev);
945 void gen6_rps_idle(struct drm_i915_private *dev_priv);
946 void gen6_rps_boost(struct drm_i915_private *dev_priv);
947 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
948 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
949 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
950 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
951 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
952 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
953 void ilk_wm_get_hw_state(struct drm_device *dev);
954
955
956 /* intel_sdvo.c */
957 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
958
959
960 /* intel_sprite.c */
961 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane);
962 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
963 enum plane plane);
964 void intel_plane_restore(struct drm_plane *plane);
965 void intel_plane_disable(struct drm_plane *plane);
966 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
967 struct drm_file *file_priv);
968 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
969 struct drm_file *file_priv);
970
971
972 /* intel_tv.c */
973 void intel_tv_init(struct drm_device *dev);
974
975 #endif /* __INTEL_DRV_H__ */
976