xref: /openbsd/sys/arch/hppa/dev/siop_sgc.c (revision 32ffafad)
1 /*	$OpenBSD: siop_sgc.c,v 1.3 2024/05/22 14:25:47 jsg Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Mark Kettenis
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #include <sys/param.h>
20 #include <sys/device.h>
21 #include <sys/systm.h>
22 
23 #include <machine/autoconf.h>
24 #include <machine/bus.h>
25 #include <machine/iomod.h>
26 
27 #include <scsi/scsi_all.h>
28 #include <scsi/scsiconf.h>
29 
30 #include <dev/ic/siopreg.h>
31 #include <dev/ic/siopvar_common.h>
32 #include <dev/ic/siopvar.h>
33 
34 #include <hppa/dev/cpudevs.h>
35 
36 #define IO_II_INTEN		0x20000000
37 #define IO_II_PACKEN		0x10000000
38 #define IO_II_PREFETCHEN	0x08000000
39 
40 int siop_sgc_match(struct device *, void *, void *);
41 void siop_sgc_attach(struct device *, struct device *, void *);
42 void siop_sgc_reset(struct siop_common_softc *);
43 
44 u_int8_t siop_sgc_r1(void *, bus_space_handle_t, bus_size_t);
45 u_int16_t siop_sgc_r2(void *, bus_space_handle_t, bus_size_t);
46 void siop_sgc_w1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
47 void siop_sgc_w2(void *, bus_space_handle_t, bus_size_t, u_int16_t);
48 
49 struct siop_sgc_softc {
50 	struct siop_softc sc_siop;
51 	bus_space_tag_t sc_iot;
52 	bus_space_handle_t sc_ioh;
53 	struct hppa_bus_space_tag sc_bustag;
54 };
55 
56 const struct cfattach siop_gedoens_ca = {
57 	sizeof(struct siop_sgc_softc), siop_sgc_match, siop_sgc_attach
58 };
59 
60 int
siop_sgc_match(struct device * parent,void * match,void * aux)61 siop_sgc_match(struct device *parent, void *match, void *aux)
62 {
63 	struct confargs *ca = aux;
64 
65 	if (ca->ca_type.iodc_type != HPPA_TYPE_ADMA ||
66 	    ca->ca_type.iodc_sv_model != HPPA_ADMA_FWSCSI)
67 		return 0;
68 
69 	return 1;
70 }
71 
72 void
siop_sgc_attach(struct device * parent,struct device * self,void * aux)73 siop_sgc_attach(struct device *parent, struct device *self, void *aux)
74 {
75 	struct siop_sgc_softc *sc = (struct siop_sgc_softc *)self;
76 	struct confargs *ca = aux;
77 	volatile struct iomod *regs;
78 
79 	sc->sc_iot = ca->ca_iot;
80 	if (bus_space_map(sc->sc_iot, ca->ca_hpa,
81 	    IOMOD_HPASIZE, 0, &sc->sc_ioh)) {
82 		printf(": cannot map io space\n");
83 		return;
84 	}
85 
86 	sc->sc_bustag = *sc->sc_iot;
87 	sc->sc_bustag.hbt_r1 = siop_sgc_r1;
88 	sc->sc_bustag.hbt_r2 = siop_sgc_r2;
89 	sc->sc_bustag.hbt_w1 = siop_sgc_w1;
90 	sc->sc_bustag.hbt_w2 = siop_sgc_w2;
91 
92 	sc->sc_siop.sc_c.features = SF_CHIP_PF | SF_CHIP_BE | SF_BUS_WIDE;
93 	sc->sc_siop.sc_c.maxburst = 4;
94 	sc->sc_siop.sc_c.maxoff = 8;
95 	sc->sc_siop.sc_c.clock_div = 3;
96 	sc->sc_siop.sc_c.clock_period = 250;
97 	sc->sc_siop.sc_c.ram_size = 0;
98 
99 	sc->sc_siop.sc_c.sc_reset = siop_sgc_reset;
100 	sc->sc_siop.sc_c.sc_dmat = ca->ca_dmatag;
101 
102 	sc->sc_siop.sc_c.sc_rt = &sc->sc_bustag;
103 	bus_space_subregion(sc->sc_iot, sc->sc_ioh, IOMOD_DEVOFFSET,
104 	    IOMOD_HPASIZE - IOMOD_DEVOFFSET, &sc->sc_siop.sc_c.sc_rh);
105 
106 	regs = bus_space_vaddr(sc->sc_iot, sc->sc_ioh);
107 	regs->io_command = CMD_RESET;
108 	while ((regs->io_status & IO_ERR_MEM_RY) == 0)
109 		delay(100);
110 	regs->io_ii_rw = IO_II_PACKEN | IO_II_PREFETCHEN;
111 
112 	siop_sgc_reset(&sc->sc_siop.sc_c);
113 
114 	regs->io_eim = cpu_gethpa(0) | (31 - ca->ca_irq);
115 	regs->io_ii_rw |= IO_II_INTEN;
116 	cpu_intr_establish(IPL_BIO, ca->ca_irq, siop_intr, sc,
117 	    sc->sc_siop.sc_c.sc_dev.dv_xname);
118 
119 	printf(": NCR53C720 rev %d\n", bus_space_read_1(sc->sc_siop.sc_c.sc_rt,
120 	    sc->sc_siop.sc_c.sc_rh, SIOP_CTEST3) >> 4);
121 
122 	siop_attach(&sc->sc_siop);
123 }
124 
125 void
siop_sgc_reset(struct siop_common_softc * sc)126 siop_sgc_reset(struct siop_common_softc *sc)
127 {
128 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, DCNTL_EA);
129 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST0, CTEST0_EHP);
130 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, CTEST4_MUX);
131 
132 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0,
133 	    (0xc << STIME0_SEL_SHIFT));
134 }
135 
136 u_int8_t
siop_sgc_r1(void * v,bus_space_handle_t h,bus_size_t o)137 siop_sgc_r1(void *v, bus_space_handle_t h, bus_size_t o)
138 {
139 	return *(volatile u_int8_t *)(h + (o ^ 3));
140 }
141 
142 u_int16_t
siop_sgc_r2(void * v,bus_space_handle_t h,bus_size_t o)143 siop_sgc_r2(void *v, bus_space_handle_t h, bus_size_t o)
144 {
145 	if (o == SIOP_SIST0) {
146 		u_int16_t reg;
147 
148 		reg = siop_sgc_r1(v, h, SIOP_SIST0);
149 		reg |= siop_sgc_r1(v, h, SIOP_SIST1) << 8;
150 		return reg;
151 	}
152 	return *(volatile u_int16_t *)(h + (o ^ 2));
153 }
154 
155 void
siop_sgc_w1(void * v,bus_space_handle_t h,bus_size_t o,u_int8_t vv)156 siop_sgc_w1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv)
157 {
158 	*(volatile u_int8_t *)(h + (o ^ 3)) = vv;
159 }
160 
161 void
siop_sgc_w2(void * v,bus_space_handle_t h,bus_size_t o,u_int16_t vv)162 siop_sgc_w2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv)
163 {
164 	*(volatile u_int16_t *)(h + (o ^ 2)) = vv;
165 }
166